From d54e027a3867937f3cbe35c0785a77f6845e05f0 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Mon, 29 Jan 2024 11:04:06 +0700 Subject: [PATCH] dts: bindings: more typo correction and wording enhancement This change reflects further corrections and suggestions from @ajarmouni-st. Signed-off-by: Pisit Sawangvonganan --- dts/bindings/bluetooth/ambiq,bt-hci-spi.yaml | 6 +++--- dts/bindings/can/microchip,mcp251xfd.yaml | 2 +- dts/bindings/clock/st,stm32-rcc.yaml | 2 +- dts/bindings/dma/st,stm32-dma-v2.yaml | 2 +- dts/bindings/i2c/atmel,sam-i2c-twim.yaml | 2 +- dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml | 6 +++--- dts/bindings/net/wireless/gpio-radio-coex.yaml | 2 +- dts/bindings/power-domain/power-domain-gpio-monitor.yaml | 4 ++-- dts/bindings/rng/st,stm32-rng.yaml | 2 +- dts/bindings/sensor/st,lsm6dsv16x-common.yaml | 2 +- dts/bindings/serial/st,stm32-uart-base.yaml | 2 +- dts/bindings/watchdog/intel,adsp-watchdog.yaml | 2 +- 12 files changed, 17 insertions(+), 17 deletions(-) diff --git a/dts/bindings/bluetooth/ambiq,bt-hci-spi.yaml b/dts/bindings/bluetooth/ambiq,bt-hci-spi.yaml index 752c0d56f2..42df66d218 100644 --- a/dts/bindings/bluetooth/ambiq,bt-hci-spi.yaml +++ b/dts/bindings/bluetooth/ambiq,bt-hci-spi.yaml @@ -27,6 +27,6 @@ properties: type: phandle-array description: | This clkreq gpio is used to send the XO32MHz clock request to host from - from controller. The host needs to enable XO32MHz when receiving low to - high edge interrupt and disable XO32MHz when receiving high to low edge - interrupt. + controller. The host needs to enable XO32MHz when receiving low to high + edge interrupts and disable XO32MHz when receiving high to low edge + interrupts. diff --git a/dts/bindings/can/microchip,mcp251xfd.yaml b/dts/bindings/can/microchip,mcp251xfd.yaml index c6cd1b9f09..b35cb0fa48 100644 --- a/dts/bindings/can/microchip,mcp251xfd.yaml +++ b/dts/bindings/can/microchip,mcp251xfd.yaml @@ -47,7 +47,7 @@ properties: pll-enable: type: boolean description: | - Enables controller PLL, which multiples input clock frequency x10. + Enables controller PLL, which multiplies input clock frequency by 10. This parameter also implicitly sets whether the clock is from the PLL output or directly from the oscillator. If this option is enabled the clock source is the PLL, otherwise its diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml index 1f6e487baa..ebc6b7e84e 100644 --- a/dts/bindings/clock/st,stm32-rcc.yaml +++ b/dts/bindings/clock/st,stm32-rcc.yaml @@ -51,7 +51,7 @@ description: | ... } In this example, I2C1 device is assigned HSI as domain clock source. - Domain clock is independent from the bus/gatted clock and allows access to the device's + Domain clock is independent from the bus/gated clock and allows access to the device's register while the gated clock is off. As it doesn't feed the peripheral's controller, it allows peripheral operation, but can't be used for peripheral configuration. It is peripheral driver's responsibility to query and use clock source information in diff --git a/dts/bindings/dma/st,stm32-dma-v2.yaml b/dts/bindings/dma/st,stm32-dma-v2.yaml index d3c9edac70..632ff53a90 100644 --- a/dts/bindings/dma/st,stm32-dma-v2.yaml +++ b/dts/bindings/dma/st,stm32-dma-v2.yaml @@ -19,7 +19,7 @@ description: | or a value between +1 .. + 3. channel-config: A 32bit mask specifying the DMA channel configuration A name custom DMA flags for channel configuration is used - which is device dependent see stm32_dma.h: + which is device dependent. See stm32_dma.h: -bit 5 : DMA cyclic mode config 0x0: STM32_DMA_MODE_NORMAL 0x1: STM32_DMA_MODE_CYCLIC diff --git a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml index f18860ed92..90c5c6e838 100644 --- a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml +++ b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml @@ -14,7 +14,7 @@ description: | When using speeds above standard mode, user may need adjust clock and data lines slew and strength parameters. In general, slew 0 and minimal strength - is enough for short buses and light loads. As reference, the below + is enough for short buses and light loads. As a reference, the below is the lowest power configuration: std-clk-slew-lim = <0>; diff --git a/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml index 3363a35a7f..4e9770e65c 100644 --- a/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml +++ b/dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml @@ -57,12 +57,12 @@ description: | intmux[20 mod 8] |= 0x02 << (20 mod 4); These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2. - The interrupt can be enabled/disable at NVIC at line 20 as usual. + The interrupt can be enabled/disabled at NVIC at line 20 as usual. Notes: 1) Multiple definitions will generate multiple interrupts - 2) The interrupt sources are shared between Cortex-M0+/M4. These means, can - trigger action in parallel in both processors. + 2) The interrupt sources are shared between Cortex-M0+/M4. This means, they + can trigger actions in parallel on both processors. 3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels at interrupt-parent properties. 4) Only the peripherals used by Cortex-M0+ should be configured. diff --git a/dts/bindings/net/wireless/gpio-radio-coex.yaml b/dts/bindings/net/wireless/gpio-radio-coex.yaml index ab453e5652..1acb8e7f9a 100644 --- a/dts/bindings/net/wireless/gpio-radio-coex.yaml +++ b/dts/bindings/net/wireless/gpio-radio-coex.yaml @@ -4,7 +4,7 @@ description: | Generic representation of Coexistence pin interface for radios. This interface is usually available on Wifi/Bluetooth/LTE modules to - interact with each other when sharing same antenna. This prevents + interact with each other when sharing the same antenna. This prevents any collisions between transmissions from different modules. The grant signal should signal that the external transceiver/module is not transmitting. Therefore you are free to perform any TX operations as diff --git a/dts/bindings/power-domain/power-domain-gpio-monitor.yaml b/dts/bindings/power-domain/power-domain-gpio-monitor.yaml index ebc9b5b503..734aab8e6f 100644 --- a/dts/bindings/power-domain/power-domain-gpio-monitor.yaml +++ b/dts/bindings/power-domain/power-domain-gpio-monitor.yaml @@ -6,8 +6,8 @@ description: | This power domain monitors the state of a GPIO pin to detect whether a power rail is on/off. Therefore, performing resume/suspend on power domain won't - change physical state of power rails and those action won't be triggered on - child nodes. Additionally, due to the asynchronous nature of monitoring a + change physical state of power rails and that action won't be triggered on + child nodes. Additionally, due to the asynchronous nature of monitoring, a pending transaction won't be interrupted by power state change. compatible: "power-domain-gpio-monitor" diff --git a/dts/bindings/rng/st,stm32-rng.yaml b/dts/bindings/rng/st,stm32-rng.yaml index 58d4aea8f8..c0e6d5e2ec 100644 --- a/dts/bindings/rng/st,stm32-rng.yaml +++ b/dts/bindings/rng/st,stm32-rng.yaml @@ -19,7 +19,7 @@ properties: <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */ A correctly configured domain clock is required to allow the integrated low sampling clock detection mechanism to behave properly. - In provided example, MSI should be configured to provide 48Mhz clock. + In the provided example, MSI should be configured to provide 48Mhz clock. nist-config: type: int diff --git a/dts/bindings/sensor/st,lsm6dsv16x-common.yaml b/dts/bindings/sensor/st,lsm6dsv16x-common.yaml index fc1d2c6d59..84c0dce96a 100644 --- a/dts/bindings/sensor/st,lsm6dsv16x-common.yaml +++ b/dts/bindings/sensor/st,lsm6dsv16x-common.yaml @@ -135,7 +135,7 @@ properties: description: | Specify the default gyro output data rate expressed in samples per second (Hz). The values are taken in accordance to lsm6dsv16x_data_rate_t enumerative in hal/st - module. Please note that this values will not change the operating mode, which will remain + module. Please note that these values will not change the operating mode, which will remain High Performance (device default). Moreover, the values here which will be selected in the DT are the only way to specify the odr accuracy even at runtime with SENSOR_ATTR_SAMPLING_FREQUENCY. diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml index 9b4852bbc8..3c20564bdd 100644 --- a/dts/bindings/serial/st,stm32-uart-base.yaml +++ b/dts/bindings/serial/st,stm32-uart-base.yaml @@ -90,7 +90,7 @@ properties: fifo-enable: type: boolean description: | - Enables transmit and receive FIFO using default FIFO configuration (typically thresholds + Enables transmit and receive FIFO using default FIFO configuration (typically threshold is set to 1/8). In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also allows more reliable communication with UART devices sensitive to variation of inter-frames diff --git a/dts/bindings/watchdog/intel,adsp-watchdog.yaml b/dts/bindings/watchdog/intel,adsp-watchdog.yaml index f8e76ea23f..495ee67af8 100644 --- a/dts/bindings/watchdog/intel,adsp-watchdog.yaml +++ b/dts/bindings/watchdog/intel,adsp-watchdog.yaml @@ -16,7 +16,7 @@ properties: type: int description: | Clock frequency used by counter in Hz. You can specify a frequency here or specify a clock - using the clocks properties. + using the property "clocks". reset-pulse-length: type: int