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drivers: pinctrl: add pin control driver for NXP RT600/RT500 SOCs

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add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-04-05 17:28:12 -05:00 committed by David Leach
parent d9a74b8e0f
commit d5b719e084
4 changed files with 115 additions and 4 deletions
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8
drivers/pinctrl/Kconfig.lpc_iocon
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@ -1,11 +1,13 @@
# Copyright (c) 2022 NXP
# Copyright 2022, NXP
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_NXP_LPC_PINCTRL := nxp,lpc-iocon-pinctrl
DT_COMPAT_NXP_RT_PINCTRL := nxp,rt-iocon-pinctrl
config PINCTRL_NXP_IOCON
bool "IOCON Pin controller driver for NXP LPC MCUs"
depends on SOC_FAMILY_LPC
default $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_PINCTRL))
depends on SOC_FAMILY_LPC || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX
default $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_PINCTRL)) || \
$(dt_compat_enabled,$(DT_COMPAT_NXP_RT_PINCTRL))
help
Enable pin controller driver for NXP LPC MCUs

7
drivers/pinctrl/pinctrl_lpc_iocon.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, NXP
* Copyright 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -45,6 +45,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
return 0;
}
#ifdef CONFIG_SOC_FAMILY_LPC
/* LPC family needs iocon clock to be enabled */
static int pinctrl_clock_init(const struct device *dev)
{
ARG_UNUSED(dev);
@ -54,3 +57,5 @@ static int pinctrl_clock_init(const struct device *dev)
}
SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
#endif /* CONFIG_SOC_FAMILY_LPC */

52
soc/arm/nxp_imx/rt5xx/pinctrl_soc.h Normal file
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@ -0,0 +1,52 @@
/*
* Copyright 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT5XX_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT5XX_PINCTRL_SOC_H_
#include <devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \
(IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
(IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \
IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \
IOPCTL_PIO_FULLDRIVE(DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \
IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
/* MCUX RT parts only have one pin type */
#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_ */

52
soc/arm/nxp_imx/rt6xx/pinctrl_soc.h Normal file
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@ -0,0 +1,52 @@
/*
* Copyright 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_
#include <devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \
(IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
(IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \
IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \
IOPCTL_PIO_FULLDRIVE(DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \
IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
/* MCUX RT parts only have one pin type */
#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT6XX_PINCTRL_SOC_H_ */