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tests: clock: fix test meta data and components

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Fix meta data and standarize components in test identifiers.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-10-10 15:28:22 +00:00 committed by Johan Hedberg
parent b0b8f2ff80
commit d5bac8c9a2
8 changed files with 93 additions and 93 deletions
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76
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml
View file

@ -8,7 +8,7 @@ common:
timeout: 5
tags: clock-control
tests:
drivers.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_48_msi_4:
drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_48_msi_4:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/pll_48_msi_4.overlay"
platform_allow:
@ -17,7 +17,7 @@ tests:
- stm32l562e_dk
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hsi_16:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/pll_64_hsi_16.overlay"
platform_allow:
@ -26,7 +26,7 @@ tests:
- stm32l562e_dk
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.sysclksrc_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.sysclksrc_hsi_16:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/hsi_16.overlay"
platform_allow:
@ -37,7 +37,7 @@ tests:
- nucleo_wl55jc
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.sysclksrc_msi_48:
drivers.clock.stm32_clock_configuration.common_core.sysclksrc_msi_48:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/msi_range11.overlay"
platform_allow:
@ -48,7 +48,7 @@ tests:
- nucleo_wb55rg
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.l4_l5.sysclksrc_hse_8.fixup:
drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_hse_8.fixup:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/hse_8.overlay"
platform_allow:
@ -60,7 +60,7 @@ tests:
fixture: mco_sb_closed
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hse_8.fixup:
drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hse_8.fixup:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/pll_64_hse_8.overlay"
platform_allow:
@ -72,7 +72,7 @@ tests:
fixture: mco_sb_closed
integration_platforms:
- disco_l475_iot1
drivers.stm32_clock_configuration.common_core.g0.sysclksrc_pll_64_hse_8:
drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hse_8.overlay"
platform_allow: nucleo_g071rb
harness: ztest
@ -80,40 +80,40 @@ tests:
fixture: mco_sb_closed
integration_platforms:
- nucleo_g071rb
drivers.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_2:
drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_2:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_g0_16_div_2.overlay"
platform_allow: nucleo_g071rb
integration_platforms:
- nucleo_g071rb
drivers.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_4:
drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_g0_16_div_4.overlay"
platform_allow: nucleo_g071rb
integration_platforms:
- nucleo_g071rb
drivers.stm32_clock_configuration.common_core.g4.sysclksrc_pll_64_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.g4.sysclksrc_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
platform_allow: nucleo_g474re
integration_platforms:
- nucleo_g474re
drivers.stm32_clock_configuration.common_core.g0.sysclksrc_pll_g0_64_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_pll_g0_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_g0_64_hsi_16.overlay"
platform_allow: nucleo_g071rb
integration_platforms:
- nucleo_g071rb
drivers.stm32_clock_configuration.common_core.g4.sysclksrc_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.g4.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g474re
integration_platforms:
- nucleo_g474re
drivers.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16:
drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_g0_16.overlay"
platform_allow: nucleo_g071rb
integration_platforms:
- nucleo_g071rb
drivers.stm32_clock_configuration.common_core.g4.sysclksrc_hse_24:
drivers.clock.stm32_clock_configuration.common_core.g4.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common_core.l0_l1.sysclksrc_hse_8:
drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_hse_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/hse_8.overlay"
platform_allow:
@ -121,77 +121,77 @@ tests:
- nucleo_l073rz
integration_platforms:
- nucleo_l152re
drivers.stm32_clock_configuration.common_core.l0_l1.sysclksrc_pll_32_hse_8:
drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_pll_32_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hse_8.overlay"
platform_allow:
- nucleo_l152re
- nucleo_l073rz
integration_platforms:
- nucleo_l152re
drivers.stm32_clock_configuration.common_core.l0_l1.sysclksrc_pll_32_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_pll_32_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_32_hsi_16.overlay"
platform_allow:
- nucleo_l152re
- nucleo_l073rz
integration_platforms:
- nucleo_l152re
drivers.stm32_clock_configuration.common_core.l0_l1.sysclksrc_msi_range6:
drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_msi_range6:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msi_range6.overlay"
platform_allow:
- nucleo_l152re
- nucleo_l073rz
integration_platforms:
- nucleo_l152re
drivers.stm32_clock_configuration.common_core.wl.sysclksrc_pll_48_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.wl.sysclksrc_pll_48_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_48_hsi_16.overlay"
platform_allow: nucleo_wl55jc
integration_platforms:
- nucleo_wl55jc
drivers.stm32_clock_configuration.common_core.wl.sysclksrc_pll_48_hse_32:
drivers.clock.stm32_clock_configuration.common_core.wl.sysclksrc_pll_48_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
platform_allow: nucleo_wl55jc
integration_platforms:
- nucleo_wl55jc
drivers.stm32_clock_configuration.common_core.wl.sysclksrc_hse_32:
drivers.clock.stm32_clock_configuration.common_core.wl.sysclksrc_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/wl_32_hse.overlay"
platform_allow: nucleo_wl55jc
integration_platforms:
- nucleo_wl55jc
drivers.stm32_clock_configuration.common_core.wb.sysclksrc_hse_32:
drivers.clock.stm32_clock_configuration.common_core.wb.sysclksrc_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_32.overlay"
platform_allow: nucleo_wb55rg
integration_platforms:
- nucleo_wb55rg
drivers.stm32_clock_configuration.common_core.wb.sysclksrc_pll_48_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.wb.sysclksrc_pll_48_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/wb_pll_48_hsi_16.overlay"
platform_allow: nucleo_wb55rg
integration_platforms:
- nucleo_wb55rg
drivers.stm32_clock_configuration.common_core.wb.sysclksrc_pll_64_hse_32:
drivers.clock.stm32_clock_configuration.common_core.wb.sysclksrc_pll_64_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/wb_pll_64_hse_32.overlay"
platform_allow: nucleo_wb55rg
integration_platforms:
- nucleo_wb55rg
drivers.stm32_clock_configuration.common_core.wb.sysclksrc_pll_48_msi_4:
drivers.clock.stm32_clock_configuration.common_core.wb.sysclksrc_pll_48_msi_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
platform_allow: nucleo_wb55rg
integration_platforms:
- nucleo_wb55rg
drivers.stm32_clock_configuration.common_core.f0_f3.sysclksrc_hsi_8:
drivers.clock.stm32_clock_configuration.common_core.f0_f3.sysclksrc_hsi_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_8.overlay"
platform_allow:
- nucleo_f091rc
- stm32f3_disco
integration_platforms:
- nucleo_f091rc
drivers.stm32_clock_configuration.common_core.f0_f3.sysclksrc_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f0_f3.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hse_8_bypass.overlay"
platform_allow:
- nucleo_f091rc
- stm32f3_disco
integration_platforms:
- nucleo_f091rc
drivers.stm32_clock_configuration.common_core.f0_f3.sysclksrc_pll_32_hsi_8:
drivers.clock.stm32_clock_configuration.common_core.f0_f3.sysclksrc_pll_32_hsi_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f0_f3_pll_32_hsi_8.overlay"
platform_allow:
@ -199,7 +199,7 @@ tests:
- stm32f3_disco
integration_platforms:
- nucleo_f091rc
drivers.stm32_clock_configuration.common_core.f0_f3.sysclksrc_pll_32_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f0_f3.sysclksrc_pll_32_hse_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f0_f3_pll_32_hse_8.overlay"
platform_allow:
@ -207,29 +207,29 @@ tests:
- stm32f3_disco
integration_platforms:
- nucleo_f091rc
drivers.stm32_clock_configuration.common_core.f1.sysclksrc_hsi_8:
drivers.clock.stm32_clock_configuration.common_core.f1.sysclksrc_hsi_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_8.overlay"
platform_allow: nucleo_f103rb
integration_platforms:
- nucleo_f103rb
drivers.stm32_clock_configuration.common_core.f1.sysclksrc_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f1.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_f103rb
integration_platforms:
- nucleo_f103rb
drivers.stm32_clock_configuration.common_core.f1.sysclksrc_pll_64_hsi_8:
drivers.clock.stm32_clock_configuration.common_core.f1.sysclksrc_pll_64_hsi_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f1_pll_64_hsi_8.overlay"
platform_allow: nucleo_f103rb
integration_platforms:
- nucleo_f103rb
drivers.stm32_clock_configuration.common_core.f1.sysclksrc_pll_64_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f1.sysclksrc_pll_64_hse_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f1_pll_64_hse_8.overlay"
platform_allow: nucleo_f103rb
integration_platforms:
- nucleo_f103rb
drivers.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/hsi_16.overlay"
platform_allow:
- nucleo_f207zg
@ -238,7 +238,7 @@ tests:
- nucleo_f746zg
integration_platforms:
- nucleo_f207zg
drivers.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/hse_8.overlay"
platform_allow:
- nucleo_f207zg
@ -247,7 +247,7 @@ tests:
- nucleo_f746zg
integration_platforms:
- nucleo_f207zg
drivers.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_64_hsi_16:
drivers.clock.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_64_hsi_16:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_64_hsi_16.overlay"
platform_allow:
@ -257,7 +257,7 @@ tests:
- nucleo_f746zg
integration_platforms:
- nucleo_f207zg
drivers.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_64_hse_8:
drivers.clock.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_64_hse_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_64_hse_8.overlay"
platform_allow:
@ -267,7 +267,7 @@ tests:
- nucleo_f746zg
integration_platforms:
- nucleo_f207zg
drivers.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_100_hsi_16_ahb2:
drivers.clock.stm32_clock_configuration.common_core.f2_f4_f7.sysclksrc_pll_100_hsi_16_ahb2:
extra_args:
DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_100_hsi_16_ahb_2.overlay"
platform_allow:

22
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/testcase.yaml
View file

@ -1,36 +1,36 @@
common:
timeout: 5
tests:
drivers.stm32_clock_configuration.common_device.wb.i2c1_hsi_lptim1_lse:
drivers.clock.stm32_clock_configuration.common_device.wb.i2c1_hsi_lptim1_lse:
extra_args: DTC_OVERLAY_FILE="boards/wb_i2c1_hsi_lptim1_lse.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common_device.wb.i2c1_sysclk_lptim1_lsi:
drivers.clock.stm32_clock_configuration.common_device.wb.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/wb_i2c1_sysclk_lptim1_lsi.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common_device.g0.i2c1_sysclk_lptim1_lsi:
drivers.clock.stm32_clock_configuration.common_device.g0.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/g0_i2c1_sysclk_lptim1_lsi.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common_device.g0.i2c1_hsi_lptim1_lse_adc1_pllp:
drivers.clock.stm32_clock_configuration.common_device.g0.i2c1_hsi_lptim1_lse_adc1_pllp:
extra_args: DTC_OVERLAY_FILE="boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common_device.wl.i2c1_hsi_lptim1_lse_adc1_pllp:
drivers.clock.stm32_clock_configuration.common_device.wl.i2c1_hsi_lptim1_lse_adc1_pllp:
extra_args: DTC_OVERLAY_FILE="boards/wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common_device.wl.i2c1_sysclk_lptim1_lsi:
drivers.clock.stm32_clock_configuration.common_device.wl.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/wl_i2c1_sysclk_lptim1_lsi.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common_device.l4.i2c1_sysclk_lptim1_lsi:
drivers.clock.stm32_clock_configuration.common_device.l4.i2c1_sysclk_lptim1_lsi:
extra_args: DTC_OVERLAY_FILE="boards/l4_i2c1_sysclk_lptim1_lsi.overlay"
platform_allow: disco_l475_iot1
drivers.stm32_clock_configuration.common_device.l4.i2c1_hsi_lptim1_lse:
drivers.clock.stm32_clock_configuration.common_device.l4.i2c1_hsi_lptim1_lse:
extra_args: DTC_OVERLAY_FILE="boards/l4_i2c1_hsi_lptim1_lse.overlay"
platform_allow: disco_l475_iot1
drivers.stm32_clock_configuration.common_device.g4.i2c1_hsi_adc1_pllp:
drivers.clock.stm32_clock_configuration.common_device.g4.i2c1_hsi_adc1_pllp:
extra_args: DTC_OVERLAY_FILE="boards/g4_i2c1_hsi_adc1_pllp.overlay"
platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common_device.f0.i2c1_hsi:
drivers.clock.stm32_clock_configuration.common_device.f0.i2c1_hsi:
extra_args: DTC_OVERLAY_FILE="boards/f0_i2c1_hsi.overlay"
platform_allow: nucleo_f091rc
drivers.stm32_clock_configuration.common_device.f3.i2c1_hsi:
drivers.clock.stm32_clock_configuration.common_device.f3.i2c1_hsi:
extra_args: DTC_OVERLAY_FILE="boards/f3_i2c1_hsi.overlay"
platform_allow: stm32f3_disco

18
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/testcase.yaml
View file

@ -3,30 +3,30 @@ common:
tags: clock_control
tests:
drivers.stm32_clock_configuration.h5.sysclksrc_pll_csi_100:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_pll_csi_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_csi_240:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_pll_csi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hsi_240:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_pll_hsi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hse25_100:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_pll_hse25_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hse25_240:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_pll_hse25_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_csi4:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_csi4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/csi4.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_hse_25:
drivers.clock.stm32_clock_configuration.h5.sysclksrc_hse_25:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse25.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.pll_csi_ahb_2_100:
drivers.clock.stm32_clock_configuration.h5.pll_csi_ahb_2_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_ahb_2_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.pll_hse25_ahb_2_100:
drivers.clock.stm32_clock_configuration.h5.pll_hse25_ahb_2_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_ahb_2_100.overlay"
platform_allow: stm32h573i_dk

14
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml
View file

@ -3,37 +3,37 @@ common:
tags: clock_control
tests:
drivers.stm32_clock_configuration.h7_core.sysclksrc_pll_hse_96:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hse_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_96.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_96:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_96.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_hsi_64:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_hsi_64:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_64.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_csi_4:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_csi_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/csi_4.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_hse_8:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_pll_csi_96:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_csi_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_96.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.stm32_clock_configuration.h7_core.sysclksrc_pll_hse_550:
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hse_550:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_550.overlay"
platform_allow:
- nucleo_h723zg

14
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/testcase.yaml
View file

@ -2,17 +2,17 @@ common:
timeout: 5
platform_allow: nucleo_h723zg
tests:
drivers.stm32_clock_configuration.h7_dev.spi1_pllq_1_d1ppre_1:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_pllq_1_d1ppre_1:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_1_d1ppre_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pllq_2_d1ppre_4:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_pllq_2_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_2_d1ppre_4.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pll2p_1:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_pll2p_1:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll2p_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pll3p_1_d1ppre_4:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_pll3p_1_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll3p_1_d1ppre_4.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_d1ppre_1:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_per_ck_d1ppre_1:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_per_ck_d1ppre_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_hsi:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_per_ck_hsi:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_per_ck_hsi.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_hse:
drivers.clock.stm32_clock_configuration.h7_dev.spi1_per_ck_hse:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_per_ck_hse.overlay"

22
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
View file

@ -2,31 +2,31 @@ common:
timeout: 5
platform_allow: b_u585i_iot02a
tests:
drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay"
drivers.stm32_clock_configuration.u5.pll_msis_ahb_2_40:
drivers.clock.stm32_clock_configuration.u5.pll_msis_ahb_2_40:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_40.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_40.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_msis_48:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_msis_48:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msis_48.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_msis_24:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_msis_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msis_24.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_hsi_16:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_hse_16:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_hse_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_16.overlay"
# Build only as HSE not implemened on available boards
build_only: true
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_160:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_hse_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay"
# Build only as HSE not implemened on available boards
build_only: true
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_fracn_160:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_hse_fracn_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_fracn_160.overlay"
# Build only as HSE not implemened on available boards
build_only: true
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_fracn_160:
drivers.clock.stm32_clock_configuration.u5.sysclksrc_pll_hsi_fracn_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_160.overlay"

8
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/testcase.yaml
View file

@ -2,11 +2,11 @@ common:
timeout: 5
platform_allow: b_u585i_iot02a
tests:
drivers.stm32_clock_configuration.dev_u5.spi1_pclk2:
drivers.clock.stm32_clock_configuration.dev_u5.spi1_pclk2:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pclk2.overlay"
drivers.stm32_clock_configuration.dev_u5.spi1_hsi_16:
drivers.clock.stm32_clock_configuration.dev_u5.spi1_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_hsi_16.overlay"
drivers.stm32_clock_configuration.dev_u5.spi1_msik:
drivers.clock.stm32_clock_configuration.dev_u5.spi1_msik:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_msik.overlay"
drivers.stm32_clock_configuration.dev_u5.spi1_sysclk:
drivers.clock.stm32_clock_configuration.dev_u5.spi1_sysclk:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_sysclk.overlay"

12
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
View file

@ -2,15 +2,15 @@ common:
timeout: 5
platform_allow: nucleo_wba52cg
tests:
drivers.stm32_clock_configuration.wba.sysclksrc_hsi_32:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hsi_32_ahb5_div:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_32_ahb5_div:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16_ahb5_div.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hse_16:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_hse_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_16.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hse_32:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_32.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_pll_hse_100:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_pll_hse_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_100.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_pll_hse_50:
drivers.clock.stm32_clock_configuration.wba.sysclksrc_pll_hse_50:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_100_ahb_50.overlay"