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dts: stm32l4: Add a comment on RNG clock configuration

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Explicit default RNG domain clock configuration constraints.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2023-04-05 10:11:48 +02:00 committed by Carles Cufí
parent f48dfbf0c6
commit d6990ff8d9
1 changed files with 3 additions and 0 deletions
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3
dts/arm/st/l4/stm32l4.dtsi
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@ -448,6 +448,9 @@
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
/* Following domain clock setting requires MSI
* clock to be enabled with msi-range = <11>;
*/
<&rcc STM32_SRC_MSI CLK48_SEL(3)>;
status = "disabled";
};