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spi: mec15xx: add pinctrl for mec15xx/mec1501 qmspi

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Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 qmspi. Update board dts, pinmux and driver files.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This commit is contained in:
Jay Vasanth 2022-09-21 12:23:41 -04:00 committed by Fabio Baltieri
parent a2de15e5cc
commit d6ba6a5fac
5 changed files with 26 additions and 70 deletions
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34
boards/arm/mec1501modular_assy6885/pinmux.c
View file

@ -150,40 +150,6 @@ static int board_pinmux_init(const struct device *dev)
pinmux_pin_set(portd, MCHP_GPIO_171, MCHP_GPIO_CTRL_MUX_F1);
#endif
#ifdef CONFIG_SPI_XEC_QMSPI
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), port_sel) == 0
/* Port 0: Shared SPI pins. Shared has two chip selects */
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), chip_select) == 0
pinmux_pin_set(portb, MCHP_GPIO_055, MCHP_GPIO_CTRL_MUX_F2);
#else
pinmux_pin_set(porta, MCHP_GPIO_002, MCHP_GPIO_CTRL_MUX_F2);
#endif
pinmux_pin_set(portb, MCHP_GPIO_056, MCHP_GPIO_CTRL_MUX_F2);
pinmux_pin_set(porte, MCHP_GPIO_223, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_224, MCHP_GPIO_CTRL_MUX_F2);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), lines) == 4
pinmux_pin_set(porte, MCHP_GPIO_227, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porta, MCHP_GPIO_016, MCHP_GPIO_CTRL_MUX_F2);
#endif
#else
/* Port 1: Private SPI pins. Only one chip select */
pinmux_pin_set(portc, MCHP_GPIO_124, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_125, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_121, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_122, MCHP_GPIO_CTRL_MUX_F1);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), lines) == 4
pinmux_pin_set(portc, MCHP_GPIO_123, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_126, MCHP_GPIO_CTRL_MUX_F1);
#endif
#endif /* DT_PROP(DT_INST(0, microchip_xec_qmspi), port_sel) == 0 */
#endif /* DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay) */
#endif /* CONFIG_SPI_XEC_QMSPI */
#ifdef CONFIG_SOC_MEC1501_TEST_CLK_OUT
/*
* Deep sleep testing: Enable TEST_CLK_OUT on GPIO_060 function 2.

5
boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
View file

@ -208,6 +208,11 @@
port_sel = <0>;
chip_select = <0>;
lines = <1>;
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056
&shd_io0_gpio223
&shd_io1_gpio224 >;
pinctrl-names = "default";
};
&tach0 {

34
boards/arm/mec15xxevb_assy6853/pinmux.c
View file

@ -140,40 +140,6 @@ static int board_pinmux_init(const struct device *dev)
pinmux_pin_set(portd, MCHP_GPIO_146, MCHP_GPIO_CTRL_MUX_F2);
#endif
#ifdef CONFIG_SPI_XEC_QMSPI
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), port_sel) == 0
/* Port 0: Shared SPI pins. Shared has two chip selects */
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), chip_select) == 0
pinmux_pin_set(portb, MCHP_GPIO_055, MCHP_GPIO_CTRL_MUX_F2);
#else
pinmux_pin_set(porta, MCHP_GPIO_002, MCHP_GPIO_CTRL_MUX_F2);
#endif
pinmux_pin_set(portb, MCHP_GPIO_056, MCHP_GPIO_CTRL_MUX_F2);
pinmux_pin_set(porte, MCHP_GPIO_223, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_224, MCHP_GPIO_CTRL_MUX_F2);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), lines) == 4
pinmux_pin_set(porte, MCHP_GPIO_227, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porta, MCHP_GPIO_016, MCHP_GPIO_CTRL_MUX_F2);
#endif
#else
/* Port 1: Private SPI pins. Only one chip select */
pinmux_pin_set(portc, MCHP_GPIO_124, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_125, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_121, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_122, MCHP_GPIO_CTRL_MUX_F1);
#if DT_PROP(DT_INST(0, microchip_xec_qmspi), lines) == 4
pinmux_pin_set(portc, MCHP_GPIO_123, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_126, MCHP_GPIO_CTRL_MUX_F1);
#endif
#endif /* DT_PROP(DT_INST(0, microchip_xec_qmspi), port_sel) == 0 */
#endif /* DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay) */
#endif /* CONFIG_SPI_XEC_QMSPI */
#ifdef CONFIG_SOC_MEC1501_TEST_CLK_OUT
/*
* Deep sleep testing: Enable TEST_CLK_OUT on GPIO_060 function 2.

15
drivers/spi/spi_xec_qmspi.c
View file

@ -13,6 +13,7 @@ LOG_MODULE_REGISTER(spi_xec, CONFIG_SPI_LOG_LEVEL);
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/* Device constant configuration parameters */
@ -26,6 +27,8 @@ struct spi_qmspi_config {
uint8_t irq_pri;
uint8_t chip_sel;
uint8_t width; /* 1(single), 2(dual), 4(quad) */
uint8_t unused;
const struct pinctrl_dev_config *pcfg;
};
/* Device run time data */
@ -625,6 +628,13 @@ static int qmspi_init(const struct device *dev)
const struct spi_qmspi_config *cfg = dev->config;
struct spi_qmspi_data *data = dev->data;
QMSPI_Type *regs = cfg->regs;
int ret;
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("QSPI pinctrl setup failed (%d)", ret);
return ret;
}
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);
@ -669,6 +679,8 @@ static const struct spi_driver_api spi_qmspi_driver_api = {
#if DT_NODE_HAS_STATUS(DT_INST(0, microchip_xec_qmspi), okay)
PINCTRL_DT_INST_DEFINE(0);
static const struct spi_qmspi_config spi_qmspi_0_config = {
.regs = (QMSPI_Type *)DT_INST_REG_ADDR(0),
.cs_timing = XEC_QMSPI_0_CS_TIMING,
@ -677,7 +689,8 @@ static const struct spi_qmspi_config spi_qmspi_0_config = {
.girq_nvic_direct = MCHP_QMSPI_GIRQ_NVIC_DIRECT,
.irq_pri = DT_INST_IRQ(0, priority),
.chip_sel = DT_INST_PROP(0, chip_select),
.width = DT_INST_PROP(0, lines)
.width = DT_INST_PROP(0, lines),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct spi_qmspi_data spi_qmspi_0_dev_data = {

8
dts/bindings/spi/microchip,xec-qmspi.yaml
View file

@ -5,7 +5,7 @@ description: Microchip XEC QMSPI controller
compatible: "microchip,xec-qmspi"
include: spi-controller.yaml
include: [spi-controller.yaml, pinctrl-device.yaml]
properties:
reg:
@ -16,6 +16,12 @@ properties:
required: true
description: SPI Port 0 or 1.
pinctrl-0:
required: true
pinctrl-names:
required: true
rxdma:
type: int
required: true