boards: arm: Add sam_v71_xult board

Add sam_v71_xult board files. This enable use of Atmel samv71 SoC.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>

boards/arm/sam_v71_xult/CMakeLists.txt

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+#
+# Copyright (c) 2019, Aurelien Jarno
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(pinmux.c)

boards/arm/sam_v71_xult/Kconfig.board

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+# Atmel SMART SAM V71 Xplained Board selection
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SAM_V71_XULT
+	bool "Atmel SMART SAM V71 Xplained Ultra Board"
+	depends on SOC_PART_NUMBER_SAMV71Q21 || SOC_PART_NUMBER_SAMV71Q21B

boards/arm/sam_v71_xult/Kconfig.defconfig

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+# Atmel SMART SAM V71 Xplained Board configuration
+
+# Copyright (c) 2019 Gerson Fernando Budke
+# Copyright (c) 2016 Piotr Mienkowski
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SAM_V71_XULT
+
+config BOARD
+	default "sam_v71_xult"
+
+if I2S
+
+config I2S_SAM_SSC_0_DMA_RX_CHANNEL
+	default 22
+
+config I2S_SAM_SSC_0_DMA_TX_CHANNEL
+	default 23
+endif # I2S
+
+if ETH_SAM_GMAC
+
+# Read MAC address from AT24MAC402 EEPROM
+
+choice ETH_SAM_GMAC_MAC_SELECT
+	default ETH_SAM_GMAC_MAC_I2C_EEPROM
+endchoice
+
+config ETH_SAM_GMAC_MAC_I2C_SLAVE_ADDRESS
+	default 0x5F
+
+config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS
+	default 0x9A
+
+config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE
+	default 1
+
+config ETH_SAM_GMAC_MAC_I2C_DEV_NAME
+	default "I2C_0"
+
+config ETH_SAM_GMAC_MAC_I2C_EEPROM
+	select I2C
+
+endif # ETH_SAM_GMAC
+
+if ADC
+
+config ADC_0
+	default y
+
+endif # ADC
+
+if I2C
+
+config I2C_0
+	default y
+
+endif # I2C
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config ETH_SAM_GMAC
+	default y if NET_L2_ETHERNET
+
+endif # NETWORKING
+
+if SPI
+
+if SPI_SAM_PORT_0
+
+config SPI_SAMV71_PORT_0_PIN_CS1
+	bool
+	default y
+
+endif # SPI_SAM_PORT_0
+
+endif # SPI
+
+endif # BOARD_SAM_V71_XULT

boards/arm/sam_v71_xult/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/arm/sam_v71_xult/doc/index.rst

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+.. _sam_v71_xplained_ultra:
+
+SAM V71 Xplained Ultra
+######################
+
+Overview
+********
+
+The SAM V71 Xplained Ultra evaluation kit is a development platform to
+evaluate the Atmel SAM V71 series microcontrollers.
+
+.. image:: img/atsamv71-xult.jpg
+     :width: 500px
+     :align: center
+     :alt: SAM V71 Xplained Ultra
+
+Hardware
+********
+
+- ATSAMV71Q21 ARM Cortex-M7 Processor
+- 12 MHz crystal oscillator
+- 32.768 kHz crystal oscillator
+- Supercap backup
+- AT24MAC402 EEPROM
+- IS42S16100E 16 Mb SDRAM
+- S25FL116K 16 Mb QSPI
+- WM8904 low power stereo audio codec
+- ATA6561 CAN Transceiver
+- SD card connector with SDIO support
+- Camera interface connector
+- MediaLB connector
+- Ethernet port
+- Micro-AB USB device
+- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data
+  Gateway Interface (DGI)
+- JTAG interface connector
+- One reset and two user pushbuttons
+- Two yellow user LEDs
+
+Supported Features
+==================
+
+The sam_v71_xplained_ultra board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| USART     | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
+| ETHERNET  | on-chip    | ethernet                            |
++-----------+------------+-------------------------------------+
+| WATCHDOG  | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| ADC       | on-chip    | ADC via AFEC                        |
++-----------+------------+-------------------------------------+
+| USB       | on-chip    | USB device                          |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by Zephyr.
+
+The default configuration can be found in the Kconfig
+:zephyr_file:`boards/arm/sam_v71_xult/sam_v71_xult_defconfig`.
+
+Connections and IOs
+===================
+
+The `SAMV71-XULT User Guide`_ has detailed information about board
+connections.
+
+System Clock
+============
+
+The SAM V71 MCU is configured to use the 12 MHz external oscillator on the
+board with the on-chip PLL to generate a 300 MHz system clock.
+
+Serial Port
+===========
+
+The ATSAMV71Q21 MCU has five UARTs and three USARTs. USART1 is configured
+for the console and is available as a Virtual COM Port via EDBG USB chip.
+
+Programming and Debugging
+*************************
+
+Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_.
+Support for Atmel SAM E microcontroller series was added in OpenOCD release
+0.10.0, which was added in Zephyr SDK 0.9.2.
+
+By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader
+located in the ROM, not the flashed image. This is determined by the value
+of GPNVM1 (General-Purpose NVM bit 1). The flash procedure will ensure that
+GPNVM1 is set to 1 changing the default behavior to boot from Flash.
+
+If your chip has a security bit GPNVM0 set you will be unable to program flash
+memory or connect to it via a debug interface. The only way to clear GPNVM0
+is to perform a chip erase procedure that will erase all GPNVM bits and the
+full contents of the SAM V71 flash memory:
+
+- With the board power off, set a jumper on the J200 header.
+- Turn the board power on. The jumper can be removed soon after the power is
+  on (flash erasing procedure is started when the erase line is asserted for
+  at least 230ms)
+
+Flashing
+========
+
+#. Run your favorite terminal program to listen for output. Under Linux the
+   terminal should be :code:`/dev/ttyACM0`. For example:
+
+   .. code-block:: console
+
+      $ minicom -D /dev/ttyACM0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+   - Speed: 115200
+   - Data: 8 bits
+   - Parity: None
+   - Stop bits: 1
+
+#. Connect the SAM V71 Xplained Ultra board to your host computer using the
+   USB debug port. Then build and flash the :ref:`hello_world`
+   application.
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: sam_v71_xult
+      :goals: build flash
+
+   You should see "Hello World! arm" in your terminal.
+
+You can flash the image using an external debug adapter such as J-Link
+or ULINK, connected to the 20-pin JTAG header. Supply the name of the
+debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment
+variable. OpenOCD will look for the appropriate interface
+configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its
+internal search path.
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: sam_v71_xult
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+SAM V71 Product Page:
+    https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-v-mcus
+
+.. _SAMV71-XULT User Guide:
+    http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf
+
+.. _OpenOCD tool:
+    http://openocd.org/
+
+.. _SAM-BA:
+    http://www.atmel.com/tools/ATMELSAM-BAIN-SYSTEMPROGRAMMER.aspx

boards/arm/sam_v71_xult/pinmux.c

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+/*
+ * Copyright (c) 2019, Gerson Fernando Budke
+ * Copyright (c) 2019, Aurelien Jarno
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+
+#if defined CONFIG_PWM && defined DT_INST_0_ATMEL_SAM_PWM
+/* PWM on EXT1 connector, pin 7, channel 0, inverted */
+static const struct soc_gpio_pin pwm_ext1_pin7 = {
+	PIO_PA0A_PWM0_PWMH0, PIOA, ID_PIOA, SOC_GPIO_FUNC_A
+};
+
+/* PWM on EXT2 connector, pin 7, channel 2, inverted */
+static const struct soc_gpio_pin pwm_ext2_pin7 = {
+	PIO_PC19B_PWM0_PWMH2, PIOC, ID_PIOC, SOC_GPIO_FUNC_B
+};
+
+/* PWM on EXT2 connector, pin 8, channel 2, non-inverted  */
+static const struct soc_gpio_pin pwm_ext2_pin8 = {
+	PIO_PD26A_PWM0_PWML2, PIOD, ID_PIOD, SOC_GPIO_FUNC_A
+};
+#endif
+
+static int sam_v71_xplained_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+#if defined CONFIG_PWM && DT_INST_0_ATMEL_SAM_PWM
+	soc_gpio_configure(&pwm_ext1_pin7);
+	soc_gpio_configure(&pwm_ext2_pin7);
+	soc_gpio_configure(&pwm_ext2_pin8);
+#endif
+
+	return 0;
+}
+
+SYS_INIT(sam_v71_xplained_init, PRE_KERNEL_1, 0);

boards/arm/sam_v71_xult/sam_v71_xult.dts

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+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ * Copyright (c) 2017 Piotr Mienkowski
+ * Copyright (c) 2017 Justin Watson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <atmel/samv71q21.dtsi>
+
+/ {
+	model = "Atmel SAM V71 Xplained Ultra board";
+	compatible = "atmel,sam_v71_xult", "atmel,samv71q21", "atmel,samv71";
+
+	aliases {
+		i2c-0 = &i2c0;
+		i2c-1 = &i2c1;
+		i2c-2 = &i2c2;
+		led0 = &yellow_led0;
+		led1 = &yellow_led1;
+		sw0 = &sw0_user_button;
+		sw1 = &sw1_user_button;
+	};
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		yellow_led0: led_0 {
+			gpios = <&porta 23 0>;
+			label = "User LED 0";
+		};
+		yellow_led1: led_1 {
+			gpios = <&portc 9 0>;
+			label = "User LED 1";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		/* The switch is labeled SW300/301 in the schematic, and
+		 * labeled SW0 on the board, and labeld ERASE User Button
+		 * on docs
+		 */
+		sw0_user_button: button_1 {
+			label = "User Button 0";
+			gpios = <&porta 9 (GPIO_PUD_PULL_UP |
+					    GPIO_INT_ACTIVE_LOW)>;
+		};
+		sw1_user_button: button_2 {
+			label = "User Button 1";
+			gpios = <&portb 12 (GPIO_PUD_PULL_UP |
+					    GPIO_INT_ACTIVE_LOW)>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <300000000>;
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&adc1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&usart1 {
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&wdog {
+	status = "okay";
+};
+
+&usbhs {
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&porta {
+	status = "okay";
+};
+
+&portb {
+	status = "okay";
+};
+
+&portc {
+	status = "okay";
+};
+
+&portd {
+	status = "okay";
+};
+
+&porte {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * The first half of sector 0 (64 kbytes)
+		 * is reserved for the bootloader
+		 */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 0x00010000>;
+			read-only;
+		};
+
+		/* From sector 1 to sector 7 (included): slot0 (896 kbytes) */
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x0020000 0x000e0000>;
+		};
+
+		/* From sector 8 to sector 14 (included): slot1 (896 kbytes) */
+		slot1_partition: partition@100000 {
+			label = "image-1";
+			reg = <0x00100000 0x000e0000>;
+		};
+
+		/* Sector 15: scratch (128 kbytes) */
+		scratch_partition: partition@1e0000 {
+			label = "image-scratch";
+			reg = <0x001e0000 0x00020000>;
+		};
+	};
+};

boards/arm/sam_v71_xult/sam_v71_xult.yaml

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+identifier: sam_v71_xult
+name: SAM V71 Xplained Ultra
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - netif:eth
+  - gpio
+  - watchdog
+  - pwm

boards/arm/sam_v71_xult/sam_v71_xult_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM=y
+CONFIG_SOC_SERIES_SAMV71=y
+CONFIG_SOC_PART_NUMBER_SAMV71Q21=y
+CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK=y
+CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA=24
+CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA=1
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=300000000
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_USART_SAM=y
+CONFIG_USART_SAM_PORT_1=y

boards/arm/sam_v71_xult/support/openocd.cfg

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+if {[info exists env(OPENOCD_INTERFACE)]} {
+	set INTERFACE $env(OPENOCD_INTERFACE)
+} else {
+	# By default connect over Debug USB port using the EDBG chip
+	set INTERFACE "cmsis-dap"
+}
+
+source [find interface/$INTERFACE.cfg]
+
+transport select swd
+
+set CHIPNAME atsamv71q21
+
+source [find target/atsamv.cfg]
+
+reset_config srst_only
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}