ARC: boards: nSIM: add 12-core SMP HS5x platform

Add new simulation (nSIM) SMP platform based on 12-core ARCv3 HS5x

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>

boards/arc/nsim/nsim_hs5x_smp_12cores.dts

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim-smp.dtsi"
+#include "nsim-flat-mem.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <3>;
+		};
+
+		cpu@4 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <4>;
+		};
+
+		cpu@5 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <5>;
+		};
+
+		cpu@6 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <6>;
+		};
+
+		cpu@7 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <7>;
+		};
+
+		cpu@8 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <8>;
+		};
+
+		cpu@9 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <9>;
+		};
+
+		cpu@a {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <10>;
+		};
+
+		cpu@b {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <11>;
+		};
+	};
+};

boards/arc/nsim/nsim_hs5x_smp_12cores.yaml

@@ -0,0 +1,17 @@
+identifier: nsim_hs5x_smp_12cores
+name: Multi-core HS5x nSIM simulator
+type: sim
+simulation: mdb-nsim
+simulation_exec: mdb
+arch: arc
+toolchain:
+  - zephyr
+  - arcmwdt
+  - cross-compile
+supported:
+  - smp
+testing:
+  timeout_multiplier: 4
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ISA_ARCV3=y
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS5X_SMP=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=12

boards/arc/nsim/support/mdb_hs5x_smp_12cores.args

@@ -0,0 +1,65 @@
+-arcv3hs
+-core0
+-Xdual_issue
+-uarch_rev=0:0
+-rgf_num_banks=1
+-rgf_num_wr_ports=2
+-lpc_width=0
+-Xatomic=2
+-Xll64
+-Xunaligned
+-Xdiv_rem=radix4
+-Xmpy_option=qmpyh
+-Xtimer0
+-Xtimer0_level=0
+-Xtimer1
+-Xtimer1_level=0
+-Xrtc
+-action_points=8
+-ap_feature=1
+-Xstack_check
+-bpu_bc_entries=2048
+-bpu_pt_entries=16384
+-bpu_rs_entries=4
+-bpu_bc_full_tag=1
+-bpu_tosq_entries=5
+-bpu_fb_entries=2
+-bpu_debug
+-smart_version=4
+-smart_stack_entries=8
+-mmuv16
+-mmu_dtlb_entries=16
+-mmu_itlb_entries=16
+-mmu_l2tlb_entries=2048
+-mmu_pgsz=4K
+-mmu_address_space=32
+-interrupts=32
+-interrupt_priorities=2
+-ext_interrupts=27
+-interrupt_base=0x0
+-dcache=32768,64,2,a
+-dcache_version=5
+-dcache_feature=2
+-dcache_mem_cycles=1
+-dcache_hw_prefetch
+-icache=32768,64,4,a
+-icache_version=6
+-icache_feature=2
+-Xpct_counters=8
+-Xpct_interrupt
+-cluster_version=32
+-arconnect
+-connect_ics=1
+-connect_ics_num_semas=16
+-connect_icm=1
+-connect_icm_sram_size=512
+-connect_icm_sram_prot=none
+-connect_pmu=1
+-connect_idu=2
+-connect_idu_cirqnum=64
+-connect_gfrc=3
+-connect_icd=2
+-connect_ici=2
+-noprofile
+-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
+-instrs_per_pass=512