drivers: pinmux: mchp_xec: drop driver
Drop Microchip XEC driver in favor of pinctrl. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
9ca624eb13
commit
d76f4f2c8a
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@ -1,4 +1,3 @@
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# SPDX-License-Identifier: Apache-2.0
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# Board initialization
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zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
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@ -24,6 +24,4 @@ config PINMUX_INIT_PRIORITY
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rule for particular boards. Don't change this value unless you
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know what you are doing.
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source "drivers/pinmux/Kconfig.xec"
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endif # PINMUX
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@ -1,10 +0,0 @@
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# Microchip XEC pinmux configuration options
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# Copyright (c) 2019 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PINMUX_XEC
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bool "XEC Microchip Pinmux driver"
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depends on SOC_FAMILY_MEC
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help
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Enable the Microchip XEC pinmux driver.
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@ -1,151 +0,0 @@
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/pinmux.h>
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#include <soc.h>
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#include <zephyr/sys/printk.h>
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#define DT_DRV_COMPAT microchip_xec_pinmux
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static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
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(MCHP_GPIO_PORT_A_BITMAP),
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(MCHP_GPIO_PORT_B_BITMAP),
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(MCHP_GPIO_PORT_C_BITMAP),
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(MCHP_GPIO_PORT_D_BITMAP),
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(MCHP_GPIO_PORT_E_BITMAP),
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(MCHP_GPIO_PORT_F_BITMAP)
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};
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struct pinmux_xec_config {
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uintptr_t pcr1_base;
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uint32_t port_num;
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};
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static int pinmux_xec_set(const struct device *dev, uint32_t pin,
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uint32_t func)
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{
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const struct pinmux_xec_config *config = dev->config;
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uintptr_t current_pcr1;
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uint32_t pcr1 = 0;
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uint32_t mask = 0;
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uint32_t temp = 0;
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/* Validate pin number in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0) {
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return -EINVAL;
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}
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mask |= MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_MUX_MASK |
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MCHP_GPIO_CTRL_INPAD_DIS_MASK;
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/* Check for open drain/push_pull setting */
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if (func & MCHP_GPIO_CTRL_BUFT_OPENDRAIN) {
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pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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} else {
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pcr1 |= MCHP_GPIO_CTRL_BUFT_PUSHPULL;
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}
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/* Parse mux mode */
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pcr1 |= func & MCHP_GPIO_CTRL_MUX_MASK;
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/* Figure out the pullup/pulldown configuration */
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mask |= MCHP_GPIO_CTRL_PUD_MASK;
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if (func & MCHP_GPIO_CTRL_PUD_PU) {
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/* Enable the pull and select the pullup resistor. */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
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} else if (func & MCHP_GPIO_CTRL_PUD_PD) {
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/* Enable the pull and select the pulldown resistor */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
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} else {
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/* None : Pin tristates when no active driver is present
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* on the pin. This is the POR setting
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*/
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pcr1 |= MCHP_GPIO_CTRL_PUD_NONE;
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}
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/* Make sure gpio isrs are disabled */
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pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
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mask |= MCHP_GPIO_CTRL_IDET_MASK;
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/* Now write contents of pcr1 variable to the PCR1 register that
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* corresponds to the pin configured. Each pin control register
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* on a 32-bit boundary.
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*/
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current_pcr1 = config->pcr1_base + pin * 4;
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temp = (sys_read32(current_pcr1) & ~mask) | pcr1;
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sys_write32(temp, current_pcr1);
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return 0;
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}
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static int pinmux_xec_get(const struct device *dev, uint32_t pin,
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uint32_t *func)
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{
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const struct pinmux_xec_config *config = dev->config;
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uintptr_t current_pcr1;
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/* Validate pin number in terms of current port */
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0) {
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return -EINVAL;
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}
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current_pcr1 = config->pcr1_base + pin * 4;
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*func = sys_read32(current_pcr1) & (MCHP_GPIO_CTRL_BUFT_MASK
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| MCHP_GPIO_CTRL_MUX_MASK
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| MCHP_GPIO_CTRL_PUD_MASK);
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return 0;
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}
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static int pinmux_xec_pullup(const struct device *dev, uint32_t pin,
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uint8_t func)
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{
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return -ENOTSUP;
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}
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static int pinmux_xec_input(const struct device *dev, uint32_t pin,
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uint8_t func)
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{
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return -ENOTSUP;
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}
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static int pinmux_xec_init(const struct device *dev)
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{
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/* Nothing to do. The PCR clock is enabled at reset. */
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return 0;
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}
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static const struct pinmux_driver_api pinmux_xec_driver_api = {
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.set = pinmux_xec_set,
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.get = pinmux_xec_get,
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.pullup = pinmux_xec_pullup,
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.input = pinmux_xec_input,
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};
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/* Get ph_reg address given a node-id */
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#define PINMUX_ADDR(n) DT_REG_ADDR(DT_PHANDLE(n, ph_reg))
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/* Get ph_reg address given instance */
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#define PINMUX_INST_ADDR(n) DT_REG_ADDR(DT_PHANDLE(DT_NODELABEL(n), ph_reg))
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/* Get port-num property */
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#define PINMUX_PORT_NUM(n) DT_PROP(DT_NODELABEL(n), port_num)
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/* id is a child node-id */
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#define PINMUX_XEC_DEVICE(id) \
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static const struct pinmux_xec_config pinmux_xec_port_cfg_##id = { \
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.pcr1_base = (uintptr_t)PINMUX_ADDR(id), \
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.port_num = (uint32_t)DT_PROP(id, port_num), \
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}; \
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DEVICE_DT_DEFINE(id, &pinmux_xec_init, NULL, NULL, \
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&pinmux_xec_port_cfg_##id, \
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PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&pinmux_xec_driver_api);
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DT_FOREACH_CHILD_STATUS_OKAY(DT_NODELABEL(pinmux), PINMUX_XEC_DEVICE)
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@ -38,35 +38,6 @@
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i2c-smb-4 = &i2c_smb_4;
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};
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pinmux: pinmux {
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compatible = "microchip,xec-pinmux";
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pinmux_000_036: pinmux-0 {
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ph-reg = <&gpio_000_036>;
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port-num = <0>;
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};
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pinmux_040_076: pinmux-1 {
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ph-reg = <&gpio_040_076>;
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port-num = <1>;
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};
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pinmux_100_136: pinmux-2 {
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ph-reg = <&gpio_100_136>;
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port-num = <2>;
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};
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pinmux_140_176: pinmux-3 {
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ph-reg = <&gpio_140_176>;
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port-num = <3>;
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};
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pinmux_200_236: pinmux-4 {
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ph-reg = <&gpio_200_236>;
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port-num = <4>;
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};
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pinmux_240_276: pinmux-5 {
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ph-reg = <&gpio_240_276>;
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port-num = <5>;
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};
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};
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soc {
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ecs: ecs@4000fc00 {
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compatible = "microchip,xec-ecs";
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@ -1,21 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC Pinmux node
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compatible: "microchip,xec-pinmux"
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include: base.yaml
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child-binding:
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description: pinmux child node
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properties:
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ph-reg:
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type: phandle
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required: true
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port-num:
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type: int
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required: true
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description: |
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Zero based GPIO port number. Pin group 000 - 036 is port 0,
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040 - 076 is port 1, etc.
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@ -8,10 +8,6 @@ if SOC_MEC1501_HSZ
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config SOC
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default "mec1501hsz"
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config PINMUX_XEC
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default y
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depends on PINMUX
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config GPIO
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default y
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@ -11,10 +11,6 @@ config SOC
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config GPIO
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default y
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config PINMUX_XEC
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default y
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depends on PINMUX
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config ESPI_XEC_V2
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default y
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depends on ESPI
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