riscv_machine_timer: Enable to use divided clock for the machine timer

GD32V SoC uses divided clock from core-clock for machine timer clock.
Add config of clock divide factor to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>

drivers/timer/Kconfig.riscv_machine

@@ -11,3 +11,20 @@ config RISCV_MACHINE_TIMER
 	help
 	  This module implements a kernel device driver for the generic RISCV machine
 	  timer driver. It provides the standard "system clock driver" interfaces.
+
+config RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER
+	int
+	default 0
+	help
+	  Specifies the division ratio of the system clock supplied to the Machine Timer.
+
+	  A clock obtained by dividing the system clock by a value of [2^N] is
+	  supplied to the timer. Where N is this parameter's value.
+	  When N=2, it is divided by 4, and when N=5, it is divided by 32.
+	  Default case is N=0, this means use system clock as machine timer clock.
+	  It is normal configuration for RISC-V machine clock.
+
+	  This parameter usually depends on the hardware configuration.
+	  The division ratio should define in devicetree,
+	  and it is desireble usage that references it with using a function such as
+	  dt_node_int_prop_int from Kconfig. (Tune in the conf file is not preferable.)

drivers/timer/riscv_machine_timer.c

@@ -9,8 +9,9 @@
 #include <spinlock.h>
 #include <soc.h>
 
-#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec()	\
-			      / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+#define CYC_PER_TICK ((uint32_t)((uint64_t) (sys_clock_hw_cycles_per_sec()			 \
+					     >> CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER) \
+				 / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
 #define MAX_CYC INT_MAX
 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
 #define MIN_DELAY 1000
@@ -135,12 +136,12 @@ uint32_t sys_clock_elapsed(void)
 
 uint32_t sys_clock_cycle_get_32(void)
 {
-	return (uint32_t)mtime();
+	return (uint32_t)(mtime() << CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER);
 }
 
 uint64_t sys_clock_cycle_get_64(void)
 {
-	return mtime();
+	return (mtime() << CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER);
 }
 
 static int sys_clock_driver_init(const struct device *dev)

dts/bindings/timer/riscv,machine-timer.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V Machine timer
+
+compatible: "nuclei,machine-timer"
+
+include: base.yaml
+
+properties:
+    clk-divider:
+      type: int
+      required: false
+      description: |
+        clk-divider specifies the division ratio to the CPU frequency that
+        clock used by machine timer.
+        This property supports the case that the machine timer and CPU use
+        different clock sources.
+        This configuration is used sometimes for such as low power consumption.
+
+        For example, the CPU clock frequency is 108MHz, and the machine timer
+        uses 27MHz, which is the CPU clock divided by 4.
+        In this case, the CPU clock frequency is defined in the CPU node
+        as follows
+
+           clock-frequency = <108000000>;
+
+        This property takes exponent of the power of 2.
+        The relationship with the frequency division ratio is as
+        following equation.
+
+           division_ratio = 2^n
+           n = log_2(division_ratio)
+
+        Setting clk-divider to 2 specifies the machine timer uses the clock
+        that CPU clock frequency divided by (2^2=)4, or 27MHz.
+
+        Devision ratio constants can be found in the
+        dt-bindings/timer/nuclei-machine-timer.h header file.

include/dt-bindings/timer/riscv-machine-timer.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
+
+/* Clock divider values */
+#define RISCV_MACHINE_TIMER_DIVIDER_1          0
+#define RISCV_MACHINE_TIMER_DIVIDER_2          1
+#define RISCV_MACHINE_TIMER_DIVIDER_4          2
+#define RISCV_MACHINE_TIMER_DIVIDER_8          3
+#define RISCV_MACHINE_TIMER_DIVIDER_16         4
+#define RISCV_MACHINE_TIMER_DIVIDER_32         5
+#define RISCV_MACHINE_TIMER_DIVIDER_64         6
+#define RISCV_MACHINE_TIMER_DIVIDER_128        7
+#define RISCV_MACHINE_TIMER_DIVIDER_256        8
+#define RISCV_MACHINE_TIMER_DIVIDER_512        9
+#define RISCV_MACHINE_TIMER_DIVIDER_1024      10
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_ */