drivers: pinmux: stm32: drop driver
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located in pinmux headers were used by the pinctrl driver, so they have been moved there. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
f1539b48cf
commit
d925c660ed
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@ -12,8 +12,12 @@
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*/
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <pinmux/pinmux_stm32.h>
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#include <zephyr/drivers/gpio.h>
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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#include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h>
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#else
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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/* GPIO buses definitions */
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@ -14,6 +14,32 @@
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#include <stm32_ll_gpio.h>
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#include <stm32_ll_system.h>
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/** Helper to extract IO port number from STM32PIN() encoded value */
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#define STM32_PORT(__pin) \
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((__pin) >> 4)
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/** Helper to extract IO pin number from STM32PIN() encoded value */
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#define STM32_PIN(__pin) \
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((__pin) & 0xf)
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/** Helper to extract IO port number from STM32_PINMUX() encoded value */
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#define STM32_DT_PINMUX_PORT(__pin) \
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(((__pin) >> STM32_PORT_SHIFT) & STM32_PORT_MASK)
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/** Helper to extract IO pin number from STM32_PINMUX() encoded value */
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#define STM32_DT_PINMUX_LINE(__pin) \
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(((__pin) >> STM32_LINE_SHIFT) & STM32_LINE_MASK)
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/** Helper to extract IO pin func from STM32_PINMUX() encoded value */
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#define STM32_DT_PINMUX_FUNC(__pin) \
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(((__pin) >> STM32_MODE_SHIFT) & STM32_MODE_MASK)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/** Helper to extract IO pin remap from STM32_PINMUX() encoded value */
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#define STM32_DT_PINMUX_REMAP(__pin) \
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(((__pin) >> STM32_REMAP_SHIFT) & STM32_REMAP_MASK)
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#endif
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/**
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* @brief Array containing pointers to each GPIO port.
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*
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@ -4,5 +4,4 @@
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zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X pinmux_lpc11u6x.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC pinmux_mcux_lpc.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_STM32 pinmux_stm32.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
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@ -30,8 +30,6 @@ source "drivers/pinmux/Kconfig.mcux"
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source "drivers/pinmux/Kconfig.mcux_lpc"
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source "drivers/pinmux/Kconfig.stm32"
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source "drivers/pinmux/Kconfig.xec"
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endif # PINMUX
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@ -1,17 +0,0 @@
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# Configuration for STM32 pinmux
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# SPDX-License-Identifier: Apache-2.0
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config PINMUX_STM32
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bool "Pinmux driver for STM32 MCUs"
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depends on SOC_FAMILY_STM32
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help
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Enable pin multiplexer for STM32 MCUs
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config PINMUX_STM32_REMAP_INIT_PRIORITY
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int "Remap initialization priority"
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default 2
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help
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Initialization priority for the routine in charge of configuring the
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remap for pins PA11/12.
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@ -1,272 +0,0 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief
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*
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* A common driver for STM32 pinmux.
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*/
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_gpio.h>
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#include <stm32_ll_system.h>
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#include <zephyr/drivers/pinmux.h>
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#include <gpio/gpio_stm32.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <pinmux/pinmux_stm32.h>
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const struct device * const gpio_ports[STM32_PORTS_MAX] = {
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioa)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiob)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioc)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiod)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioe)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiof)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiog)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioh)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioi)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioj)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiok)),
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};
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#define REMAP_PA11 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#define REMAP_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#define REMAP_PA11_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#endif
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#if REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12
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int stm32_pinmux_init_remap(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#if REMAP_PA11 || REMAP_PA12
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#if !defined(CONFIG_SOC_SERIES_STM32G0X)
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#error "Pin remap property available only on STM32G0 SoC series"
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#endif
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#if REMAP_PA11
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
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#endif
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#if REMAP_PA12
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
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#endif
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#elif REMAP_PA11_PA12
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#if !defined(SYSCFG_CFGR1_PA11_PA12_RMP)
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#error "Pin remap property available only on STM32F070x SoC series"
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#endif
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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LL_SYSCFG_EnablePinRemap();
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#endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
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return 0;
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}
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SYS_INIT(stm32_pinmux_init_remap, PRE_KERNEL_1,
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CONFIG_PINMUX_STM32_REMAP_INIT_PRIORITY);
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#endif /* REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12 */
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static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
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{
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const struct device *port_device;
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if (STM32_PORT(pin) >= STM32_PORTS_MAX) {
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return -EINVAL;
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}
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port_device = gpio_ports[STM32_PORT(pin)];
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if ((port_device == NULL) || (!device_is_ready(port_device))) {
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return -ENODEV;
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}
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return gpio_stm32_configure(port_device, STM32_PIN(pin), func, altf);
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}
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/**
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* @brief helper for converting dt stm32 pinctrl format to existing pin config
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* format
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*
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* @param *pinctrl pointer to soc_gpio_pinctrl list
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* @param list_size list size
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* @param base device base register value
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*
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* @return 0 on success, -EINVAL otherwise
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*/
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int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
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size_t list_size, uint32_t base)
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{
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uint32_t pin, mux;
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uint32_t func = 0;
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int ret = 0;
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if (!list_size) {
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/* Empty pinctrl. Exit */
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return 0;
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}
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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if (stm32_dt_pinctrl_remap(pinctrl, list_size)) {
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/* Wrong remap config. Exit */
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return -EINVAL;
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}
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#else
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ARG_UNUSED(base);
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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for (int i = 0; i < list_size; i++) {
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mux = pinctrl[i].pinmux;
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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uint32_t pupd;
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if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) {
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func = pinctrl[i].pincfg | STM32_MODE_OUTPUT |
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STM32_CNF_ALT_FUNC;
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} else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) {
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func = pinctrl[i].pincfg | STM32_MODE_INPUT |
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STM32_CNF_IN_ANALOG;
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} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) {
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func = pinctrl[i].pincfg | STM32_MODE_INPUT;
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pupd = func & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
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if (pupd == STM32_PUPD_NO_PULL) {
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func = func | STM32_CNF_IN_FLOAT;
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} else {
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func = func | STM32_CNF_IN_PUPD;
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}
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#else
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if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) {
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func = pinctrl[i].pincfg | STM32_MODER_ALT_MODE;
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} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
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func = STM32_MODER_ANALOG_MODE;
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
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STM32_DT_PINMUX_LINE(mux));
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ret = stm32_pin_configure(pin, func, STM32_DT_PINMUX_FUNC(mux));
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if (ret != 0) {
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return ret;
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}
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}
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return 0;
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}
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/* ignore swj-cfg reset state (default value) */
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#if ((DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg)) && \
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(DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) != 0))
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static int stm32f1_swj_cfg_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
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/* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */
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/* only one of the 3 bits can be set */
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#if (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 1)
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/* 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST */
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/* releases: PB4 */
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LL_GPIO_AF_Remap_SWJ_NONJTRST();
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#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 2)
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/* 010: JTAG-DP Disabled and SW-DP Enabled */
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/* releases: PB4 PB3 PA15 */
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LL_GPIO_AF_Remap_SWJ_NOJTAG();
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#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 3)
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/* 100: JTAG-DP Disabled and SW-DP Disabled */
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/* releases: PB4 PB3 PA13 PA14 PA15 */
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LL_GPIO_AF_DisableRemap_SWJ();
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#endif
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return 0;
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}
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SYS_INIT(stm32f1_swj_cfg_init, PRE_KERNEL_1, 0);
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#endif /* DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg) */
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/**
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* @brief Helper function to check and apply provided pinctrl remap
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* configuration
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*
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* Check operation verifies that pin remapping configuration is the same on all
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* pins. If configuration is valid AFIO clock is enabled and remap is applied
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*
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* @param *pinctrl pointer to soc_gpio_pinctrl list
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* @param list_size list size
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*
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* @return 0 on success, -EINVAL otherwise
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*/
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int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
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size_t list_size)
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{
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uint32_t reg_val;
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uint16_t remap;
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remap = (uint16_t)STM32_DT_PINMUX_REMAP(pinctrl[0].pinmux);
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/* not remappable */
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if (remap == NO_REMAP) {
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return 0;
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}
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for (size_t i = 1U; i < list_size; i++) {
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if (STM32_DT_PINMUX_REMAP(pinctrl[i].pinmux) != remap) {
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return -EINVAL;
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}
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}
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/* A valid remapping configuration is available */
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/* Apply remapping before proceeding with pin configuration */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
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if (STM32_REMAP_REG_GET(remap) == 0U) {
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/* read initial value, ignore write-only SWJ_CFG */
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reg_val = AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG;
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reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
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/* apply undocumented '111' (AFIO_MAPR_SWJ_CFG) to affirm SWJ_CFG */
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/* the pins are not remapped without that (when SWJ_CFG is not default) */
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AFIO->MAPR = reg_val | AFIO_MAPR_SWJ_CFG;
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} else {
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reg_val = AFIO->MAPR2;
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reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
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AFIO->MAPR2 = reg_val;
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}
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return 0;
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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@ -1,113 +0,0 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file header for STM32 pin multiplexing
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*/
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#ifndef ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_
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#define ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_
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#include <zephyr/types.h>
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#include <zephyr/drivers/clock_control.h>
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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#include <zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h>
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#else
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief structure to convey pinctrl information for stm32 soc
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* value
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*/
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struct soc_gpio_pinctrl {
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uint32_t pinmux;
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uint32_t pincfg;
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};
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/**
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* @brief helper to extract IO port number from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_PORT(__pin) \
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(((__pin) >> STM32_PORT_SHIFT) & STM32_PORT_MASK)
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/**
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* @brief helper to extract IO pin number from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_LINE(__pin) \
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(((__pin) >> STM32_LINE_SHIFT) & STM32_LINE_MASK)
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/**
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* @brief helper to extract IO pin func from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_FUNC(__pin) \
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(((__pin) >> STM32_MODE_SHIFT) & STM32_MODE_MASK)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/**
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* @brief helper to extract IO pin remap from STM32_PINMUX() encoded
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* value
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*/
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#define STM32_DT_PINMUX_REMAP(__pin) \
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(((__pin) >> STM32_REMAP_SHIFT) & STM32_REMAP_MASK)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief helper to extract IO port number from STM32PIN() encoded
|
||||
* value
|
||||
*/
|
||||
#define STM32_PORT(__pin) \
|
||||
((__pin) >> 4)
|
||||
|
||||
/**
|
||||
* @brief helper to extract IO pin number from STM32PIN() encoded
|
||||
* value
|
||||
*/
|
||||
#define STM32_PIN(__pin) \
|
||||
((__pin) & 0xf)
|
||||
|
||||
/**
|
||||
* @brief helper for converting dt stm32 pinctrl format to existing pin config
|
||||
* format
|
||||
*
|
||||
* @param *pinctrl pointer to soc_gpio_pinctrl list
|
||||
* @param list_size list size
|
||||
* @param base device base register value
|
||||
*
|
||||
* @return 0 on success, -EINVAL otherwise
|
||||
*/
|
||||
int stm32_dt_pinctrl_configure(const struct soc_gpio_pinctrl *pinctrl,
|
||||
size_t list_size, uint32_t base);
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
|
||||
/**
|
||||
* @brief Helper function to check and apply provided pinctrl remap
|
||||
* configuration
|
||||
*
|
||||
* Check operation verifies that pin remapping configuration is the same on all
|
||||
* pins. If configuration is valid AFIO clock is enabled and remap is applied
|
||||
*
|
||||
* @param *pinctrl pointer to soc_gpio_pinctrl list
|
||||
* @param list_size list size
|
||||
*
|
||||
* @return 0 value on success, -EINVAL otherwise
|
||||
*/
|
||||
int stm32_dt_pinctrl_remap(const struct soc_gpio_pinctrl *pinctrl,
|
||||
size_t list_size);
|
||||
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32_H_ */
|
||||
|
|
@ -29,10 +29,6 @@ config CLOCK_CONTROL_INIT_PRIORITY
|
|||
default 1
|
||||
depends on CLOCK_CONTROL
|
||||
|
||||
config PINMUX_STM32
|
||||
default y
|
||||
depends on PINMUX
|
||||
|
||||
config MEMC_STM32
|
||||
default y
|
||||
depends on MEMC
|
||||
|
|
|
|||
|
|
@ -1,300 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Linaro Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/** @file
|
||||
* @brief ST STM32 MCU family devicetree helper macros
|
||||
*/
|
||||
|
||||
#ifndef _ST_STM32_DT_H_
|
||||
#define _ST_STM32_DT_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
/* Devicetree related macros to construct pinctrl config data */
|
||||
|
||||
#if !defined(CONFIG_PINCTRL_STM32)
|
||||
#define STM32_NO_PULL 0x0
|
||||
#define STM32_PULL_UP 0x1
|
||||
#define STM32_PULL_DOWN 0x2
|
||||
#define STM32_PUSH_PULL 0x0
|
||||
#define STM32_OPEN_DRAIN 0x1
|
||||
#endif /* CONFIG_PINCTRL_STM32 */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Internal: Get a node identifier for an element in a
|
||||
* pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @return elements's node identifier
|
||||
*/
|
||||
#define ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL(inst, x, i) \
|
||||
DT_INST_PINCTRL_BY_IDX(inst, x, i)
|
||||
|
||||
/**
|
||||
* @brief Internal: Get a node identifier for an element in a
|
||||
* pinctrl-x property for a given device
|
||||
*
|
||||
* @param name device node label identifier
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @return elements's node identifier
|
||||
*/
|
||||
#define ST_STM32_DT_NODE_ID_FROM_PINCTRL(name, x, i) \
|
||||
DT_PINCTRL_BY_IDX(DT_NODELABEL(name), x, i)
|
||||
|
||||
/**
|
||||
* @brief Internal: Get pinmux property of a node identifier for an element
|
||||
* in a pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @return pinmux property value
|
||||
*/
|
||||
#define ST_STM32_DT_INST_PINMUX(inst, x, i) \
|
||||
DT_PROP(ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL(inst, x, i), pinmux)
|
||||
|
||||
/**
|
||||
* @brief Internal: Get pinmux property of a node identifier for an element
|
||||
* in a pinctrl-x property for a given device
|
||||
*
|
||||
* @param name device node label identifier
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @return pinmux property value
|
||||
*/
|
||||
#define ST_STM32_DT_PINMUX(name, x, i) \
|
||||
DT_PROP(ST_STM32_DT_NODE_ID_FROM_PINCTRL(name, x, i), pinmux)
|
||||
|
||||
/**
|
||||
* @brief Internal: Get <function> property of a node identifier for an element
|
||||
* in a pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @param function property of a targeted element
|
||||
* @return <function> property value
|
||||
*/
|
||||
#define ST_STM32_DT_INST_FUNC(inst, x, i, function) \
|
||||
DT_PROP(ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL(inst, x, i), function)
|
||||
|
||||
/**
|
||||
* @brief Internal: Get <function> property of a node identifier for an element
|
||||
* in a pinctrl-x property for a given device
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param name device node label identifier
|
||||
* @param function property of a targeted element
|
||||
* @return <function> property value
|
||||
*/
|
||||
#define ST_STM32_DT_FUNC(name, x, i, function) \
|
||||
DT_PROP(ST_STM32_DT_NODE_ID_FROM_PINCTRL(name, x, i), function)
|
||||
|
||||
/**
|
||||
* @brief Internal: Provide slew-rate value for a pin with index i of a
|
||||
* pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @return slew rate value
|
||||
*/
|
||||
#define ST_STM32_DT_INST_SLEW_RATE(inst, x, i) \
|
||||
DT_ENUM_IDX(ST_STM32_DT_INST_NODE_ID_FROM_PINCTRL(inst, x, i), \
|
||||
slew_rate)
|
||||
|
||||
/**
|
||||
* @brief Internal: Provide slew-rate value for a pin with index i of a
|
||||
* pinctrl-x property for a given device
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param name device node label identifier
|
||||
* @return slew rate value
|
||||
*/
|
||||
#define ST_STM32_DT_SLEW_RATE(name, x, i) \
|
||||
DT_ENUM_IDX(ST_STM32_DT_NODE_ID_FROM_PINCTRL(name, x, i), slew_rate)
|
||||
|
||||
/**
|
||||
* @brief Internal: Construct a pincfg field of a soc_gpio_pinctrl element
|
||||
* with index i of a pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param inst device instance number
|
||||
* @return pincfg field
|
||||
*/
|
||||
#ifndef CONFIG_SOC_SERIES_STM32F1X
|
||||
#define ST_STM32_DT_INST_PINCFG(inst, x, i) \
|
||||
(((STM32_NO_PULL * ST_STM32_DT_INST_FUNC(inst, x, i, bias_disable)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PULL_UP * ST_STM32_DT_INST_FUNC(inst, x, i, bias_pull_up)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PULL_DOWN * ST_STM32_DT_INST_FUNC(inst, x, i, bias_pull_down)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PUSH_PULL * ST_STM32_DT_INST_FUNC(inst, x, i, drive_push_pull))\
|
||||
<< STM32_OTYPER_SHIFT) | \
|
||||
((STM32_OPEN_DRAIN * ST_STM32_DT_INST_FUNC(inst, x, i, \
|
||||
drive_open_drain)) \
|
||||
<< STM32_OTYPER_SHIFT) | \
|
||||
(ST_STM32_DT_INST_SLEW_RATE(inst, x, i) << STM32_OSPEEDR_SHIFT))
|
||||
#else
|
||||
#define ST_STM32_DT_INST_PINCFG(inst, x, i) \
|
||||
(((STM32_NO_PULL * ST_STM32_DT_INST_FUNC(inst, x, i, bias_disable)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PULL_UP * ST_STM32_DT_INST_FUNC(inst, x, i, bias_pull_up)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PULL_DOWN * ST_STM32_DT_INST_FUNC(inst, x, i, bias_pull_down)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PUSH_PULL * ST_STM32_DT_INST_FUNC(inst, x, i, drive_push_pull))\
|
||||
<< STM32_CNF_OUT_0_SHIFT) | \
|
||||
((STM32_OPEN_DRAIN * ST_STM32_DT_INST_FUNC(inst, x, i, \
|
||||
drive_open_drain)) \
|
||||
<< STM32_CNF_OUT_0_SHIFT) | \
|
||||
(ST_STM32_DT_INST_SLEW_RATE(inst, x, i) << STM32_MODE_OSPEED_SHIFT))
|
||||
#endif /* CONFIG_SOC_SERIES_STM32F1X */
|
||||
|
||||
/**
|
||||
* @brief Internal: Construct a pincfg field of a soc_gpio_pinctrl element
|
||||
* with index i of a pinctrl-x property for a given device
|
||||
*
|
||||
* @param i index of soc_gpio_pinctrl element
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param name device node label identifier
|
||||
* @return pincfg field
|
||||
*/
|
||||
#ifndef CONFIG_SOC_SERIES_STM32F1X
|
||||
#define ST_STM32_DT_PINCFG(name, x, i) \
|
||||
(((STM32_NO_PULL * ST_STM32_DT_FUNC(name, x, i, bias_disable)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PULL_UP * ST_STM32_DT_FUNC(name, x, i, bias_pull_up)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PULL_DOWN * ST_STM32_DT_FUNC(name, x, i, bias_pull_down)) \
|
||||
<< STM32_PUPDR_SHIFT) | \
|
||||
((STM32_PUSH_PULL * ST_STM32_DT_FUNC(name, x, i, drive_push_pull)) \
|
||||
<< STM32_OTYPER_SHIFT) | \
|
||||
((STM32_OPEN_DRAIN * ST_STM32_DT_FUNC(name, x, i, drive_open_drain))\
|
||||
<< STM32_OTYPER_SHIFT) | \
|
||||
(ST_STM32_DT_SLEW_RATE(name, x, i) << STM32_OSPEEDR_SHIFT))
|
||||
#else
|
||||
#define ST_STM32_DT_PINCFG(name, x, i) \
|
||||
(((STM32_NO_PULL * ST_STM32_DT_FUNC(name, x, i, bias_disable)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PULL_UP * ST_STM32_DT_FUNC(name, x, i, bias_pull_up)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PULL_DOWN * ST_STM32_DT_FUNC(name, x, i, bias_pull_down)) \
|
||||
<< STM32_PUPD_SHIFT) | \
|
||||
((STM32_PUSH_PULL * ST_STM32_DT_FUNC(name, x, i, drive_push_pull)) \
|
||||
<< STM32_CNF_OUT_0_SHIFT) | \
|
||||
((STM32_OPEN_DRAIN * ST_STM32_DT_FUNC(name, x, i, drive_open_drain))\
|
||||
<< STM32_CNF_OUT_0_SHIFT) | \
|
||||
(ST_STM32_DT_SLEW_RATE(name, x, i) << STM32_MODE_OSPEED_SHIFT))
|
||||
#endif /* CONFIG_SOC_SERIES_STM32F1X */
|
||||
|
||||
/**
|
||||
* @brief Internal: Construct a soc_gpio_pinctrl element index i of
|
||||
* a pinctrl-x property for a given device instance inst
|
||||
*
|
||||
* @param i element index
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param inst device instance number
|
||||
* @return soc_gpio_pinctrl element
|
||||
*/
|
||||
#define ST_STM32_DT_INST_PIN_ELEM(i, x, inst) \
|
||||
{ \
|
||||
ST_STM32_DT_INST_PINMUX(inst, x, i), \
|
||||
ST_STM32_DT_INST_PINCFG(inst, x, i) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Internal: Construct a soc_gpio_pinctrl element index i of
|
||||
* a pinctrl-x property for a given device
|
||||
*
|
||||
* @param i element index
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @param name device node label identifier
|
||||
* @return soc_gpio_pinctrl element
|
||||
*/
|
||||
#define ST_STM32_DT_PIN_ELEM(i, x, name) \
|
||||
{ \
|
||||
ST_STM32_DT_PINMUX(name, x, i), \
|
||||
ST_STM32_DT_PINCFG(name, x, i) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Internal: Return the number of elements of a pinctrl-x property
|
||||
* for a given device instance
|
||||
*
|
||||
* This macro returns the number of element in property pcintrl-<x> of
|
||||
* device instance <inst>
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @return number of element in property
|
||||
*/
|
||||
#define ST_STM32_DT_INST_NUM_PINS(inst, x) DT_INST_NUM_PINCTRLS_BY_IDX(inst, x)
|
||||
|
||||
/**
|
||||
* @brief Internal: Return the number of elements of a pinctrl-x property
|
||||
* for a given device
|
||||
*
|
||||
* This macro returns the number of element in property pcintrl-<x> of
|
||||
* device "name"
|
||||
*
|
||||
* @param name device node label identifier
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @return number of element in property
|
||||
*/
|
||||
#define ST_STM32_DT_NUM_PINS(name, x) \
|
||||
DT_NUM_PINCTRLS_BY_IDX(DT_NODELABEL(name), x)
|
||||
|
||||
/**
|
||||
* @brief Construct a soc_gpio_pinctrl array of a specific pcintrl property
|
||||
* for a given device instance
|
||||
*
|
||||
* This macro returns an array of soc_gpio_pinctrl, each line matching a pinctrl
|
||||
* configuration provided in property pcintrl-<x> of device instance <inst>
|
||||
*
|
||||
* @param inst device instance number
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @return array of soc_gpio_pinctrl
|
||||
*/
|
||||
#define ST_STM32_DT_INST_PINCTRL(inst, x) \
|
||||
{ COND_CODE_1(DT_INST_PINCTRL_HAS_IDX(inst, x), \
|
||||
(LISTIFY(ST_STM32_DT_INST_NUM_PINS(inst, x), \
|
||||
ST_STM32_DT_INST_PIN_ELEM, (,), \
|
||||
x, \
|
||||
inst)), \
|
||||
()) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a soc_gpio_pinctrl array of a specific pcintrl property
|
||||
* for a given device name
|
||||
*
|
||||
* This macro returns an array of soc_gpio_pinctrl, each line matching a pinctrl
|
||||
* configuration provided in property pcintrl-<x> of a device referenced by
|
||||
* its node label identifier.
|
||||
*
|
||||
* @param name device node label identifier
|
||||
* @param x index of targeted pinctrl- property (eg: pinctrl-<x>)
|
||||
* @return array of soc_gpio_pinctrl
|
||||
*/
|
||||
#define ST_STM32_DT_PINCTRL(name, x) \
|
||||
{ COND_CODE_1(DT_PINCTRL_HAS_IDX(DT_NODELABEL(name), x), \
|
||||
(LISTIFY(ST_STM32_DT_NUM_PINS(name, x), \
|
||||
ST_STM32_DT_PIN_ELEM, (,), \
|
||||
x, \
|
||||
name)), \
|
||||
()) \
|
||||
}
|
||||
|
||||
#endif /* _ST_STM32_DT_H_ */
|
||||
|
|
@ -26,9 +26,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F0_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -26,9 +26,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F1_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -25,9 +25,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F2_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -27,9 +27,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F3_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -26,9 +26,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F4_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -25,9 +25,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F7_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -22,9 +22,6 @@
|
|||
|
||||
#include <stm32g0xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32G0_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32g4xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32G4_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -11,9 +11,6 @@
|
|||
|
||||
#include <stm32h7xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32F7_SOC_H7_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32l0xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32L0_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32l1xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32L1_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -27,9 +27,6 @@
|
|||
#undef CAN_MODE_NORMAL
|
||||
#undef CAN_MODE_LOOPBACK
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32L4X_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32l5xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32L5_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32mp1xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32MP1SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -17,9 +17,6 @@
|
|||
|
||||
#include <stm32u5xx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32U5_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32wbxx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32WBX_SOC_H_ */
|
||||
|
|
|
|||
|
|
@ -21,9 +21,6 @@
|
|||
|
||||
#include <stm32wlxx.h>
|
||||
|
||||
/* Add generated devicetree information and STM32 helper macros */
|
||||
#include <st_stm32_dt.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _STM32WL_SOC_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue