soc: arm: add Renesas rcar_gen3 series support

Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.

- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2

Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).

This first SoC definition is just enough to print Hello World in a
ram console.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>

CODEOWNERS

@@ -53,6 +53,7 @@
 /soc/arm/ti_simplelink/cc32xx/            @vanti
 /soc/arm/ti_simplelink/msp432p4xx/        @Mani-Sadhasivam
 /soc/arm/xilinx_zynqmp/                   @stephanosio
+/soc/arm/renesas_rcar/                    @julien-massot
 /soc/xtensa/intel_s1000/                  @sathishkuttan @dcpleung
 /soc/arm64/                               @carlocaione
 /soc/arm64/qemu_cortex_a53/               @carlocaione
@@ -364,6 +365,7 @@
 /dts/arm/armv*m.dtsi                      @galak @ioannisg
 /dts/arm/armv7-r.dtsi                     @bbolen @stephanosio
 /dts/arm/xilinx/                          @bbolen @stephanosio
+/dts/arm/renesas/                         @julien-massot
 /dts/x86/                                 @jhedberg
 /dts/xtensa/xtensa.dtsi                   @ydamigos
 /dts/xtensa/intel/                        @dcpleung

dts/arm/renesas/gen3/r8a77951.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <renesas/gen3/rcar_gen3_cr7.dtsi>

dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2021 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-r.dtsi>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r7";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		sram0: memory@40040000 {
+			compatible = "mmio-sram";
+			reg = <0x40040000 0x1fc0000>;
+		};
+
+		gic: interrupt-controller@f1110000 {
+			compatible = "arm,gic";
+			reg = <0xf1110000 0x1000>,
+			      <0xf1120000 0x20000>,
+			      <0xf1140000 0x20000>,
+			      <0xf1060000 0x20000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			label = "GIC";
+			status = "okay";
+		};
+	};
+};

soc/arm/renesas_rcar/CMakeLists.txt

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})

soc/arm/renesas_rcar/Kconfig

@@ -0,0 +1,17 @@
+# Renesas R-Car SoC line
+
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_RCAR
+	bool
+
+if SOC_FAMILY_RCAR
+
+config SOC_FAMILY
+	string
+	default "renesas_rcar"
+
+source "soc/arm/renesas_rcar/*/Kconfig.soc"
+
+endif # SOC_FAMILY_RCAR

soc/arm/renesas_rcar/Kconfig.defconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/renesas_rcar/*/Kconfig.defconfig.series"

soc/arm/renesas_rcar/Kconfig.soc

@@ -0,0 +1,7 @@
+# Renesas R-Car SoC line
+
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+
+source "soc/arm/renesas_rcar/*/Kconfig.series"

soc/arm/renesas_rcar/gen3/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+)

soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_R8A77950
+
+config SOC
+	default "r8a77951"
+
+endif # SOC_R8A77950

soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series

@@ -0,0 +1,14 @@
+# Renesas R-Car Gen3 SoC line
+
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RCAR_GEN3
+
+config SOC_SERIES
+	default "gen3"
+
+config NUM_IRQS
+	default 512
+
+endif # SOC_SERIES_RCAR_GEN3

soc/arm/renesas_rcar/gen3/Kconfig.series

@@ -0,0 +1,12 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RCAR_GEN3
+	bool "Renesas RCAR Gen3 Cortex R7"
+	select ARM
+	select CPU_CORTEX_R7
+	select GIC_V2
+	select CPU_HAS_DCLS
+	select SOC_FAMILY_RCAR
+	help
+	  Enable support for Renesas RCar Gen3 SoC series

soc/arm/renesas_rcar/gen3/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Renesas RCar SoC Selection"
+	depends on SOC_SERIES_RCAR_GEN3
+
+config SOC_R8A77951
+	bool "R8A77951"
+
+endchoice

soc/arm/renesas_rcar/gen3/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_a_r/scripts/linker.ld>

soc/arm/renesas_rcar/gen3/soc.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * @return 0
+ */
+
+static int soc_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+	return 0;
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/arm/renesas_rcar/gen3/soc.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+/* Define CMSIS configurations */
+#define __CR_REV      1U
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+
+#endif /* _SOC__H_ */