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dts: adsp: ace15: replace hp with ipll clock

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The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.

Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2023-09-08 13:39:43 +02:00 committed by Fabio Baltieri
parent 2f2689e3d3
commit dcecda859c
1 changed files with 1 additions and 1 deletions
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2
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
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@ -82,7 +82,7 @@
compatible = "intel,adsp-shim-clkctl";
adsp-clkctl-clk-wovcro = <0>;
adsp-clkctl-clk-lpro = <1>;
adsp-clkctl-clk-hpro = <2>;
adsp-clkctl-clk-ipll = <2>;
adsp-clkctl-freq-enc = <0xc 0x0 0x4>;
adsp-clkctl-freq-mask = <0x0 0x0 0x0>;
adsp-clkctl-freq-default = <2>;