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dts: bindings: Fix xlnx,ttcps binding compat

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The `xlnx,ttcps` binding, despite having the file name of
`xlnx,ttcps.yaml`, had the compatible property of `cdns,ttc`.

While it is true that the Xilinx ZynqMP platform embeds the Cadence
Triple Timer Counter (TTC) IP core, its TTC differs from the original
Cadence core in that it implements 32-bit counters, instead of the
16-bit counters defined in the original; hence, the Xilinx variant is
not compatible with the original Cadence version and should be treated
as a different device.

This commit changes the `xlnx,ttcps.yaml` compatible property to
`xlnx,ttcps` for the above reasons.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-03-18 13:45:28 +09:00 committed by Anas Nashif
parent 7b1a6606ad
commit dd75bccaca
3 changed files with 7 additions and 7 deletions
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8
dts/arm/xilinx/zynqmp.dtsi
View file

@ -31,7 +31,7 @@
};
ttc0: timer@ff110000 {
compatible = "cdns,ttc";
compatible = "xlnx,ttcps";
status = "disabled";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
@ -45,7 +45,7 @@
};
ttc1: timer@ff120000 {
compatible = "cdns,ttc";
compatible = "xlnx,ttcps";
status = "disabled";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
@ -59,7 +59,7 @@
};
ttc2: timer@ff130000 {
compatible = "cdns,ttc";
compatible = "xlnx,ttcps";
status = "disabled";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
@ -73,7 +73,7 @@
};
ttc3: timer@ff140000 {
compatible = "cdns,ttc";
compatible = "xlnx,ttcps";
status = "disabled";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,

4
dts/bindings/timer/xlnx,ttcps.yaml
View file

@ -1,6 +1,6 @@
description: Xilinx ZynqMP PS TTC timer
compatible: "cdns,ttc"
compatible: "xlnx,ttcps"
include: base.yaml
@ -13,5 +13,5 @@ properties:
clock-frequency:
type: int
required: false
required: true
description: Clock frequency information for Timer operation

2
tests/kernel/context/src/main.c
View file

@ -70,7 +70,7 @@
#elif defined(CONFIG_RV32M1_LPTMR_TIMER)
#define TICK_IRQ DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ_0
#elif defined(CONFIG_XLNX_PSTTC_TIMER)
#define TICK_IRQ DT_INST_0_CDNS_TTC_IRQ_0
#define TICK_IRQ DT_INST_0_XLNX_TTCPS_IRQ_0
#elif defined(CONFIG_CPU_CORTEX_M)
/*
* The Cortex-M use the SYSTICK exception for the system timer, which is