From de44a6c0c67a332695209344f3227d80450b64b7 Mon Sep 17 00:00:00 2001 From: Grant Ramsay Date: Mon, 7 Aug 2023 15:06:40 +1200 Subject: [PATCH] dts: arm64: qemu: Fix invalid PCIe interrupt-map node The interrupt-map was missing the priority field. This causes a build failure when trying to use it. The lines are split to fit into the 100 column limit. Signed-off-by: Grant Ramsay --- dts/arm64/qemu/qemu-virt-a53.dtsi | 48 +++++++++++++++++++---------- dts/arm64/qemu/qemu-virt-arm64.dtsi | 48 +++++++++++++++++++---------- 2 files changed, 64 insertions(+), 32 deletions(-) diff --git a/dts/arm64/qemu/qemu-virt-a53.dtsi b/dts/arm64/qemu/qemu-virt-a53.dtsi index 1839c2726a..cb96eba287 100644 --- a/dts/arm64/qemu/qemu-virt-a53.dtsi +++ b/dts/arm64/qemu/qemu-virt-a53.dtsi @@ -112,25 +112,41 @@ 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; #interrupt-cells = <0x01>; interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE + interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE + 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE + 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE>; + 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; msi-parent = <&its>; bus-range = <0x00 0xff>; }; diff --git a/dts/arm64/qemu/qemu-virt-arm64.dtsi b/dts/arm64/qemu/qemu-virt-arm64.dtsi index 0460c70f07..dd6916fe4d 100644 --- a/dts/arm64/qemu/qemu-virt-arm64.dtsi +++ b/dts/arm64/qemu/qemu-virt-arm64.dtsi @@ -112,25 +112,41 @@ 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; #interrupt-cells = <0x01>; interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE + interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE + 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE + 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE - 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE>; + 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY + 0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; msi-parent = <&its>; bus-range = <0x00 0xff>; };