patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

drivers: ethernet: sam_gmac: rework pin config

Browse source 
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h

We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-30 13:25:19 -05:00 committed by Kumar Gala
parent 77e0b498ac
commit dff8715615
9 changed files with 79 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/ethernet/eth_sam_gmac.c
View file

@ -1103,7 +1103,7 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val)
/* Setup Network Configuration Register */
gmac->GMAC_NCFGR = gmac_ncfgr_val | mck_divisor;
gmac->GMAC_UR = DT_ENUM_IDX(DT_NODELABEL(gmac), phy_connection_type);
gmac->GMAC_UR = DT_ENUM_IDX(DT_DRV_INST(0), phy_connection_type);
#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
/* Initialize PTP Clock Registers */
@ -2201,7 +2201,7 @@ static void eth0_irq_config(void)
}
#ifdef CONFIG_SOC_FAMILY_SAM
static const struct soc_gpio_pin pins_eth0[] = PINS_GMAC0;
static const struct soc_gpio_pin pins_eth0[] = ATMEL_SAM_DT_PINS(0);
#endif
static const struct eth_sam_dev_cfg eth0_config = {

20
dts/arm/atmel/sam4e-pinctrl.dtsi
View file

@ -10,6 +10,26 @@
soc {
pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(gmac, gcol, d, 13, a);
DT_ATMEL_PIN(gmac, gcrs, d, 10, a);
DT_ATMEL_PIN(gmac, gcrsdv, d, 4, a);
DT_ATMEL_PIN(gmac, grxdv, d, 4, a);
DT_ATMEL_PIN(gmac, gmdc, d, 8, a);
DT_ATMEL_PIN(gmac, gmdio, d, 9, a);
DT_ATMEL_PIN(gmac, grx0, d, 5, a);
DT_ATMEL_PIN(gmac, grx1, d, 6, a);
DT_ATMEL_PIN(gmac, grx2, d, 11, a);
DT_ATMEL_PIN(gmac, grx3, d, 12, a);
DT_ATMEL_PIN(gmac, grxck, d, 14, a);
DT_ATMEL_PIN(gmac, grxer, d, 7, a);
DT_ATMEL_PIN(gmac, gtx0, d, 2, a);
DT_ATMEL_PIN(gmac, gtx1, d, 3, a);
DT_ATMEL_PIN(gmac, gtx2, d, 15, a);
DT_ATMEL_PIN(gmac, gtx3, d, 16, a);
DT_ATMEL_PIN(gmac, gtxck, d, 0, a);
DT_ATMEL_PIN(gmac, grefck, d, 0, a);
DT_ATMEL_PIN(gmac, gtxen, d, 1, a);
DT_ATMEL_PIN(gmac, gtxer, d, 17, a);
DT_ATMEL_PIN(spi, miso, a, 12, a);
DT_ATMEL_PIN(spi, mosi, a, 13, a);
DT_ATMEL_PIN(spi, npcs0, a, 11, a);

10
dts/arm/atmel/sam4e.dtsi
View file

@ -153,6 +153,16 @@
phy-connection-type = "mii";
label = "GMAC";
status = "disabled";
/* Default to MII config */
pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
&pd2a_gmac_gtx0 &pd3a_gmac_gtx1
&pd15a_gmac_gtx2 &pd16a_gmac_gtx3
&pd4a_gmac_grxdv &pd7a_gmac_grxer
&pd14a_gmac_grxck &pd5a_gmac_grx0
&pd6a_gmac_grx1 &pd11a_gmac_grx2
&pd12a_gmac_grx3 &pd13a_gmac_gcol
&pd10a_gmac_gcrs &pd8a_gmac_gmdc
&pd9a_gmac_gmdio>;
};
pinctrl@400e0e00 {

22
dts/arm/atmel/same70-pinctrl.dtsi
View file

@ -12,6 +12,28 @@
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(afec0, adtrg, a, 8, b);
DT_ATMEL_PIN(afec1, adtrg, d, 9, c);
DT_ATMEL_PIN(gmac, gcol, d, 13, a);
DT_ATMEL_PIN(gmac, gcrs, d, 10, a);
DT_ATMEL_PIN(gmac, gmdc, d, 8, a);
DT_ATMEL_PIN(gmac, gmdio, d, 9, a);
DT_ATMEL_PIN(gmac, grxck, d, 14, a);
DT_ATMEL_PIN(gmac, grxdv, d, 4, a);
DT_ATMEL_PIN(gmac, grxer, d, 7, a);
DT_ATMEL_PIN(gmac, grx0, d, 5, a);
DT_ATMEL_PIN(gmac, grx1, d, 6, a);
DT_ATMEL_PIN(gmac, grx2, d, 11, a);
DT_ATMEL_PIN(gmac, grx3, d, 12, a);
DT_ATMEL_PIN(gmac, gtsucomp, b, 1, b);
DT_ATMEL_PIN(gmac, gtsucomp, b, 12, b);
DT_ATMEL_PIN(gmac, gtsucomp, d, 11, c);
DT_ATMEL_PIN(gmac, gtsucomp, d, 20, c);
DT_ATMEL_PIN(gmac, gtxck, d, 0, a);
DT_ATMEL_PIN(gmac, gtxen, d, 1, a);
DT_ATMEL_PIN(gmac, gtxer, d, 17, a);
DT_ATMEL_PIN(gmac, gtx0, d, 2, a);
DT_ATMEL_PIN(gmac, gtx1, d, 3, a);
DT_ATMEL_PIN(gmac, gtx2, d, 15, a);
DT_ATMEL_PIN(gmac, gtx3, d, 16, a);
DT_ATMEL_PIN(spi0, miso, d, 20, b);
DT_ATMEL_PIN(spi0, mosi, d, 21, b);
DT_ATMEL_PIN(spi0, npcs0, b, 2, d);

6
dts/arm/atmel/same70.dtsi
View file

@ -347,6 +347,12 @@
local-mac-address = [00 00 00 00 00 00];
label = "GMAC";
status = "disabled";
/* Default to RMII config */
pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
&pd2a_gmac_gtx0 &pd3a_gmac_gtx1
&pd4a_gmac_grxdv &pd5a_gmac_grx0
&pd6a_gmac_grx1 &pd7a_gmac_grxer
&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
};
trng: random@40070000 {

19
dts/bindings/ethernet/atmel,sam-gmac.yaml
View file

@ -40,3 +40,22 @@ properties:
- "rmii"
- "mii"
default: "rmii"
pinctrl-0:
type: phandles
required: false
description: |
PIO pin configuration for the various GMAC signals that include
GTXCK, GTXEN, GTX[3..0], GTXER, GRXCK, GRXDV, GRX[3..0], GRXER,
GCRS, GCOL, GMDC, and GMDIO. Which signals are used vary based
on if the PHY connection is MII or RMII (see datasheet for more
details). We expect that the phandles will reference pinctrl nodes.
These nodes will have a nodelabel that matches the Atmel SoC HAL
defines and be of the form p<port><pin><periph>_<inst>_<signal>.
For example the GMAC on SAME7x would be for RMII
pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
&pd2a_gmac_gtx0 &pd3a_gmac_gtx1
&pd4a_gmac_grxdv &pd5a_gmac_grx0
&pd6a_gmac_grx1 &pd7a_gmac_grxer
&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;

11
soc/arm/atmel_sam/sam4e/soc_pinmap.h
View file

@ -17,15 +17,4 @@
#include <soc.h>
/* Ethernet MAC (GMAC) */
#define PINS_GMAC_MASK (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | \
PIO_PD2A_GTX0 | PIO_PD3A_GTX1 | PIO_PD15A_GTX2 | \
PIO_PD16A_GTX3 | PIO_PD4A_GRXDV | PIO_PD7A_GRXER | \
PIO_PD14A_GRXCK | PIO_PD5A_GRX0 | PIO_PD6A_GRX1 | \
PIO_PD11A_GRX2 | PIO_PD12A_GRX3 | PIO_PD13A_GCOL | \
PIO_PD10A_GCRS | PIO_PD8A_GMDC | PIO_PD9A_GMDIO)
#define PIN_GMAC_SET1 {PINS_GMAC_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_A}
#define PINS_GMAC0 {PIN_GMAC_SET1}
#endif /* _ATMEL_SAM4E_SOC_PINMAP_H_ */

10
soc/arm/atmel_sam/same70/soc_pinmap.h
View file

@ -15,16 +15,6 @@
#include <soc.h>
/* Ethernet MAC (GMAC) */
#define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \
| PIO_PD2A_GMAC_GTX0 | PIO_PD3A_GMAC_GTX1 | PIO_PD4A_GMAC_GRXDV \
| PIO_PD5A_GMAC_GRX0 | PIO_PD6A_GMAC_GRX1 | PIO_PD7A_GMAC_GRXER \
| PIO_PD8A_GMAC_GMDC | PIO_PD9A_GMAC_GMDIO)
#define PIN_GMAC_SET1 {PINS_GMAC_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_A}
#define PINS_GMAC0 {PIN_GMAC_SET1}
/* Synchronous Serial Controller (SSC) */
#define PIN_SSC0_RD {PIO_PA10C_SSC_RD, PIOA, ID_PIOA, SOC_GPIO_FUNC_C}

10
soc/arm/atmel_sam/samv71/soc_pinmap.h
View file

@ -16,16 +16,6 @@
#include <soc.h>
/* Ethernet MAC (GMAC) */
#define PINS_GMAC_MASK (PIO_PD0A_GMAC_GTXCK | PIO_PD1A_GMAC_GTXEN \
| PIO_PD2A_GMAC_GTX0 | PIO_PD3A_GMAC_GTX1 | PIO_PD4A_GMAC_GRXDV \
| PIO_PD5A_GMAC_GRX0 | PIO_PD6A_GMAC_GRX1 | PIO_PD7A_GMAC_GRXER \
| PIO_PD8A_GMAC_GMDC | PIO_PD9A_GMAC_GMDIO)
#define PIN_GMAC_SET1 {PINS_GMAC_MASK, PIOD, ID_PIOD, SOC_GPIO_FUNC_A}
#define PINS_GMAC0 {PIN_GMAC_SET1}
/* Synchronous Serial Controller (SSC) */
#define PIN_SSC0_RD {PIO_PA10C_SSC_RD, PIOA, ID_PIOA, SOC_GPIO_FUNC_C}