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riscv32: use device tree defines in linker

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Delete memory-related configs from defconfig and use device tree based
macros in general riscv32 linker script instead of Kconfig ones.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit is contained in:
Filip Kokosinski 2019-04-18 16:37:41 +02:00 committed by Maureen Helm
parent 2b61c37d04
commit e0a825003d
3 changed files with 2 additions and 34 deletions
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4
include/arch/riscv32/common/linker.ld
View file

@ -36,9 +36,9 @@
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
ROM (rx) : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)
#endif
RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE)
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

16
soc/riscv32/riscv-privilege/miv/Kconfig.defconfig.series
View file

@ -30,20 +30,4 @@ config XIP
bool
default y
config RISCV_ROM_BASE_ADDR
hex
default 0x80000000
config RISCV_ROM_SIZE
hex
default 0x40000
config RISCV_RAM_BASE_ADDR
hex
default 0x80040000
config RISCV_RAM_SIZE
hex
default 0x40000
endif # SOC_SERIES_RISCV32_MIV

16
soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.defconfig.series
View file

@ -30,20 +30,4 @@ config XIP
bool
default y
config RISCV_ROM_BASE_ADDR
hex
default 0x20400000
config RISCV_ROM_SIZE
hex
default 0xC00000
config RISCV_RAM_BASE_ADDR
hex
default 0x80000000
config RISCV_RAM_SIZE
hex
default 0x4000
endif # SOC_SERIES_RISCV32_SIFIVE_FREEDOM