nrf52_bsim: Provide more CMSIS headers and definitions

Including Exclusive store load and status clear.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>

boards/posix/nrf52_bsim/CMakeLists.txt

@@ -29,11 +29,12 @@ zephyr_library_sources(
 	main.c
 	time_machine.c
 	trace_hook.c
-	cmsis.c
+	cmsis/cmsis.c
 	soc/nrfx_coredep.c
 )
 
 zephyr_include_directories(soc)
+zephyr_include_directories(cmsis)
 
 zephyr_library_include_directories(
   $ENV{BSIM_COMPONENTS_PATH}/libUtilv1/src/

boards/posix/nrf52_bsim/board_irq.h

@@ -19,6 +19,8 @@ void posix_isr_declare(unsigned int irq_p, int flags, void isr_p(const void *),
 		       const void *isr_param_p);
 void posix_irq_priority_set(unsigned int irq, unsigned int prio,
 			    uint32_t flags);
+void nrfbsim_WFE_model(void);
+void nrfbsim_SEV_model(void);
 
 /**
  * Configure a static interrupt.

boards/posix/nrf52_bsim/cmsis/cmsis.c

@@ -10,6 +10,7 @@
 #include "posix_core.h"
 #include "posix_board_if.h"
 #include "board_soc.h"
+#include "bs_tracing.h"
 
 /*
  *  Replacement for ARMs NVIC functions()
@@ -46,8 +47,7 @@ uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 
 void NVIC_SystemReset(void)
 {
-	posix_print_warning("%s called. Exiting\n", __func__);
-	posix_exit(1);
+	bs_trace_error_time_line("%s called. Exiting\n", __func__);
 }
 
 /*
@@ -72,3 +72,18 @@ void __set_PRIMASK(uint32_t primask)
 {
 	hw_irq_ctrl_change_lock(primask != 0);
 }
+
+void __WFE(void)
+{
+	nrfbsim_WFE_model();
+}
+
+void __WFI(void)
+{
+	__WFE();
+}
+
+void __SEV(void)
+{
+	nrfbsim_SEV_model();
+}

boards/posix/nrf52_bsim/cmsis/cmsis.h

@@ -12,40 +12,27 @@
 #ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_H
 #define BOARDS_POSIX_NRF52_BSIM_CMSIS_H
 
+#include <stdint.h>
+#include "cmsis_instr.h"
+#include "nrf52833.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* Implement the following ARM intrinsics as no-op:
- * - ARM Data Synchronization Barrier
- * - ARM Data Memory Synchronization Barrier
- * - ARM Instruction Synchronization Barrier
- * - ARM No Operation
- */
-#ifndef __DMB
-#define __DMB()
-#endif
-
-#ifndef __DSB
-#define __DSB()
-#endif
-
-#ifndef __ISB
-#define __ISB()
-#endif
-
-#ifndef __NOP
-#define __NOP()
-#endif
-
 void __enable_irq(void);
-
 void __disable_irq(void);
-
 uint32_t __get_PRIMASK(void);
-
 void __set_PRIMASK(uint32_t primask);
 
+void NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void NVIC_DisableIRQ(IRQn_Type IRQn);
+void NVIC_EnableIRQ(IRQn_Type IRQn);
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+void NVIC_SystemReset(void);
+
 #ifdef __cplusplus
 }
 #endif

boards/posix/nrf52_bsim/cmsis/cmsis_instr.h

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Oticon A/S
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This header defines replacements for inline
+ * ARM Cortex-M CMSIS intrinsics.
+ */
+
+#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H
+#define BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H
+
+/* Implement the following ARM intrinsics as no-op:
+ * - ARM Data Synchronization Barrier
+ * - ARM Data Memory Synchronization Barrier
+ * - ARM Instruction Synchronization Barrier
+ * - ARM No Operation
+ */
+#ifndef __DMB
+#define __DMB()
+#endif
+
+#ifndef __DSB
+#define __DSB()
+#endif
+
+#ifndef __ISB
+#define __ISB()
+#endif
+
+#ifndef __NOP
+#define __NOP()
+#endif
+
+void __WFE(void);
+void __WFI(void);
+void __SEV(void);
+
+/*
+ *  Implement the following ARM intrinsics as non-exclusive accesses
+ *
+ *  - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
+ *  - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W})
+ *  - CLREX : Exclusive lock removal (__CLREX) - no-op
+ *
+ *  Description:
+ *    These accesses always succeed, and do NOT set any kind of internal
+ *    exclusive access flag;
+ *    There is no local/global memory monitors, MPU control of what are
+ *    shareable regions, exclusive reservations granules, automatic clearing
+ *    on context switch, or so.
+ *
+ *    This should be enough for the expected uses of LDR/STREXB
+ *    (locking mutexes or guarding other atomic operations, inside a few lines
+ *    of code in the same function): As the POSIX arch will not make an embedded
+ *    thread lose context while just executing its own code, and it does not
+ *    allow parallel embedded SW threads to execute at the same exact time,
+ *    there is no actual need to protect atomicity.
+ *
+ *    But as this ARM exclusive access monitor mechanism can in principle be
+ *    used for other, unexpected, purposes, this simple replacement may not be
+ *    enough.
+ */
+
+/**
+ * \brief   Pretend to execute a STR Exclusive (8 bit)
+ * \details Executes a ~exclusive~ STR instruction for 8 bit values.
+ * \param [in]  value  Value to store
+ * \param [in]    ptr  Pointer to location
+ * \return          0  Function succeeded (always)
+ */
+static inline uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr)
+{
+	*ptr = value;
+	return 0;
+}
+
+/**
+ * \brief   Pretend to execute a STR Exclusive (16 bit)
+ * \details Executes a ~exclusive~ STR instruction for 16 bit values.
+ * \param [in]  value  Value to store
+ * \param [in]    ptr  Pointer to location
+ * \return          0  Function succeeded (always)
+ */
+static inline uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr)
+{
+	*ptr = value;
+	return 0;
+}
+
+/**
+ * \brief   Pretend to execute a STR Exclusive (32 bit)
+ * \details Executes a ~exclusive~ STR instruction for 32 bit values.
+ * \param [in]  value  Value to store
+ * \param [in]    ptr  Pointer to location
+ * \return          0  Function succeeded (always)
+ */
+static inline uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr)
+{
+	*ptr = value;
+	return 0;
+}
+
+/**
+ * \brief   Pretend to execute a LDR Exclusive (8 bit)
+ * \details Executes an ~exclusive~ LDR instruction for 8 bit value.
+ *          Meaning, it does not set a exclusive lock,
+ *          instead just loads the stored value
+ * \param [in]    ptr  Pointer to data
+ * \return             value of type uint8_t at (*ptr)
+ */
+static inline uint8_t __LDREXB(volatile uint8_t *ptr)
+{
+	return *ptr;
+}
+
+/**
+ * \brief   Pretend to execute a LDR Exclusive (16 bit)
+ * \details Executes an ~exclusive~ LDR instruction for 16 bit value.
+ *          Meaning, it does not set a exclusive lock,
+ *          instead just loads the stored value
+ * \param [in]    ptr  Pointer to data
+ * \return             value of type uint8_t at (*ptr)
+ */
+static inline uint16_t __LDREXH(volatile uint16_t *ptr)
+{
+	return *ptr;
+}
+
+/**
+ * \brief   Pretend to execute a LDR Exclusive (32 bit)
+ * \details Executes an ~exclusive~ LDR instruction for 32 bit value.
+ *          Meaning, it does not set a exclusive lock,
+ *          instead just loads the stored value
+ * \param [in]    ptr  Pointer to data
+ * \return             value of type uint8_t at (*ptr)
+ */
+static inline uint32_t __LDREXW(volatile uint32_t *ptr)
+{
+	return *ptr;
+}
+
+/**
+ * \brief   Pretend to remove the exclusive lock
+ * \details The real function would removes the exclusive lock which is created
+ *          by LDREX, this one does nothing
+ */
+static inline void __CLREX(void) { /* Nothing to be done */ }
+
+#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_INSTR_H */

boards/posix/nrf52_bsim/irq_handler.c

@@ -327,7 +327,7 @@ void posix_irq_offload(void (*routine)(const void *), const void *parameter)
  */
 static bool CPU_event_set_flag;
 
-void __WFE(void)
+void nrfbsim_WFE_model(void)
 {
 	if (CPU_event_set_flag == false) {
 		CPU_will_be_awaken_from_WFE = true;
@@ -337,12 +337,7 @@ void __WFE(void)
 	CPU_event_set_flag = false;
 }
 
-void __WFI(void)
-{
-	__WFE();
-}
-
-void __SEV(void)
+void nrfbsim_SEV_model(void)
 {
 	CPU_event_set_flag = true;
 }