driver: add new gpio driver "gpio_mcux_rgpio"
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP. GPIO pinctrl, read/write and interrupt is supported. Runtime mmio configuration is enabled, so no need for region definition in mimx9/mmu_region.c Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
This commit is contained in:
Chekhov Ma
Anas Nashif
parent
2effad3b11
commit
e1d495be81
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@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MCP230XX gpio_mcp230xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BD8LB600FS gpio_bd8lb600fs.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX gpio_mcux.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_IGPIO gpio_mcux_igpio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_RGPIO gpio_mcux_rgpio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_LPC gpio_mcux_lpc.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MMIO32 gpio_mmio32.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XEC gpio_mchp_xec.c)
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@ -105,6 +105,8 @@ source "drivers/gpio/Kconfig.mcux"
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source "drivers/gpio/Kconfig.mcux_igpio"
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source "drivers/gpio/Kconfig.mcux_rgpio"
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source "drivers/gpio/Kconfig.mcux_lpc"
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source "drivers/gpio/Kconfig.mmio32"
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12
drivers/gpio/Kconfig.mcux_rgpio
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12
drivers/gpio/Kconfig.mcux_rgpio
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@ -0,0 +1,12 @@
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# MCUX RGPIO configuration options
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# Copyright 2023, NXP
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_MCUX_RGPIO
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bool "MCUX RGPIO driver"
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default y
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depends on DT_HAS_NXP_IMX_RGPIO_ENABLED
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select PINCTRL
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help
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Enable the MCUX RGPIO driver.
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308
drivers/gpio/gpio_mcux_rgpio.c
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308
drivers/gpio/gpio_mcux_rgpio.c
Normal file
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@ -0,0 +1,308 @@
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/*
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* Copyright 2023, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_rgpio
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <fsl_common.h>
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#include <fsl_rgpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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struct gpio_pin_gaps {
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uint8_t start;
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uint8_t len;
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};
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/* Required by DEVICE_MMIO_NAMED_* macros */
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#define DEV_CFG(_dev) \
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((const struct mcux_rgpio_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
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struct mcux_rgpio_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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DEVICE_MMIO_NAMED_ROM(reg_base);
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const struct pinctrl_soc_pinmux *pin_muxes;
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const struct gpio_pin_gaps *pin_gaps;
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uint8_t mux_count;
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uint8_t gap_count;
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};
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struct mcux_rgpio_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data general;
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DEVICE_MMIO_NAMED_RAM(reg_base);
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static int mcux_rgpio_configure(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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const struct mcux_rgpio_config *config = dev->config;
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struct pinctrl_soc_pin pin_cfg;
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int cfg_idx = pin, i;
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/* Some SOCs have non-contiguous gpio pin layouts, account for this */
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for (i = 0; i < config->gap_count; i++) {
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if (pin >= config->pin_gaps[i].start) {
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if (pin < (config->pin_gaps[i].start +
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config->pin_gaps[i].len)) {
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/* Pin is not connected to a mux */
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return -ENOTSUP;
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}
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cfg_idx -= config->pin_gaps[i].len;
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}
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}
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/* Init pin configuration struct, and use pinctrl api to apply settings */
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if (cfg_idx >= config->mux_count) {
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/* Pin is not connected to a mux */
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return -ENOTSUP;
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}
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/* Set appropriate bits in pin configuration register */
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volatile uint32_t *gpio_cfg_reg = (volatile uint32_t *)
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((size_t)config->pin_muxes[cfg_idx].config_register);
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uint32_t reg = *gpio_cfg_reg;
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/* TODO: Default flags, work for i.MX 9352 */
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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/* Set ODE bit */
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reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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} else {
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reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT);
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}
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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/* i.MX93 has no pull enable bit */
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if (((flags & GPIO_PULL_UP) != 0)) {
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reg |= (0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
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reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT);
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} else {
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reg |= (0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT);
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reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT);
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}
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} else {
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/* Set pin to highz */
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reg &= ~((0x1 << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |
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(0x1 << MCUX_IMX_BIAS_PULL_UP_SHIFT));
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}
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memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg));
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/* cfg register will be set by pinctrl_configure_pins */
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pin_cfg.pin_ctrl_flags = reg;
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pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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RGPIO_WritePinOutput(base, pin, 1);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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RGPIO_WritePinOutput(base, pin, 0);
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}
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WRITE_BIT(base->PDDR, pin, flags & GPIO_OUTPUT);
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return 0;
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}
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static int mcux_rgpio_port_get_raw(const struct device *dev, uint32_t *value)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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*value = base->PDIR;
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return 0;
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}
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static int mcux_rgpio_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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base->PDOR = (base->PDOR & ~mask) | (mask & value);
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return 0;
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}
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static int mcux_rgpio_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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RGPIO_PortSet(base, mask);
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return 0;
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}
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static int mcux_rgpio_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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RGPIO_PortClear(base, mask);
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return 0;
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}
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static int mcux_rgpio_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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RGPIO_PortToggle(base, mask);
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return 0;
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}
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static int mcux_rgpio_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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unsigned int key;
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uint8_t irqs, irqc;
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irqs = 0; /* only irq0 is used for irq */
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if (mode == GPIO_INT_MODE_DISABLED) {
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irqc = kRGPIO_InterruptOrDMADisabled;
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} else if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_LOW)) {
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irqc = kRGPIO_InterruptFallingEdge;
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} else if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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irqc = kRGPIO_InterruptRisingEdge;
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} else if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_BOTH)) {
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irqc = kRGPIO_InterruptEitherEdge;
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} else if ((mode == GPIO_INT_MODE_LEVEL) &&
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(trig == GPIO_INT_TRIG_LOW)) {
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irqc = kRGPIO_InterruptLogicZero;
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} else if ((mode == GPIO_INT_MODE_LEVEL) &&
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(trig == GPIO_INT_TRIG_HIGH)) {
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irqc = kRGPIO_InterruptLogicOne;
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} else {
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return -EINVAL; /* should never end up here */
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}
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key = irq_lock();
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RGPIO_SetPinInterruptConfig(base, pin, irqs, irqc);
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irq_unlock(key);
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return 0;
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}
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static int mcux_rgpio_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct mcux_rgpio_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static void mcux_rgpio_port_isr(const struct device *dev)
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{
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RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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struct mcux_rgpio_data *data = dev->data;
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uint32_t int_flags;
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int_flags = base->ISFR[0]; /* Notice: only irq0 is used for now */
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base->ISFR[0] = int_flags;
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gpio_fire_callbacks(&data->callbacks, dev, int_flags);
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}
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static const struct gpio_driver_api mcux_rgpio_driver_api = {
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.pin_configure = mcux_rgpio_configure,
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.port_get_raw = mcux_rgpio_port_get_raw,
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.port_set_masked_raw = mcux_rgpio_port_set_masked_raw,
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.port_set_bits_raw = mcux_rgpio_port_set_bits_raw,
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.port_clear_bits_raw = mcux_rgpio_port_clear_bits_raw,
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.port_toggle_bits = mcux_rgpio_port_toggle_bits,
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.pin_interrupt_configure = mcux_rgpio_pin_interrupt_configure,
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.manage_callback = mcux_rgpio_manage_callback,
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};
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/* These macros will declare an array of pinctrl_soc_pinmux types */
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#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
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#define MCUX_RGPIO_PIN_DECLARE(n) \
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const struct pinctrl_soc_pinmux mcux_rgpio_pinmux_##n[] = { \
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DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \
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}; \
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const uint8_t mcux_rgpio_pin_gaps_##n[] = \
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DT_INST_PROP_OR(n, gpio_reserved_ranges, {});
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#define MCUX_RGPIO_PIN_INIT(n) \
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.pin_muxes = mcux_rgpio_pinmux_##n, \
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.pin_gaps = (const struct gpio_pin_gaps *)mcux_rgpio_pin_gaps_##n, \
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.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux), \
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.gap_count = (ARRAY_SIZE(mcux_rgpio_pin_gaps_##n) / 2)
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#define MCUX_RGPIO_IRQ_INIT(n, i) \
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do { \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, i, irq), \
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DT_INST_IRQ_BY_IDX(n, i, priority), \
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mcux_rgpio_port_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq)); \
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} while (false)
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#define MCUX_RGPIO_INIT(n) \
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MCUX_RGPIO_PIN_DECLARE(n) \
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static int mcux_rgpio_##n##_init(const struct device *dev); \
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\
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static const struct mcux_rgpio_config mcux_rgpio_##n##_config = {\
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
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MCUX_RGPIO_PIN_INIT(n) \
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}; \
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\
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static struct mcux_rgpio_data mcux_rgpio_##n##_data; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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mcux_rgpio_##n##_init, \
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NULL, \
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&mcux_rgpio_##n##_data, \
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&mcux_rgpio_##n##_config, \
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POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&mcux_rgpio_driver_api); \
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\
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static int mcux_rgpio_##n##_init(const struct device *dev) \
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{ \
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DEVICE_MMIO_NAMED_MAP(dev, reg_base, \
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K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \
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(MCUX_RGPIO_IRQ_INIT(n, 0);)) \
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\
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1), \
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(MCUX_RGPIO_IRQ_INIT(n, 1);)) \
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\
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return 0; \
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}
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DT_INST_FOREACH_STATUS_OKAY(MCUX_RGPIO_INIT)
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32
dts/bindings/gpio/nxp,imx-rgpio.yaml
Normal file
32
dts/bindings/gpio/nxp,imx-rgpio.yaml
Normal file
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@ -0,0 +1,32 @@
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# Copyright 2024, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: i.MX RGPIO node
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compatible: "nxp,imx-rgpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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rdc:
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type: int
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description: Set the RDC permission for this peripheral
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pinmux:
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type: phandles
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description: |
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IMX pin selection peripheral does not follow specific
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pattern for which GPIO port uses which pinmux. Use this property to specify
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pinctrl nodes to use for the gpio port when CONFIG_PINCTRL=y. Note that
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the order of the nodes matters. The first node for gpio1 will be used
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as the pinmux for gpio0, port 0.
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2022, NXP
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* Copyright (c) 2022-2023, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -19,7 +19,6 @@ extern "C" {
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#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT
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#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT
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#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT
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#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PE_SHIFT
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#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT
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#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT
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#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
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