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arch: guard more code with CONFIG_EXCEPTION_DEBUG

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It should be possible to disable exception debug, which is enabled by
default to reduce image size. Add missing guards now that the option is
cross architecture.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-12-12 09:57:11 -05:00 committed by Carles Cufí
parent a7e8391e31
commit e25f31ab78
6 changed files with 17 additions and 4 deletions
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5
arch/arm/core/fatal.c
View file

@ -17,6 +17,7 @@
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
#ifdef CONFIG_EXCEPTION_DEBUG
static void esf_dump(const z_arch_esf_t *esf)
{
LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x",
@ -63,13 +64,15 @@ static void esf_dump(const z_arch_esf_t *esf)
LOG_ERR("Faulting instruction address (r15/pc): 0x%08x",
esf->basic.pc);
}
#endif /* CONFIG_EXCEPTION_DEBUG */
void z_arm_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
#ifdef CONFIG_EXCEPTION_DEBUG
if (esf != NULL) {
esf_dump(esf);
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
}

3
arch/mips/core/fatal.c
View file

@ -12,6 +12,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
FUNC_NORETURN void z_mips_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
#ifdef CONFIG_EXCEPTION_DEBUG
if (esf != NULL) {
printk("$ 0 : (ze) %08lx(at) %08lx(v0) %08lx(v1)\n",
esf->at, esf->v0, esf->v1);
@ -33,7 +34,7 @@ FUNC_NORETURN void z_mips_fatal_error(unsigned int reason,
printk("Cause : %08lx\n", esf->cause);
printk("BadVA : %08lx\n", esf->badvaddr);
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
CODE_UNREACHABLE;
}

2
arch/nios2/core/fatal.c
View file

@ -14,6 +14,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
#if CONFIG_EXCEPTION_DEBUG
if (esf != NULL) {
/* Subtract 4 from EA since we added 4 earlier so that the
* faulting instruction isn't retried.
@ -33,6 +34,7 @@ FUNC_NORETURN void z_nios2_fatal_error(unsigned int reason,
esf->r13, esf->r14, esf->r15, esf->ra);
LOG_ERR("estatus: %08x", esf->estatus);
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
CODE_UNREACHABLE;

3
arch/riscv/core/fatal.c
View file

@ -31,6 +31,7 @@ static const struct z_exc_handle exceptions[] = {
FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
#ifdef CONFIG_EXCEPTION_DEBUG
if (esf != NULL) {
LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0);
LOG_ERR(" a1: " PR_REG " t1: " PR_REG, esf->a1, esf->t1);
@ -54,7 +55,7 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
LOG_ERR("mstatus: " PR_REG, esf->mstatus);
LOG_ERR("");
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
CODE_UNREACHABLE;
}

6
arch/sparc/core/fatal.c
View file

@ -93,7 +93,7 @@ struct savearea {
uint32_t in[8];
};
#if CONFIG_EXCEPTION_DEBUG
/*
* Exception trap type (tt) values according to The SPARC V8
* manual, Table 7-1.
@ -202,10 +202,12 @@ static void print_all(const z_arch_esf_t *esf)
print_backtrace(esf);
LOG_ERR("");
}
#endif /* CONFIG_EXCEPTION_DEBUG */
FUNC_NORETURN void z_sparc_fatal_error(unsigned int reason,
const z_arch_esf_t *esf)
{
#if CONFIG_EXCEPTION_DEBUG
if (esf != NULL) {
if (IS_ENABLED(CONFIG_EXTRA_EXCEPTION_INFO)) {
print_all(esf);
@ -213,6 +215,8 @@ FUNC_NORETURN void z_sparc_fatal_error(unsigned int reason,
print_special_registers(esf);
}
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
CODE_UNREACHABLE;
}

2
arch/xtensa/core/fatal.c
View file

@ -86,6 +86,7 @@ char *xtensa_exccause(unsigned int cause_code)
void xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
{
#ifdef CONFIG_EXCEPTION_DEBUG
if (esf) {
/* Don't want to get elbowed by xtensa_switch
* in between printing registers and dumping them;
@ -103,6 +104,7 @@ void xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
#endif
arch_irq_unlock(key);
}
#endif /* CONFIG_EXCEPTION_DEBUG */
z_fatal_error(reason, esf);
}