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drivers: clock_control: Add PLL fracn for STM32U5

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Based on RM0456, each PLL in the STM32U5 has the
capability to work either in integer or fractional mode.
In this update, the fractional mode can be enabled
by setting the fracn value in the device tree.

Signed-off-by: Jatty Andriean <jandriea@outlook.com>
This commit is contained in:
Jatty Andriean 2023-09-19 03:25:34 +00:00 committed by Carles Cufí
parent 68292b0310
commit e364a095a6
3 changed files with 24 additions and 0 deletions
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12
drivers/clock_control/clock_stm32_ll_u5.c
View file

@ -519,6 +519,10 @@ static int set_up_plls(void)
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
LL_RCC_PLL1FRACN_Disable();
if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
LL_RCC_PLL1FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
@ -569,6 +573,10 @@ static int set_up_plls(void)
LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
LL_RCC_PLL2FRACN_Disable();
if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {
LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE);
LL_RCC_PLL2FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
@ -617,6 +625,10 @@ static int set_up_plls(void)
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
LL_RCC_PLL3FRACN_Disable();
if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {
LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE);
LL_RCC_PLL3FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);

6
dts/bindings/clock/st,stm32u5-pll-clock.yaml
View file

@ -71,3 +71,9 @@ properties:
On PLL1, only division by 1 and even division values are allowed.
No restrictions for PLL2 and PLL3
Valid range: 1 - 128
fracn:
type: int
description: |
PLLx FRACN value
Valid range: 0 - 8191

6
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -143,6 +143,8 @@
#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
@ -172,6 +174,8 @@
#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
@ -185,6 +189,8 @@
#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)