soc: st: add PM support for STM32H5

Single STOP mode level supported on STM32H5

Signed-off-by: Adam Berlinger <adam.berlinger@st.com>

dts/arm/st/h5/stm32h5.dtsi

@@ -30,6 +30,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m33";
 			reg = <0>;
+			cpu-power-states = <&stop>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -116,6 +117,15 @@
 			};
 		};
 
+		power-states {
+			stop: state0 {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+				substate-id = <1>;
+				min-residency-us = <20>;
+			};
+		};
+
 		rcc: rcc@44020c00 {
 			compatible = "st,stm32u5-rcc";
 			clocks-controller;

soc/st/stm32/stm32h5x/CMakeLists.txt

@@ -5,6 +5,10 @@ zephyr_sources(
   soc.c
   )
 
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+  )
+
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32h5x/Kconfig

@@ -14,3 +14,4 @@ config SOC_SERIES_STM32H5X
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
 	select HAS_SWO
+	select HAS_PM

soc/st/stm32/stm32h5x/power.c

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <soc.h>
+#include <zephyr/init.h>
+
+#include <stm32h5xx_ll_cortex.h>
+#include <stm32h5xx_ll_pwr.h>
+#include <clock_control/clock_stm32_ll_common.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Invoke Low Power/System Off specific Tasks */
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	if (state != PM_STATE_SUSPEND_TO_IDLE) {
+		LOG_DBG("Unsupported power state %u", state);
+		return;
+	}
+
+	switch (substate_id) {
+	case 1: /* this corresponds to the STOP mode: */
+		/* enter STOP mode */
+		LL_PWR_SetPowerMode(LL_PWR_STOP_MODE);
+		LL_LPM_EnableDeepSleep();
+		/* enter SLEEP mode : WFE or WFI */
+		k_cpu_idle();
+		break;
+	default:
+		LOG_DBG("Unsupported power state substate-id %u",
+			substate_id);
+		break;
+	}
+}
+
+/* Handle SOC specific activity after Low Power Mode Exit */
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	if (state != PM_STATE_SUSPEND_TO_IDLE) {
+		LOG_DBG("Unsupported power substate %u", state);
+	} else {
+		switch (substate_id) {
+		case 1:	/* STOP */
+			LL_LPM_DisableSleepOnExit();
+			/* Clear SLEEPDEEP bit */
+			LL_LPM_EnableSleep();
+			break;
+		default:
+			LOG_DBG("Unsupported power substate-id %u",
+				substate_id);
+			break;
+		}
+		/* need to restore the clock */
+		stm32_clock_control_init(NULL);
+	}
+
+	/*
+	 * System is now in active mode.
+	 * Reenable interrupts which were disabled
+	 * when OS started idling code.
+	 */
+	irq_unlock(0);
+}
+
+/* Initialize STM32 Power */
+static int stm32_power_init(void)
+{
+	return 0;
+}
+
+SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);