patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

soc: nxp: ke1xf: set ip clock in dts

Browse source 
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen 2019-07-28 23:48:23 +02:00 committed by Maureen Helm
parent c433a2ba33
commit e4f191aaf6
4 changed files with 71 additions and 49 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
dts/arm/nxp/nxp_ke1xf.dtsi
View file

@ -5,6 +5,7 @@
*/ */
#include <arm/armv7-m.dtsi> #include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_pcc.h>
#include <dt-bindings/clock/kinetis_scg.h> #include <dt-bindings/clock/kinetis_scg.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h> #include <dt-bindings/i2c/i2c.h>
@ -86,7 +87,7 @@
compatible = "nxp,kinetis-pcc"; compatible = "nxp,kinetis-pcc";
reg = <0x40065000 0x1000>; reg = <0x40065000 0x1000>;
label = "PCC"; label = "PCC";
#clock-cells = <1>; #clock-cells = <2>;
}; };
rtc0: rtc@4003d000 { rtc0: rtc@4003d000 {
@ -125,7 +126,7 @@
reg = <0x4006a000 0x1000>; reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>; interrupts = <31 0>, <32 0>;
interrupt-names = "transmit", "receive"; interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1a8>; clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "UART_0"; label = "UART_0";
status = "disabled"; status = "disabled";
}; };
@ -135,7 +136,7 @@
reg = <0x4006b000 0x1000>; reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>; interrupts = <33 0>, <34 0>;
interrupt-names = "transmit", "receive"; interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1ac>; clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "UART_1"; label = "UART_1";
status = "disabled"; status = "disabled";
}; };
@ -145,7 +146,7 @@
reg = <0x4006c000 0x1000>; reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>; interrupts = <35 0>, <36 0>;
interrupt-names = "transmit", "receive"; interrupt-names = "transmit", "receive";
clocks = <&pcc 0x1b0>; clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "UART_2"; label = "UART_2";
status = "disabled"; status = "disabled";
}; };
@ -157,7 +158,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x40066000 0x1000>; reg = <0x40066000 0x1000>;
interrupts = <24 0>; interrupts = <24 0>;
clocks = <&pcc 0x198>; clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "I2C_0"; label = "I2C_0";
status = "disabled"; status = "disabled";
}; };
@ -169,7 +170,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x40067000 0x1000>; reg = <0x40067000 0x1000>;
interrupts = <25 0>; interrupts = <25 0>;
clocks = <&pcc 0x19c>; clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "I2C_1"; label = "I2C_1";
status = "disabled"; status = "disabled";
}; };
@ -178,7 +179,7 @@
compatible = "nxp,imx-lpspi"; compatible = "nxp,imx-lpspi";
reg = <0x4002c000 0x1000>; reg = <0x4002c000 0x1000>;
interrupts = <26 0>; interrupts = <26 0>;
clocks = <&pcc 0xb0>; clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "SPI_0"; label = "SPI_0";
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
@ -189,7 +190,7 @@
compatible = "nxp,imx-lpspi"; compatible = "nxp,imx-lpspi";
reg = <0x4002d000 0x1000>; reg = <0x4002d000 0x1000>;
interrupts = <27 0>; interrupts = <27 0>;
clocks = <&pcc 0xb4>; clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "SPI_1"; label = "SPI_1";
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
@ -235,31 +236,31 @@
pinmux_a: pinmux@40049000 { pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0x1000>; reg = <0x40049000 0x1000>;
clocks = <&pcc 0x124>; clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
pinmux_b: pinmux@4004a000 { pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0x1000>; reg = <0x4004a000 0x1000>;
clocks = <&pcc 0x128>; clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
pinmux_c: pinmux@4004b000 { pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0x1000>; reg = <0x4004b000 0x1000>;
clocks = <&pcc 0x12c>; clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
pinmux_d: pinmux@4004c000 { pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0x1000>; reg = <0x4004c000 0x1000>;
clocks = <&pcc 0x130>; clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
pinmux_e: pinmux@4004d000 { pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux"; compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0x1000>; reg = <0x4004d000 0x1000>;
clocks = <&pcc 0x134>; clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>;
}; };
gpioa: gpio@400ff000 { gpioa: gpio@400ff000 {
@ -311,7 +312,7 @@
compatible = "nxp,kinetis-adc12"; compatible = "nxp,kinetis-adc12";
reg = <0x4003b000 0x1000>; reg = <0x4003b000 0x1000>;
interrupts = <39 0>; interrupts = <39 0>;
clocks = <&pcc 0xec>; clocks = <&pcc 0xec KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "ADC_0"; label = "ADC_0";
clk-source = <0>; clk-source = <0>;
clk-divider = <1>; clk-divider = <1>;
@ -323,7 +324,7 @@
compatible = "nxp,kinetis-adc12"; compatible = "nxp,kinetis-adc12";
reg = <0x40027000 0x1000>; reg = <0x40027000 0x1000>;
interrupts = <73 0>; interrupts = <73 0>;
clocks = <&pcc 0x9c>; clocks = <&pcc 0x9c KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "ADC_1"; label = "ADC_1";
clk-source = <0>; clk-source = <0>;
clk-divider = <1>; clk-divider = <1>;
@ -335,7 +336,7 @@
compatible = "nxp,kinetis-adc12"; compatible = "nxp,kinetis-adc12";
reg = <0x4003c000 0x1000>; reg = <0x4003c000 0x1000>;
interrupts = <74 0>; interrupts = <74 0>;
clocks = <&pcc 0xf0>; clocks = <&pcc 0xf0 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "ADC_2"; label = "ADC_2";
clk-source = <0>; clk-source = <0>;
clk-divider = <1>; clk-divider = <1>;
@ -347,7 +348,7 @@
compatible = "nxp,kinetis-ftm"; compatible = "nxp,kinetis-ftm";
reg = <0x40038000 0x1000>; reg = <0x40038000 0x1000>;
interrupts = <42 0>; interrupts = <42 0>;
clocks = <&pcc 0xe0>; clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "FTM_0"; label = "FTM_0";
#pwm-cells = <2>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
@ -357,7 +358,7 @@
compatible = "nxp,kinetis-ftm"; compatible = "nxp,kinetis-ftm";
reg = <0x40039000 0x1000>; reg = <0x40039000 0x1000>;
interrupts = <43 0>; interrupts = <43 0>;
clocks = <&pcc 0xe4>; clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "FTM_1"; label = "FTM_1";
#pwm-cells = <2>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
@ -367,7 +368,7 @@
compatible = "nxp,kinetis-ftm"; compatible = "nxp,kinetis-ftm";
reg = <0x4003a000 0x1000>; reg = <0x4003a000 0x1000>;
interrupts = <44 0>; interrupts = <44 0>;
clocks = <&pcc 0xe8>; clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "FTM_2"; label = "FTM_2";
#pwm-cells = <2>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
@ -377,7 +378,7 @@
compatible = "nxp,kinetis-ftm"; compatible = "nxp,kinetis-ftm";
reg = <0x40026000 0x1000>; reg = <0x40026000 0x1000>;
interrupts = <71 0>; interrupts = <71 0>;
clocks = <&pcc 0x98>; clocks = <&pcc 0x98 KINETIS_PCC_SRC_FIRC_ASYNC>;
label = "FTM_3"; label = "FTM_3";
#pwm-cells = <2>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";

3
dts/bindings/arm/nxp,kinetis-pcc.yaml
View file

@ -18,7 +18,8 @@ properties:
required: true required: true
"#clock-cells": "#clock-cells":
const: 1 const: 2
clock-cells: clock-cells:
- name - name
- ip-source

17
include/dt-bindings/clock/kinetis_pcc.h Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
/* NXP Kinetis Peripheral Clock Controller IP sources */
#define KINETIS_PCC_SRC_NONE_OR_EXT 0 /* Clock off or external clock is used */
#define KINETIS_PCC_SRC_SOSC_ASYNC 1 /* System Oscillator async clock */
#define KINETIS_PCC_SRC_SIRC_ASYNC 2 /* Slow IRC async clock */
#define KINETIS_PCC_SRC_FIRC_ASYNC 3 /* Fast IRC async clock */
#define KINETIS_PCC_SRC_SPLL_ASYNC 6 /* System PLL async clock */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_ */

59
soc/arm/nxp_kinetis/ke1xf/soc.c
View file

@ -163,47 +163,50 @@ static ALWAYS_INLINE void clk_init(void)
CLOCK_GetCurSysClkConfig(&current); CLOCK_GetCurSysClkConfig(&current);
} while (current.src != scg_sys_clk_config.src); } while (current.src != scg_sys_clk_config.src);
#ifdef CONFIG_UART_MCUX_LPUART_0 #ifdef DT_NXP_KINETIS_LPUART_UART_0_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpuart0,
DT_NXP_KINETIS_LPUART_UART_0_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_UART_MCUX_LPUART_1 #ifdef DT_NXP_KINETIS_LPUART_UART_1_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpuart1,
DT_NXP_KINETIS_LPUART_UART_1_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_UART_MCUX_LPUART_2 #ifdef DT_NXP_KINETIS_LPUART_UART_2_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpuart2, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpuart2,
DT_NXP_KINETIS_LPUART_UART_2_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_I2C_0 #ifdef DT_NXP_IMX_LPI2C_I2C_0_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpi2c0, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpi2c0, DT_NXP_IMX_LPI2C_I2C_0_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_I2C_1 #ifdef DT_NXP_IMX_LPI2C_I2C_1_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpi2c1, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpi2c1, DT_NXP_IMX_LPI2C_I2C_1_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_SPI_0 #ifdef DT_NXP_IMX_LPSPI_SPI_0_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpspi0, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpspi0, DT_NXP_IMX_LPSPI_SPI_0_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_SPI_1 #ifdef DT_NXP_IMX_LPSPI_SPI_1_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Lpspi1, DT_NXP_IMX_LPSPI_SPI_1_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_ADC_0 #ifdef DT_NXP_KINETIS_ADC12_ADC_0_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Adc0, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Adc0, DT_NXP_KINETIS_ADC12_ADC_0_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_ADC_1 #ifdef DT_NXP_KINETIS_ADC12_ADC_1_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Adc1, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Adc1, DT_NXP_KINETIS_ADC12_ADC_1_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_ADC_2 #ifdef DT_NXP_KINETIS_ADC12_ADC_2_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Adc2, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Adc2, DT_NXP_KINETIS_ADC12_ADC_2_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_PWM_0 #ifdef DT_NXP_KINETIS_FTM_FTM_0_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Ftm0, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Ftm0, DT_NXP_KINETIS_FTM_FTM_0_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_PWM_1 #ifdef DT_NXP_KINETIS_FTM_FTM_1_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Ftm1, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Ftm1, DT_NXP_KINETIS_FTM_FTM_1_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_PWM_2 #ifdef DT_NXP_KINETIS_FTM_FTM_2_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Ftm2, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Ftm2, DT_NXP_KINETIS_FTM_FTM_2_CLOCK_IP_SOURCE);
#endif #endif
#ifdef CONFIG_PWM_3 #ifdef DT_NXP_KINETIS_FTM_FTM_3_CLOCK_IP_SOURCE
CLOCK_SetIpSrc(kCLOCK_Ftm3, kCLOCK_IpSrcFircAsync); CLOCK_SetIpSrc(kCLOCK_Ftm3, DT_NXP_KINETIS_FTM_FTM_3_CLOCK_IP_SOURCE);
#endif #endif
} }