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dts: intel_s1000: Exclude sram space dedicated for mcubootloader

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The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
This commit is contained in:
Rajavardhan Gundi 2018-12-14 16:55:43 +05:30 committed by Anas Nashif
parent 18b64833d5
commit e584b05215
3 changed files with 26 additions and 14 deletions
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2
Kconfig.zephyr
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@ -332,7 +332,7 @@ config BOOTLOADER_SRAM_SIZE
int "SRAM reserved for bootloader"
default 16
depends on !XIP || IS_BOOTLOADER
depends on ARM
depends on ARM || XTENSA
help
This option specifies the amount of SRAM (measure in kB) reserved for
a bootloader image, when either:

2
boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
View file

@ -18,6 +18,8 @@ CONFIG_3RD_LEVEL_INTERRUPTS=y
CONFIG_CAVS_ICTL=y
CONFIG_DW_ICTL=y
CONFIG_BOOTLOADER_SRAM_SIZE=192
CONFIG_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_DEVICE_VID=0x8087

36
soc/xtensa/intel_s1000/memory.h
View file

@ -6,30 +6,40 @@
#ifndef __INC_MEMORY_H
#define __INC_MEMORY_H
#include <autoconf.h>
/* L2 HP SRAM */
#define L2_VECTOR_SIZE 0x1000
#ifdef CONFIG_BOOTLOADER_MCUBOOT
#define SRAM_BASE (DT_L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define SRAM_SIZE (DT_L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#else
#define SRAM_BASE (DT_L2_SRAM_BASE)
#define SRAM_SIZE (DT_L2_SRAM_SIZE)
#endif
/* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM DT_L2_SRAM_BASE
#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE
#define MEM_RESET_TEXT_SIZE 0x268
#define MEM_RESET_LIT_SIZE 0x8
/* This is the base address of all the vectors defined in SRAM */
#define XCHAL_VECBASE_RESET_PADDR_SRAM (DT_L2_SRAM_BASE + 0x400)
#define XCHAL_VECBASE_RESET_PADDR_SRAM (SRAM_BASE + 0x400)
#define MEM_VECBASE_LIT_SIZE 0x178
/* The addresses of the vectors in SRAM.
* Only the memerror vector continues to point to its ROM address.
*/
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x580)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x5C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x600)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x640)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x680)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x6C0)
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x700)
#define XCHAL_USER_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x740)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x7C0)
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (SRAM_BASE + 0x580)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (SRAM_BASE + 0x5C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (SRAM_BASE + 0x600)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (SRAM_BASE + 0x640)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (SRAM_BASE + 0x680)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (SRAM_BASE + 0x6C0)
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (SRAM_BASE + 0x700)
#define XCHAL_USER_VECTOR_PADDR_SRAM (SRAM_BASE + 0x740)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (SRAM_BASE + 0x7C0)
/* Vector and literal sizes */
#define MEM_VECT_LIT_SIZE 0x8
@ -46,8 +56,8 @@
/* text and data share the same L2 HP SRAM on Intel S1000.
* So, they lie next to each other.
*/
#define RAM_BASE (DT_L2_SRAM_BASE + L2_VECTOR_SIZE)
#define RAM_SIZE (DT_L2_SRAM_SIZE - L2_VECTOR_SIZE)
#define RAM_BASE (SRAM_BASE + L2_VECTOR_SIZE)
#define RAM_SIZE (SRAM_SIZE - L2_VECTOR_SIZE)
/* Location for the intList section which is later used to construct the
* Interrupt Descriptor Table (IDT). This is a bogus address as this