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drivers: serial: psoc6: Rework to support pinctrl

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The current serial driver uses hard code configuration.  Rework driver
to use pinctrl and enable full configuration from device tree.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
This commit is contained in:
Gerson Fernando Budke 2020-09-25 18:24:07 -03:00 committed by Kumar Gala
parent 66b6f07ea3
commit e6cba8d9c8
7 changed files with 151 additions and 87 deletions
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8
boards/arm/cy8ckit_062_ble/Kconfig.defconfig
View file

@ -11,13 +11,5 @@ config BOARD
default "cy8ckit_062_ble_m0" if BOARD_CY8CKIT_062_BLE_M0
default "cy8ckit_062_ble_m4" if BOARD_CY8CKIT_062_BLE_M4
config UART_PSOC6_UART_5
default y
depends on UART_PSOC6
config UART_PSOC6_UART_6
default y
depends on UART_PSOC6
endif # BOARD_CY8CKIT_062_BLE_M0 || \
# BOARD_CY8CKIT_062_BLE_M4

8
boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig
View file

@ -10,13 +10,5 @@ config BOARD
default "cy8ckit_062_wifi_bt_m0" if BOARD_CY8CKIT_062_WIFI_BT_M0
default "cy8ckit_062_wifi_bt_m4" if BOARD_CY8CKIT_062_WIFI_BT_M4
config UART_PSOC6_UART_5
default y
depends on UART_PSOC6
config UART_PSOC6_UART_6
default y
depends on UART_PSOC6
endif # BOARD_CY8CKIT_062_WIFI_BT_M0 || \
# BOARD_CY8CKIT_062_WIFI_BT_M4

23
drivers/serial/Kconfig.psoc6
View file

@ -1,23 +1,12 @@
# Cypress UART configuration
# Cypress SCB[UART] configuration
# Copyright (c) 2018 Cypress
# Copyright (c) 2020 ATL Electronics
# SPDX-License-Identifier: Apache-2.0
menuconfig UART_PSOC6
bool "PSoC6 MCU serial driver"
select SERIAL_HAS_DRIVER
config UART_PSOC6
bool "PSoC-6 MCU SCB serial driver"
depends on SOC_FAMILY_PSOC6
select SERIAL_HAS_DRIVER
help
This option enables the UART driver for PSoC6 family of processors.
config UART_PSOC6_UART_5
bool "Enable PSOC6 SCB6 as UART_5 on Port 5"
depends on UART_PSOC6
help
Enable support for UART_5 on port 5 in the driver.
config UART_PSOC6_UART_6
bool "Enable PSOC6 SCB6 as UART_6 on Port 12"
depends on UART_PSOC6
help
Enable support for UART_6 on port 12 in the driver.
This option enables the SCB[UART] driver for PSoC-6 SoC family.

71
drivers/serial/uart_psoc6.c
View file

@ -3,6 +3,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT cypress_psoc6_uart
/** @file
* @brief UART driver for Cypress PSoC6 MCU family.
*
@ -19,7 +21,6 @@
#include "cy_syslib.h"
#include "cy_sysclk.h"
#include "cy_gpio.h"
#include "cy_scb_uart.h"
/* UART desired baud rate is 115200 bps (Standard mode).
@ -44,12 +45,9 @@
struct cypress_psoc6_config {
CySCB_Type *base;
GPIO_PRT_Type *port;
uint32_t rx_num;
uint32_t tx_num;
en_hsiom_sel_t rx_val;
en_hsiom_sel_t tx_val;
en_clk_dst_t scb_clock;
uint32_t periph_id;
uint32_t num_pins;
struct soc_gpio_pin pins[];
};
/* Populate configuration structure */
@ -96,17 +94,10 @@ static int uart_psoc6_init(const struct device *dev)
{
const struct cypress_psoc6_config *config = dev->config;
/* Connect SCB5 UART function to pins */
Cy_GPIO_SetHSIOM(config->port, config->rx_num, config->rx_val);
Cy_GPIO_SetHSIOM(config->port, config->tx_num, config->tx_val);
/* Configure pins for UART operation */
Cy_GPIO_SetDrivemode(config->port, config->rx_num, CY_GPIO_DM_HIGHZ);
Cy_GPIO_SetDrivemode(config->port, config->tx_num,
CY_GPIO_DM_STRONG_IN_OFF);
soc_gpio_list_configure(config->pins, config->num_pins);
/* Connect assigned divider to be a clock source for UART */
Cy_SysClk_PeriphAssignDivider(config->scb_clock,
Cy_SysClk_PeriphAssignDivider(config->periph_id,
UART_PSOC6_UART_CLK_DIV_TYPE,
UART_PSOC6_UART_CLK_DIV_NUMBER);
@ -147,38 +138,18 @@ static const struct uart_driver_api uart_psoc6_driver_api = {
.poll_out = uart_psoc6_poll_out,
};
#ifdef CONFIG_UART_PSOC6_UART_5
static const struct cypress_psoc6_config cypress_psoc6_uart5_config = {
.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart5)),
.port = P5_0_PORT,
.rx_num = P5_0_NUM,
.tx_num = P5_1_NUM,
.rx_val = P5_0_SCB5_UART_RX,
.tx_val = P5_1_SCB5_UART_TX,
.scb_clock = PCLK_SCB5_CLOCK,
};
#define CY_PSOC6_UART_INIT(n) \
static const struct cypress_psoc6_config cy_psoc6_uart##n##_config = { \
.base = (CySCB_Type *)DT_INST_REG_ADDR(n), \
.periph_id = DT_INST_PROP(n, peripheral_id), \
\
.num_pins = CY_PSOC6_DT_INST_NUM_PINS(n), \
.pins = CY_PSOC6_DT_INST_PINS(n), \
}; \
DEVICE_DT_INST_DEFINE(n, &uart_psoc6_init, device_pm_control_nop, \
NULL, \
&cy_psoc6_uart##n##_config, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&uart_psoc6_driver_api);
DEVICE_DT_DEFINE(DT_NODELABEL(uart5),
uart_psoc6_init, device_pm_control_nop, NULL,
&cypress_psoc6_uart5_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
(void *)&uart_psoc6_driver_api);
#endif /* CONFIG_UART_PSOC6_UART_5 */
#ifdef CONFIG_UART_PSOC6_UART_6
static const struct cypress_psoc6_config cypress_psoc6_uart6_config = {
.base = (CySCB_Type *)DT_REG_ADDR(DT_NODELABEL(uart6)),
.port = P12_0_PORT,
.rx_num = P12_0_NUM,
.tx_num = P12_1_NUM,
.rx_val = P12_0_SCB6_UART_RX,
.tx_val = P12_1_SCB6_UART_TX,
.scb_clock = PCLK_SCB6_CLOCK,
};
DEVICE_DT_DEFINE(DT_NODELABEL(uart6),
uart_psoc6_init, device_pm_control_nop, NULL,
&cypress_psoc6_uart6_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
(void *)&uart_psoc6_driver_api);
#endif /* CONFIG_UART_PSOC6_UART_6 */
DT_INST_FOREACH_STATUS_OKAY(CY_PSOC6_UART_INIT)

44
dts/arm/cypress/psoc6-pinctrl.dtsi
View file

@ -10,10 +10,54 @@
soc {
pinctrl@40310000 {
/* instance, signal, port, pin, hsiom [, flag1, ... ] */
DT_CYPRESS_HSIOM(uart0, rx, 0, 2, act_6, input-enable);
DT_CYPRESS_HSIOM(uart0, tx, 0, 3, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart0, rts, 0, 4, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart0, cts, 0, 5, act_6, input-enable);
DT_CYPRESS_HSIOM(uart1, rx, 10, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart1, tx, 10, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart1, rts, 10, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart1, cts, 10, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart2, rx, 9, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart2, tx, 9, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart2, rts, 9, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart2, cts, 9, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart3, rx, 6, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart3, tx, 6, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart3, rts, 6, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart3, cts, 6, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart4, rx, 7, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart4, tx, 7, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart4, rts, 7, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart4, cts, 7, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart4, rx, 8, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart4, tx, 8, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart4, rts, 8, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart4, cts, 8, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart5, rx, 5, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart5, tx, 5, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart5, rts, 5, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart5, cts, 5, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart5, rx, 11, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart5, tx, 11, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart5, rts, 11, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart5, cts, 11, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, rx, 6, 4, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, tx, 6, 5, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, rts, 6, 6, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, cts, 6, 7, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, rx, 12, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, tx, 12, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, rts, 12, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, cts, 12, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, rx, 13, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart6, tx, 13, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, rts, 13, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart6, cts, 13, 3, act_6, input-enable);
DT_CYPRESS_HSIOM(uart7, rx, 1, 0, act_6, input-enable);
DT_CYPRESS_HSIOM(uart7, tx, 1, 1, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart7, rts, 1, 2, act_6, drive-push-pull);
DT_CYPRESS_HSIOM(uart7, cts, 1, 3, act_6, input-enable);
};
};
};

63
dts/arm/cypress/psoc6.dtsi
View file

@ -248,21 +248,78 @@
};
};
uart0: uart@40610000 {
compatible = "cypress,psoc6-uart";
reg = <0x40610000 0x10000>;
interrupts = <41 7>;
peripheral-id = <0>;
status = "disabled";
label = "uart_0";
};
uart1: uart@40620000 {
compatible = "cypress,psoc6-uart";
reg = <0x40620000 0x10000>;
interrupts = <42 7>;
peripheral-id = <1>;
status = "disabled";
label = "uart_1";
};
uart2: uart@40630000 {
compatible = "cypress,psoc6-uart";
reg = <0x40630000 0x10000>;
interrupts = <43 7>;
peripheral-id = <2>;
status = "disabled";
label = "uart_2";
};
uart3: uart@40640000 {
compatible = "cypress,psoc6-uart";
reg = <0x40640000 0x10000>;
interrupts = <44 7>;
peripheral-id = <3>;
status = "disabled";
label = "uart_3";
};
uart4: uart@40650000 {
compatible = "cypress,psoc6-uart";
reg = <0x40650000 0x10000>;
interrupts = <45 7>;
peripheral-id = <4>;
status = "disabled";
label = "uart_4";
};
uart5: uart@40660000 {
compatible = "cypress,psoc6-uart";
reg = <0x40660000 0x10000>;
interrupts = <2 1>;
interrupts = <46 7>;
peripheral-id = <5>;
status = "disabled";
label = "uart_5";
};
uart6: uart@40670000 {
compatible = "cypress,psoc6-uart";
reg = <0x40670000 0x10000>;
interrupts = <2 1>;
interrupts = <47 7>;
peripheral-id = <6>;
status = "disabled";
label = "uart_6";
};
uart7: uart@40680000 {
compatible = "cypress,psoc6-uart";
reg = <0x40680000 0x10000>;
interrupts = <48 7>;
peripheral-id = <7>;
status = "disabled";
label = "uart_7";
};
uart8: uart@40690000 {
compatible = "cypress,psoc6-uart";
reg = <0x40690000 0x10000>;
interrupts = <18 7>;
peripheral-id = <8>;
status = "disabled";
label = "uart_8";
};
uid: device_uid@16000600 {
compatible = "cypress,psoc6-uid";

21
dts/bindings/serial/cypress,psoc6-uart.yaml
View file

@ -1,7 +1,8 @@
# Copyright (c) 2018, Cypress
# Copyright (c) 2020, ATL Electronics
# SPDX-License-Identifier: Apache-2.0
description: Cypress UART
description: Cypress SCB[UART]
compatible: "cypress,psoc6-uart"
@ -13,3 +14,21 @@ properties:
interrupts:
required: true
peripheral-id:
type: int
description: peripheral ID
required: true
pinctrl-0:
type: phandles
description: |
Port pin configuration for RX & TX signals. We expect that the
phandles will reference pinctrl nodes. These nodes will have a
nodelabel that matches the Cypress SoC HAL defines and be of the
form p<port>_<pin>_<periph><inst>_<signal>.
For example the UART on PSoC-63 Pioneer Kit would be
pinctrl-0 = <&p5_0_uart5_rx &p5_1_uart5_tx>;
required: true