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interrupt_controller: cavs: add support in ISR for SMP

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The CAVS interrupt controller has different base addresses for
each CPU. When running under SMP, the driver needs to look at
the correct address for the CPU the ISR is running so interrupts
can be dispatched correctly. This adds a function to calculate
the correct base address. Note that each supported SoC may have
different offsets so per SoC config will need to added. Support
for intel_s1000 is added as an example.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2020-01-16 17:49:26 -08:00 committed by Anas Nashif
parent b4a7eed82e
commit e6d468ac22
1 changed files with 22 additions and 1 deletions
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23
drivers/interrupt_controller/intc_cavs.c
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@ -8,6 +8,27 @@
#include <irq_nextlevel.h>
#include "intc_cavs.h"
#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
#if defined(CONFIG_SOC_INTEL_S1000)
#define PER_CPU_OFFSET(x) (0x40 * x)
#else
#error "Must define PER_CPU_OFFSET(x) for SoC"
#endif
#else
#define PER_CPU_OFFSET(x) 0
#endif
static ALWAYS_INLINE
struct cavs_registers *get_base_address(struct cavs_ictl_runtime *context)
{
#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
return UINT_TO_POINTER(context->base_addr +
PER_CPU_OFFSET(arch_curr_cpu()->id));
#else
return UINT_TO_POINTER(context->base_addr);
#endif
}
static ALWAYS_INLINE void cavs_ictl_dispatch_child_isrs(u32_t intr_status,
u32_t isr_base_offset)
{
@ -31,7 +52,7 @@ static void cavs_ictl_isr(void *arg)
const struct cavs_ictl_config *config = port->config->config_info;
volatile struct cavs_registers * const regs =
(struct cavs_registers *)context->base_addr;
get_base_address(context);
cavs_ictl_dispatch_child_isrs(regs->status_il,
config->isr_table_offset);