drivers: display: Add support for LED matrix driven by nRF SoC GPIOs
Add a display driver and the corresponding devicetree binding for a LED matrix with rows and columns driven by nRF SoCs GPIOs. Such matrix can be found, for example, in the BBC micro:bit boards. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Carles Cufí
parent
ca0702283f
commit
e7f7e955b3
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@ -2,6 +2,7 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_DISPLAY_MCUX_ELCDIF display_mcux_elcdif.c)
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zephyr_library_sources_ifdef(CONFIG_DISPLAY_NRF_LED_MATRIX display_nrf_led_matrix.c)
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zephyr_library_sources_ifdef(CONFIG_DUMMY_DISPLAY display_dummy.c)
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zephyr_library_sources_ifdef(CONFIG_FRAMEBUF_DISPLAY display_framebuf.c)
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zephyr_library_sources_ifdef(CONFIG_GD7965 gd7965.c)
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@ -23,6 +23,7 @@ source "subsys/logging/Kconfig.template.log_config"
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source "drivers/display/Kconfig.grove"
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source "drivers/display/Kconfig.mcux_elcdif"
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source "drivers/display/Kconfig.microbit"
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source "drivers/display/Kconfig.nrf_led_matrix"
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source "drivers/display/Kconfig.ili9xxx"
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source "drivers/display/Kconfig.sdl"
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source "drivers/display/Kconfig.ssd1306"
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19
drivers/display/Kconfig.nrf_led_matrix
Normal file
19
drivers/display/Kconfig.nrf_led_matrix
Normal file
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@ -0,0 +1,19 @@
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# Copyright (c) 2021, Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config DISPLAY_NRF_LED_MATRIX
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bool "LED matrix driven by GPIOs"
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depends on SOC_FAMILY_NRF
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select NRFX_GPIOTE
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select NRFX_PPI if HAS_HW_NRF_PPI
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help
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Enable driver for a LED matrix with rows and columns driven by
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GPIOs. The matrix is refreshed pixel by pixel (only one LED is
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turned on in particular time slots) and each pixel can have one
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of 256 levels of brightness (0 means off completely).
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Assignment of GPIOs to rows and columns and the mapping of those
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to pixels are specified in properties of a "nordic,nrf-led-matrix"
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compatible node in devicetree.
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The driver uses one TIMER instance and, depending on what is set
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in devicetree, one PWM instance or one PPI channel and one GPIOTE
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channel.
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450
drivers/display/display_nrf_led_matrix.c
Normal file
450
drivers/display/display_nrf_led_matrix.c
Normal file
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@ -0,0 +1,450 @@
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/*
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* Copyright (c) 2021, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/display.h>
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#include <devicetree.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <hal/nrf_timer.h>
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#ifdef PWM_PRESENT
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#include <hal/nrf_pwm.h>
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#endif
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#include <nrfx_gpiote.h>
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#ifdef PPI_PRESENT
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#include <nrfx_ppi.h>
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#endif
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#define MATRIX_NODE DT_INST(0, nordic_nrf_led_matrix)
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#define TIMER_NODE DT_PHANDLE(MATRIX_NODE, timer)
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#define USE_PWM DT_NODE_HAS_PROP(MATRIX_NODE, pwm)
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#define ROW_COUNT DT_PROP_LEN(MATRIX_NODE, row_gpios)
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#define COL_COUNT DT_PROP_LEN(MATRIX_NODE, col_gpios)
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#define X_PIXELS DT_PROP(MATRIX_NODE, width)
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#define Y_PIXELS DT_PROP(MATRIX_NODE, height)
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#define PIXEL_COUNT DT_PROP_LEN(MATRIX_NODE, pixel_mapping)
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BUILD_ASSERT(PIXEL_COUNT == (X_PIXELS * Y_PIXELS),
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"Invalid length of pixel-mapping");
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#define PIXEL_MAPPING(idx) DT_PROP_BY_IDX(MATRIX_NODE, pixel_mapping, idx)
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#define CHECK_PIXEL(node_id, pha, idx) \
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BUILD_ASSERT((PIXEL_MAPPING(idx) >> 4) < ROW_COUNT, \
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"Invalid row index in pixel-mapping["#idx"]"); \
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BUILD_ASSERT((PIXEL_MAPPING(idx) & 0xF) < COL_COUNT, \
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"Invalid column index in pixel-mapping["#idx"]");
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DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping, CHECK_PIXEL)
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#define REFRESH_FREQUENCY DT_PROP(MATRIX_NODE, refresh_frequency)
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#define BASE_FREQUENCY 16000000
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#define TIMER_CLK_CONFIG NRF_TIMER_FREQ_16MHz
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#define PWM_CLK_CONFIG NRF_PWM_CLK_16MHz
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#define BRIGHTNESS_MAX 255
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#define QUANTUM (BASE_FREQUENCY / (REFRESH_FREQUENCY * PIXEL_COUNT * \
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BRIGHTNESS_MAX))
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#define PIXEL_PERIOD (BRIGHTNESS_MAX * QUANTUM)
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BUILD_ASSERT(PIXEL_PERIOD <= BIT_MASK(16));
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#if USE_PWM
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BUILD_ASSERT(PIXEL_PERIOD <= PWM_COUNTERTOP_COUNTERTOP_Msk);
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#endif
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#define ACTIVE_LOW_MASK 0x80
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#define PSEL_MASK 0x7F
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struct display_drv_config {
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NRF_TIMER_Type *timer;
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#if USE_PWM
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NRF_PWM_Type *pwm;
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#endif
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uint8_t rows[ROW_COUNT];
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uint8_t cols[COL_COUNT];
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uint8_t pixel_mapping[PIXEL_COUNT];
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};
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struct display_drv_data {
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#if USE_PWM
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uint16_t seq;
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#else
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uint8_t gpiote_ch;
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#endif
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uint8_t pixel_idx;
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uint8_t framebuf[PIXEL_COUNT];
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uint8_t brightness;
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bool blanking;
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};
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static void set_pin(uint8_t pin_info, bool active)
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{
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uint32_t value = active ? 1 : 0;
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if (pin_info & ACTIVE_LOW_MASK) {
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value = !value;
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}
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nrf_gpio_pin_write(pin_info & PSEL_MASK, value);
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}
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static int api_blanking_on(const struct device *dev)
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{
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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if (!dev_data->blanking) {
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_STOP);
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for (uint8_t i = 0; i < ROW_COUNT; ++i) {
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set_pin(dev_config->rows[i], false);
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}
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for (uint8_t i = 0; i < COL_COUNT; ++i) {
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set_pin(dev_config->cols[i], false);
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}
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dev_data->blanking = true;
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}
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return 0;
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}
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static int api_blanking_off(const struct device *dev)
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{
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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if (dev_data->blanking) {
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dev_data->pixel_idx = PIXEL_COUNT - 1;
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_CLEAR);
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
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dev_data->blanking = false;
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}
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return 0;
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}
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static void *api_get_framebuffer(const struct device *dev)
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{
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struct display_drv_data *dev_data = dev->data;
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return dev_data->framebuf;
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}
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static int api_set_brightness(const struct device *dev,
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const uint8_t brightness)
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{
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struct display_drv_data *dev_data = dev->data;
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uint8_t new_brightness = CLAMP(brightness, 1, BRIGHTNESS_MAX);
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int16_t delta = (int16_t)new_brightness - dev_data->brightness;
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dev_data->brightness = new_brightness;
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for (uint8_t i = 0; i < PIXEL_COUNT; ++i) {
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uint8_t old_val = dev_data->framebuf[i];
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if (old_val) {
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int16_t new_val = old_val + delta;
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dev_data->framebuf[i] =
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(uint8_t)CLAMP(new_val, 1, BRIGHTNESS_MAX);
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}
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}
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return 0;
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}
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static int api_set_contrast(const struct device *dev,
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const uint8_t contrast)
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{
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return -ENOTSUP;
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}
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static int api_set_pixel_format(const struct device *dev,
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const enum display_pixel_format format)
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{
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switch (format) {
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case PIXEL_FORMAT_MONO01:
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return 0;
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default:
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return -ENOTSUP;
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}
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}
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static int api_set_orientation(const struct device *dev,
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const enum display_orientation orientation)
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{
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switch (orientation) {
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case DISPLAY_ORIENTATION_NORMAL:
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return 0;
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default:
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return -ENOTSUP;
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}
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}
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static void api_get_capabilities(const struct device *dev,
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struct display_capabilities *caps)
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{
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caps->x_resolution = X_PIXELS;
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caps->y_resolution = Y_PIXELS;
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caps->supported_pixel_formats = PIXEL_FORMAT_MONO01;
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caps->screen_info = 0;
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caps->current_pixel_format = PIXEL_FORMAT_MONO01;
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caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
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}
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static inline void move_to_next_pixel(uint8_t *mask, uint8_t *data,
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const uint8_t **byte_buf)
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{
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*mask <<= 1;
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if (!*mask) {
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*mask = 0x01;
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*data = *(*byte_buf)++;
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}
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}
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static int api_write(const struct device *dev,
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const uint16_t x, const uint16_t y,
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const struct display_buffer_descriptor *desc,
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const void *buf)
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{
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struct display_drv_data *dev_data = dev->data;
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const uint8_t *byte_buf = buf;
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uint16_t end_x = x + desc->width;
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uint16_t end_y = y + desc->height;
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if (x >= X_PIXELS || end_x > X_PIXELS ||
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y >= Y_PIXELS || end_y > Y_PIXELS) {
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return -EINVAL;
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}
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if (desc->pitch < desc->width) {
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return -EINVAL;
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}
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uint16_t to_skip = desc->pitch - desc->width;
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uint8_t mask = 0;
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uint8_t data = 0;
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for (uint16_t py = y; py < end_y; ++py) {
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for (uint16_t px = x; px < end_x; ++px) {
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move_to_next_pixel(&mask, &data, &byte_buf);
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dev_data->framebuf[px + (py * X_PIXELS)] =
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(data & mask) ? dev_data->brightness : 0;
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}
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if (to_skip) {
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uint16_t cnt = to_skip;
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do {
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move_to_next_pixel(&mask, &data, &byte_buf);
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} while (--cnt);
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}
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}
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return 0;
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}
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static int api_read(const struct device *dev,
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const uint16_t x, const uint16_t y,
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const struct display_buffer_descriptor *desc,
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void *buf)
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{
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return -ENOTSUP;
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}
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const struct display_driver_api driver_api = {
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.blanking_on = api_blanking_on,
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.blanking_off = api_blanking_off,
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.write = api_write,
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.read = api_read,
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.get_framebuffer = api_get_framebuffer,
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.set_brightness = api_set_brightness,
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.set_contrast = api_set_contrast,
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.get_capabilities = api_get_capabilities,
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.set_pixel_format = api_set_pixel_format,
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.set_orientation = api_set_orientation,
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};
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static void timer_irq_handler(void *arg)
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{
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const struct device *dev = arg;
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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uint8_t prev_row_idx, pixel_mapping, row_pin_info, col_pin_info;
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uint16_t pulse;
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/* The timer is automagically stopped and cleared by shortcuts
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* on the same event (COMPARE0) that generates this interrupt.
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* But the event itself needs to be cleared here.
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*/
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nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
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/* Disable the row that contains the previously handled pixel. */
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prev_row_idx = dev_config->pixel_mapping[dev_data->pixel_idx] >> 4;
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set_pin(dev_config->rows[prev_row_idx], false);
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/* Disconnect that pixel column pin from the peripheral driving it. */
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#if USE_PWM
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nrf_pwm_disable(dev_config->pwm);
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#else
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch] = 0;
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#endif
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/* Switch to the next pixel. */
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++dev_data->pixel_idx;
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if (dev_data->pixel_idx >= PIXEL_COUNT) {
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dev_data->pixel_idx = 0;
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}
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pixel_mapping = dev_config->pixel_mapping[dev_data->pixel_idx];
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row_pin_info = dev_config->rows[pixel_mapping >> 4];
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col_pin_info = dev_config->cols[pixel_mapping & 0xF];
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/* Prepare the low pulse on the column pin for the current pixel. */
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pulse = dev_data->framebuf[dev_data->pixel_idx] * QUANTUM;
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#if USE_PWM
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dev_config->pwm->PSEL.OUT[0] = col_pin_info & PSEL_MASK;
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dev_data->seq = pulse
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| ((col_pin_info & ACTIVE_LOW_MASK) ? 0 : BIT(15));
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nrf_pwm_enable(dev_config->pwm);
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nrf_pwm_task_trigger(dev_config->pwm, NRF_PWM_TASK_SEQSTART0);
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#else
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uint32_t gpiote_cfg = GPIOTE_CONFIG_MODE_Task
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| ((col_pin_info & PSEL_MASK) << GPIOTE_CONFIG_PSEL_Pos);
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if (col_pin_info & ACTIVE_LOW_MASK) {
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gpiote_cfg |= (GPIOTE_CONFIG_POLARITY_LoToHi
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<< GPIOTE_CONFIG_POLARITY_Pos)
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/* If there should be no pulse at all for a given
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* pixel, its column GPIO needs to be configured
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* as initially inactive.
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*/
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| ((pulse == 0 ? GPIOTE_CONFIG_OUTINIT_High
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: GPIOTE_CONFIG_OUTINIT_Low)
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<< GPIOTE_CONFIG_OUTINIT_Pos);
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} else {
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gpiote_cfg |= (GPIOTE_CONFIG_POLARITY_HiToLo
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<< GPIOTE_CONFIG_POLARITY_Pos)
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| ((pulse == 0 ? GPIOTE_CONFIG_OUTINIT_Low
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: GPIOTE_CONFIG_OUTINIT_High)
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<< GPIOTE_CONFIG_OUTINIT_Pos);
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}
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nrf_timer_cc_set(dev_config->timer, 1, pulse);
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch] = gpiote_cfg;
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#endif
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/* Enable the row drive for the current pixel and restart the timer. */
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set_pin(row_pin_info, true);
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
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}
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static int instance_init(const struct device *dev)
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{
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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#if USE_PWM
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uint32_t out_psels[NRF_PWM_CHANNEL_COUNT] = {
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NRF_PWM_PIN_NOT_CONNECTED,
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NRF_PWM_PIN_NOT_CONNECTED,
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NRF_PWM_PIN_NOT_CONNECTED,
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NRF_PWM_PIN_NOT_CONNECTED,
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};
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nrf_pwm_sequence_t sequence = {
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.values.p_raw = &dev_data->seq,
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.length = 1,
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};
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nrf_pwm_pins_set(dev_config->pwm, out_psels);
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nrf_pwm_configure(dev_config->pwm,
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PWM_CLK_CONFIG, NRF_PWM_MODE_UP, PIXEL_PERIOD);
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nrf_pwm_decoder_set(dev_config->pwm,
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NRF_PWM_LOAD_COMMON, NRF_PWM_STEP_TRIGGERED);
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nrf_pwm_sequence_set(dev_config->pwm, 0, &sequence);
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nrf_pwm_loop_set(dev_config->pwm, 0);
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nrf_pwm_shorts_set(dev_config->pwm, NRF_PWM_SHORT_SEQEND0_STOP_MASK);
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#else
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nrfx_err_t err;
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nrf_ppi_channel_t ppi_ch;
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err = nrfx_ppi_channel_alloc(&ppi_ch);
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if (err != NRFX_SUCCESS) {
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return -ENOMEM;
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}
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err = nrfx_gpiote_channel_alloc(&dev_data->gpiote_ch);
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if (err != NRFX_SUCCESS) {
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nrfx_ppi_channel_free(ppi_ch);
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return -ENOMEM;
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}
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nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
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nrf_timer_event_address_get(dev_config->timer,
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nrf_timer_compare_event_get(1)),
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nrf_gpiote_event_address_get(NRF_GPIOTE,
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nrf_gpiote_out_task_get(dev_data->gpiote_ch)));
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nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
|
||||
#endif /* USE_PWM */
|
||||
|
||||
for (uint8_t i = 0; i < ROW_COUNT; ++i) {
|
||||
uint8_t row_pin_info = dev_config->rows[i];
|
||||
|
||||
set_pin(row_pin_info, false);
|
||||
nrf_gpio_cfg(row_pin_info & PSEL_MASK,
|
||||
NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < COL_COUNT; ++i) {
|
||||
uint8_t col_pin_info = dev_config->cols[i];
|
||||
|
||||
set_pin(col_pin_info, false);
|
||||
nrf_gpio_cfg(col_pin_info & PSEL_MASK,
|
||||
NRF_GPIO_PIN_DIR_OUTPUT,
|
||||
NRF_GPIO_PIN_INPUT_DISCONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
nrf_timer_bit_width_set(dev_config->timer, NRF_TIMER_BIT_WIDTH_16);
|
||||
nrf_timer_frequency_set(dev_config->timer, TIMER_CLK_CONFIG);
|
||||
nrf_timer_cc_set(dev_config->timer, 0, PIXEL_PERIOD);
|
||||
nrf_timer_shorts_set(dev_config->timer,
|
||||
NRF_TIMER_SHORT_COMPARE0_STOP_MASK |
|
||||
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
|
||||
nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
|
||||
nrf_timer_int_enable(dev_config->timer, NRF_TIMER_INT_COMPARE0_MASK);
|
||||
|
||||
IRQ_CONNECT(DT_IRQN(TIMER_NODE), DT_IRQ(TIMER_NODE, priority),
|
||||
timer_irq_handler, DEVICE_DT_GET(MATRIX_NODE), 0);
|
||||
irq_enable(DT_IRQN(TIMER_NODE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct display_drv_data instance_data = {
|
||||
.brightness = 0xFF,
|
||||
.blanking = true,
|
||||
};
|
||||
|
||||
#define GET_PIN_INFO(node_id, pha, idx) \
|
||||
(DT_GPIO_PIN_BY_IDX(node_id, pha, idx) | \
|
||||
(DT_PROP_BY_PHANDLE_IDX(node_id, pha, idx, port) << 5) | \
|
||||
((DT_GPIO_FLAGS_BY_IDX(node_id, pha, idx) & GPIO_ACTIVE_LOW) ? \
|
||||
ACTIVE_LOW_MASK : 0)),
|
||||
|
||||
static const struct display_drv_config instance_config = {
|
||||
.timer = (NRF_TIMER_Type *)DT_REG_ADDR(TIMER_NODE),
|
||||
#if USE_PWM
|
||||
.pwm = (NRF_PWM_Type *)DT_REG_ADDR(DT_PHANDLE(MATRIX_NODE, pwm)),
|
||||
#endif
|
||||
.rows = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios, GET_PIN_INFO) },
|
||||
.cols = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, col_gpios, GET_PIN_INFO) },
|
||||
.pixel_mapping = DT_PROP(MATRIX_NODE, pixel_mapping),
|
||||
};
|
||||
|
||||
DEVICE_DT_DEFINE(MATRIX_NODE,
|
||||
instance_init, NULL,
|
||||
&instance_data, &instance_config,
|
||||
POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &driver_api);
|
||||
65
dts/bindings/display/nordic,nrf-led-matrix.yaml
Normal file
65
dts/bindings/display/nordic,nrf-led-matrix.yaml
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
# Copyright (c) 2021, Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Generic LED matrix driven by nRF SoC GPIOs
|
||||
|
||||
compatible: "nordic,nrf-led-matrix"
|
||||
|
||||
include: display-controller.yaml
|
||||
|
||||
properties:
|
||||
row-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: |
|
||||
Array of GPIOs to be used as rows of the matrix.
|
||||
|
||||
col-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: |
|
||||
Array of GPIOs to be used as columns of the matrix.
|
||||
|
||||
pixel-mapping:
|
||||
type: uint8-array
|
||||
required: true
|
||||
description: |
|
||||
Array of bytes that specify which rows and columns of the matrix
|
||||
control its particular pixels, line by line. Each byte in this
|
||||
array corresponds to one pixel of the matrix and specifies the row
|
||||
index in the high nibble and the column index in the low nibble.
|
||||
|
||||
For example, the following snippet (from the bbc_microbit board DTS):
|
||||
|
||||
width = <5>;
|
||||
height = <5>;
|
||||
pixel-mapping = [00 13 01 14 02
|
||||
23 24 25 26 27
|
||||
...
|
||||
|
||||
specifies that:
|
||||
- pixel (0,0) is controlled by row 0 and column 0
|
||||
- pixel (1,0) is controlled by row 1 and column 3
|
||||
- pixel (0,1) is controlled by row 2 and column 3
|
||||
- pixel (1,1) is controlled by row 2 and column 4
|
||||
and so on.
|
||||
|
||||
refresh-frequency:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Frequency of refreshing the matrix, in Hz.
|
||||
|
||||
timer:
|
||||
type: phandle
|
||||
required: true
|
||||
description: |
|
||||
Reference to a TIMER instance for controlling refreshing of the matrix.
|
||||
|
||||
pwm:
|
||||
type: phandle
|
||||
required: false
|
||||
description: |
|
||||
Reference to a PWM instance for generating pulse signals on column
|
||||
GPIOs. If not provided, one PPI and one GPIOTE channel are allocated
|
||||
and used instead for generating those pulses.
|
||||
Loading…
Reference in a new issue