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arch: Add imx7d_m4 gpio definitions

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Adds all necessary gpio definitions and configurations for imx7d_m4 soc.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
This commit is contained in:
Diego Sueiro 2018-05-08 07:38:50 +01:00 committed by Maureen Helm
parent de7fc9dec9
commit e8e76ae433
5 changed files with 154 additions and 1 deletions
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10
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4
View file

@ -26,6 +26,16 @@ config CLOCK_CONTROL_IMX_CCM
endif # CLOCK_CONTROL
config GPIO
def_bool y
if GPIO
config GPIO_IMX
def_bool y
endif # GPIO
if SERIAL
config UART_IMX

1
arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.soc
View file

@ -12,6 +12,7 @@ depends on SOC_SERIES_IMX7_M4
config SOC_MCIMX7_M4
bool "SOC_MCIMX7_M4"
select HAS_IMX_HAL
select HAS_IMX_GPIO
endchoice

50
arch/arm/soc/nxp_imx/mcimx7_m4/dts.fixup
View file

@ -8,6 +8,56 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_GPIO_IMX_PORT_1_NAME NXP_IMX_GPIO_30200000_LABEL
#define CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS NXP_IMX_GPIO_30200000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_1_IRQ_0 NXP_IMX_GPIO_30200000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI NXP_IMX_GPIO_30200000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_1_IRQ_1 NXP_IMX_GPIO_30200000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI NXP_IMX_GPIO_30200000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_2_NAME NXP_IMX_GPIO_30210000_LABEL
#define CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS NXP_IMX_GPIO_30210000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_2_IRQ_0 NXP_IMX_GPIO_30210000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI NXP_IMX_GPIO_30210000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_2_IRQ_1 NXP_IMX_GPIO_30210000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI NXP_IMX_GPIO_30210000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_3_NAME NXP_IMX_GPIO_30220000_LABEL
#define CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS NXP_IMX_GPIO_30220000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_3_IRQ_0 NXP_IMX_GPIO_30220000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI NXP_IMX_GPIO_30220000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_3_IRQ_1 NXP_IMX_GPIO_30220000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI NXP_IMX_GPIO_30220000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_4_NAME NXP_IMX_GPIO_30230000_LABEL
#define CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS NXP_IMX_GPIO_30230000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_4_IRQ_0 NXP_IMX_GPIO_30230000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI NXP_IMX_GPIO_30230000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_4_IRQ_1 NXP_IMX_GPIO_30230000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI NXP_IMX_GPIO_30230000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_5_NAME NXP_IMX_GPIO_30240000_LABEL
#define CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS NXP_IMX_GPIO_30240000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_5_IRQ_0 NXP_IMX_GPIO_30240000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI NXP_IMX_GPIO_30240000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_5_IRQ_1 NXP_IMX_GPIO_30240000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI NXP_IMX_GPIO_30240000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_6_NAME NXP_IMX_GPIO_30250000_LABEL
#define CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS NXP_IMX_GPIO_30250000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_6_IRQ_0 NXP_IMX_GPIO_30250000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI NXP_IMX_GPIO_30250000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_6_IRQ_1 NXP_IMX_GPIO_30250000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI NXP_IMX_GPIO_30250000_IRQ_1_PRIORITY
#define CONFIG_GPIO_IMX_PORT_7_NAME NXP_IMX_GPIO_30260000_LABEL
#define CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS NXP_IMX_GPIO_30260000_BASE_ADDRESS
#define CONFIG_GPIO_IMX_PORT_7_IRQ_0 NXP_IMX_GPIO_30260000_IRQ_0
#define CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI NXP_IMX_GPIO_30260000_IRQ_0_PRIORITY
#define CONFIG_GPIO_IMX_PORT_7_IRQ_1 NXP_IMX_GPIO_30260000_IRQ_1
#define CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI NXP_IMX_GPIO_30260000_IRQ_1_PRIORITY
#define CONFIG_UART_IMX_UART_1_NAME NXP_IMX_UART_30860000_LABEL
#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS NXP_IMX_UART_30860000_BASE_ADDRESS
#define CONFIG_UART_IMX_UART_1_BAUD_RATE NXP_IMX_UART_30860000_CURRENT_SPEED

28
arch/arm/soc/nxp_imx/mcimx7_m4/soc.c
View file

@ -51,6 +51,30 @@ void SOC_RdcInit(void)
RDC_SetDomainID(RDC, rdcMdaM4, CONFIG_DOMAIN_ID, false);
}
#ifdef CONFIG_GPIO_IMX
static void nxp_mcimx7_gpio_config(void)
{
#ifdef CONFIG_GPIO_IMX_PORT_1
RDC_SetPdapAccess(RDC, rdcPdapGpio1,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Enable gpio clock gate */
CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
#endif /* CONFIG_GPIO_IMX_PORT_1 */
#ifdef CONFIG_GPIO_IMX_PORT_2
RDC_SetPdapAccess(RDC, rdcPdapGpio2,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Enable gpio clock gate */
CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
#endif /* CONFIG_GPIO_IMX_PORT_2 */
}
#endif /* CONFIG_GPIO_IMX */
#ifdef CONFIG_UART_IMX
static void nxp_mcimx7_uart_config(void)
{
@ -85,6 +109,10 @@ static int nxp_mcimx7_init(struct device *arg)
/* BoC specific clock settings */
SOC_ClockInit();
#ifdef CONFIG_GPIO_IMX
nxp_mcimx7_gpio_config();
#endif /* CONFIG_GPIO_IMX */
#ifdef CONFIG_UART_IMX
nxp_mcimx7_uart_config();
#endif /* CONFIG_UART_IMX */

66
dts/arm/nxp/nxp_imx7d_m4.dtsi
View file

@ -5,6 +5,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
@ -75,8 +76,71 @@
gpio1: gpio@30200000 {
compatible = "nxp,imx-gpio";
reg = <0x30200000 0x10000>;
interrupts = <62 0>, <63 0>;
interrupts = <64 0>, <65 0>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio@30210000 {
compatible = "nxp,imx-gpio";
reg = <0x30210000 0x10000>;
interrupts = <66 0>, <67 0>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio@30220000 {
compatible = "nxp,imx-gpio";
reg = <0x30220000 0x10000>;
interrupts = <68 0>, <69 0>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio@30230000 {
compatible = "nxp,imx-gpio";
reg = <0x30230000 0x10000>;
interrupts = <70 0>, <71 0>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio@30240000 {
compatible = "nxp,imx-gpio";
reg = <0x30240000 0x10000>;
interrupts = <72 0>, <73 0>;
label = "GPIO_5";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio@30250000 {
compatible = "nxp,imx-gpio";
reg = <0x30250000 0x10000>;
interrupts = <74 0>, <75 0>;
label = "GPIO_6";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio@30260000 {
compatible = "nxp,imx-gpio";
reg = <0x30260000 0x10000>;
interrupts = <76 0>, <77 0>;
label = "GPIO_7";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* For now only uart2 is supported and