patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

ITE: drivers/pwm: Add the flag of PWM output open-drain mode

Browse source 
This flag is used when the PWM output is set to open-drain mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2023-08-23 13:33:47 +08:00 committed by Carles Cufí
parent 6e1a205819
commit ed37374dac
4 changed files with 27 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/pwm/pwm_ite_it8xxx2.c
View file

@ -106,6 +106,11 @@ static int pwm_it8xxx2_set_cycles(const struct device *dev,
*reg_pwmpol &= ~BIT(ch);
}
/* Enable PWM output open-drain */
if (flags & PWM_IT8XXX2_OPEN_DRAIN) {
inst->PWMODENR |= BIT(ch);
}
/* If pulse cycles is 0, set duty cycle 0 and enable pwm channel */
if (pulse_cycles == 0) {
*reg_dcr = 0;

10
include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h
View file

@ -6,6 +6,8 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
#include <zephyr/dt-bindings/dt-util.h>
/* PWM prescaler references */
#define PWM_PRESCALER_C4 1
#define PWM_PRESCALER_C6 2
@ -21,4 +23,12 @@
#define PWM_CHANNEL_6 6
#define PWM_CHANNEL_7 7
/*
* Provides a type to hold PWM configuration flags.
*
* The upper 8 bits are reserved for SoC specific flags.
* Output onpe-drain flag [ 8 ]
*/
#define PWM_IT8XXX2_OPEN_DRAIN BIT(8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ */

8
soc/riscv/riscv-ite/common/check_regs.c
View file

@ -232,3 +232,11 @@ IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXFRDRB1, 0x0d);
IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_FTCB1R, 0x19);
IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_HPR2, 0x1e);
IT8XXX2_REG_OFFSET_CHECK(spisc_it8xxx2_regs, SPISC_RXVLISR, 0x27);
/* PWM register structure check */
IT8XXX2_REG_SIZE_CHECK(pwm_it8xxx2_regs, 0x4a);
IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C0CPRS, 0x00);
IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR1M, 0x10);
IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, C4CPRS, 0x27);
IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, CTR2, 0x42);
IT8XXX2_REG_OFFSET_CHECK(pwm_it8xxx2_regs, PWMODENR, 0x49);

4
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -221,6 +221,10 @@ struct pwm_it8xxx2_regs {
volatile uint8_t CTR2;
/* 0x043: Cycle Time3 */
volatile uint8_t CTR3;
/* 0x044~0x048: Reserved7 */
volatile uint8_t reserved7[5];
/* 0x049: PWM Output Open-Drain Enable */
volatile uint8_t PWMODENR;
};
#endif /* !__ASSEMBLER__ */