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ext: gecko: Add Silabs Gecko HAL for EFM32PG12B SoCs

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This includes the Gecko HAL files for the EFM32PG12B SoCs

Origin: Silicon Labs Gecko SDK
URL: https://github.com/SiliconLabs/Gecko_SDK
Version: v5.1.2 (SHA: 938464c68e6c3b2237388a692f767bb0767ec010)
Purpose: Add support for Silicon Labs EXX32 SoCs
License: Zlib
Maintained-by: External

Signed-off-by: Gil Benkö <gil.benkoe@pm.me>
This commit is contained in:
Gil Benkö 2018-04-11 10:30:27 +02:00 committed by Kumar Gala
parent a618ea2a5a
commit f0c7695348
56 changed files with 42514 additions and 4 deletions
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/**************************************************************************//**
* @file efm32pg12b_af_pins.h
* @brief EFM32PG12B_AF_PINS register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_AF_Pins
* @{
*****************************************************************************/
/** AF pin number for location number i */
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 15 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 7 : -1)
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 14 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 10 : (i) == 5 ? 15 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1)
#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : -1)
#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : -1)
#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 0 : -1)
#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1)
#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 12 : (i) == 12 ? 13 : (i) == 13 ? 14 : (i) == 14 ? 15 : -1)
#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : -1)
#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 9 : -1)
#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : -1)
#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : -1)
#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 0 : (i) == 10 ? 1 : -1)
#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : -1)
#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : -1)
#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 6 : -1)
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
#define AF_TIMER0_CC3_PIN(i) (-1)
#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
#define AF_TIMER0_CDTI3_PIN(i) (-1)
#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_TIMER1_CDTI0_PIN(i) (-1)
#define AF_TIMER1_CDTI1_PIN(i) (-1)
#define AF_TIMER1_CDTI2_PIN(i) (-1)
#define AF_TIMER1_CDTI3_PIN(i) (-1)
#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 12 : (i) == 13 ? 13 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 6 : (i) == 23 ? 7 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
#define AF_WTIMER0_CC3_PIN(i) (-1)
#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 8 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 11 : (i) == 8 ? 12 : (i) == 9 ? 13 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 8 : (i) == 25 ? 9 : (i) == 26 ? 10 : (i) == 27 ? 11 : (i) == 28 ? 12 : (i) == 29 ? 13 : (i) == 30 ? 14 : (i) == 31 ? 15 : -1)
#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 10 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 8 : (i) == 23 ? 9 : (i) == 24 ? 10 : (i) == 25 ? 11 : (i) == 26 ? 12 : (i) == 27 ? 13 : (i) == 28 ? 14 : (i) == 29 ? 15 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 0 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
#define AF_WTIMER0_CDTI3_PIN(i) (-1)
#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 4 : (i) == 9 ? 5 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 5 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 8 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 11 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 12 : (i) == 15 ? 13 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 6 : (i) == 25 ? 7 : (i) == 26 ? 8 : (i) == 27 ? 9 : (i) == 28 ? 10 : (i) == 29 ? 11 : (i) == 30 ? 12 : (i) == 31 ? 13 : -1)
#define AF_WTIMER1_CDTI0_PIN(i) (-1)
#define AF_WTIMER1_CDTI1_PIN(i) (-1)
#define AF_WTIMER1_CDTI2_PIN(i) (-1)
#define AF_WTIMER1_CDTI3_PIN(i) (-1)
#define AF_USART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_USART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
#define AF_USART0_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 12 : (i) == 6 ? 13 : (i) == 7 ? 14 : (i) == 8 ? 15 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 9 : (i) == 16 ? 10 : (i) == 17 ? 11 : (i) == 18 ? 12 : (i) == 19 ? 13 : (i) == 20 ? 14 : (i) == 21 ? 15 : (i) == 22 ? 0 : (i) == 23 ? 1 : (i) == 24 ? 2 : (i) == 25 ? 3 : (i) == 26 ? 4 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 0 : (i) == 31 ? 1 : -1)
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 12 : (i) == 18 ? 13 : (i) == 19 ? 14 : (i) == 20 ? 15 : (i) == 21 ? 0 : (i) == 22 ? 1 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 4 : (i) == 26 ? 5 : (i) == 27 ? 6 : (i) == 28 ? 7 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 12 : (i) == 17 ? 13 : (i) == 18 ? 14 : (i) == 19 ? 15 : (i) == 20 ? 0 : (i) == 21 ? 1 : (i) == 22 ? 2 : (i) == 23 ? 3 : (i) == 24 ? 4 : (i) == 25 ? 5 : (i) == 26 ? 6 : (i) == 27 ? 7 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 3 : -1)
#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 12 : (i) == 16 ? 13 : (i) == 17 ? 14 : (i) == 18 ? 15 : (i) == 19 ? 0 : (i) == 20 ? 1 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 4 : (i) == 24 ? 5 : (i) == 25 ? 6 : (i) == 26 ? 7 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 4 : -1)
#define AF_USART2_TX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 9 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_USART2_RX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 5 : -1)
#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 3 : (i) == 15 ? 4 : (i) == 16 ? 5 : (i) == 17 ? 6 : (i) == 18 ? 7 : (i) == 19 ? 8 : (i) == 20 ? 9 : (i) == 21 ? 10 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 5 : (i) == 31 ? 6 : -1)
#define AF_USART2_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 0 : (i) == 12 ? 1 : (i) == 13 ? 3 : (i) == 14 ? 4 : (i) == 15 ? 5 : (i) == 16 ? 6 : (i) == 17 ? 7 : (i) == 18 ? 8 : (i) == 19 ? 9 : (i) == 20 ? 10 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 0 : (i) == 11 ? 1 : (i) == 12 ? 3 : (i) == 13 ? 4 : (i) == 14 ? 5 : (i) == 15 ? 6 : (i) == 16 ? 7 : (i) == 17 ? 8 : (i) == 18 ? 9 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 8 : -1)
#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 9 : (i) == 8 ? 10 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 4 : (i) == 13 ? 5 : (i) == 14 ? 6 : (i) == 15 ? 7 : (i) == 16 ? 8 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 5 : (i) == 28 ? 6 : (i) == 29 ? 7 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
#define AF_USART3_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 9 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 14 : (i) == 7 ? 15 : (i) == 8 ? 2 : (i) == 9 ? 3 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 14 : (i) == 17 ? 15 : (i) == 18 ? 0 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 3 : (i) == 22 ? 4 : (i) == 23 ? 5 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_USART3_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 15 : (i) == 7 ? 2 : (i) == 8 ? 3 : (i) == 9 ? 6 : (i) == 10 ? 7 : (i) == 11 ? 8 : (i) == 12 ? 9 : (i) == 13 ? 10 : (i) == 14 ? 11 : (i) == 15 ? 14 : (i) == 16 ? 15 : (i) == 17 ? 0 : (i) == 18 ? 1 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 4 : (i) == 22 ? 5 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 8 : -1)
#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 13 : (i) == 4 ? 14 : (i) == 5 ? 15 : (i) == 6 ? 2 : (i) == 7 ? 3 : (i) == 8 ? 6 : (i) == 9 ? 7 : (i) == 10 ? 8 : (i) == 11 ? 9 : (i) == 12 ? 10 : (i) == 13 ? 11 : (i) == 14 ? 14 : (i) == 15 ? 15 : (i) == 16 ? 0 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 3 : (i) == 20 ? 4 : (i) == 21 ? 5 : (i) == 22 ? 11 : (i) == 23 ? 12 : (i) == 24 ? 13 : (i) == 25 ? 14 : (i) == 26 ? 15 : (i) == 27 ? 0 : (i) == 28 ? 1 : (i) == 29 ? 2 : (i) == 30 ? 8 : (i) == 31 ? 9 : -1)
#define AF_USART3_CS_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 13 : (i) == 3 ? 14 : (i) == 4 ? 15 : (i) == 5 ? 2 : (i) == 6 ? 3 : (i) == 7 ? 6 : (i) == 8 ? 7 : (i) == 9 ? 8 : (i) == 10 ? 9 : (i) == 11 ? 10 : (i) == 12 ? 11 : (i) == 13 ? 14 : (i) == 14 ? 15 : (i) == 15 ? 0 : (i) == 16 ? 1 : (i) == 17 ? 2 : (i) == 18 ? 3 : (i) == 19 ? 4 : (i) == 20 ? 5 : (i) == 21 ? 11 : (i) == 22 ? 12 : (i) == 23 ? 13 : (i) == 24 ? 14 : (i) == 25 ? 15 : (i) == 26 ? 0 : (i) == 27 ? 1 : (i) == 28 ? 2 : (i) == 29 ? 8 : (i) == 30 ? 9 : (i) == 31 ? 10 : -1)
#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 11 : (i) == 12 ? 14 : (i) == 13 ? 15 : (i) == 14 ? 0 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 4 : (i) == 19 ? 5 : (i) == 20 ? 11 : (i) == 21 ? 12 : (i) == 22 ? 13 : (i) == 23 ? 14 : (i) == 24 ? 15 : (i) == 25 ? 0 : (i) == 26 ? 1 : (i) == 27 ? 2 : (i) == 28 ? 8 : (i) == 29 ? 9 : (i) == 30 ? 10 : (i) == 31 ? 11 : -1)
#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 11 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 8 : (i) == 28 ? 9 : (i) == 29 ? 10 : (i) == 30 ? 11 : (i) == 31 ? 12 : -1)
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 6 : (i) == 20 ? 7 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 6 : (i) == 19 ? 7 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 5 : (i) == 5 ? 11 : (i) == 6 ? 12 : (i) == 7 ? 13 : (i) == 8 ? 14 : (i) == 9 ? 15 : (i) == 10 ? 6 : (i) == 11 ? 7 : (i) == 12 ? 8 : (i) == 13 ? 9 : (i) == 14 ? 10 : (i) == 15 ? 11 : (i) == 16 ? 9 : (i) == 17 ? 10 : (i) == 18 ? 11 : (i) == 19 ? 12 : (i) == 20 ? 13 : (i) == 21 ? 14 : (i) == 22 ? 15 : (i) == 23 ? 0 : (i) == 24 ? 1 : (i) == 25 ? 2 : (i) == 26 ? 3 : (i) == 27 ? 4 : (i) == 28 ? 5 : (i) == 29 ? 6 : (i) == 30 ? 7 : (i) == 31 ? 0 : -1)
#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 9 : (i) == 4 ? 2 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 7 : (i) == 8 ? 8 : (i) == 9 ? 9 : (i) == 10 ? 10 : (i) == 11 ? 14 : (i) == 12 ? 15 : (i) == 13 ? 0 : (i) == 14 ? 1 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 4 : (i) == 18 ? 5 : (i) == 19 ? 10 : (i) == 20 ? 11 : (i) == 21 ? 8 : (i) == 22 ? 9 : (i) == 23 ? 10 : (i) == 24 ? 11 : (i) == 25 ? 12 : (i) == 26 ? 13 : (i) == 27 ? 14 : (i) == 28 ? 15 : (i) == 29 ? 0 : (i) == 30 ? 1 : (i) == 31 ? 2 : -1)
#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 7 : (i) == 7 ? 8 : (i) == 8 ? 9 : (i) == 9 ? 10 : (i) == 10 ? 14 : (i) == 11 ? 15 : (i) == 12 ? 0 : (i) == 13 ? 1 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 4 : (i) == 17 ? 5 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 8 : (i) == 21 ? 9 : (i) == 22 ? 10 : (i) == 23 ? 11 : (i) == 24 ? 12 : (i) == 25 ? 13 : (i) == 26 ? 14 : (i) == 27 ? 15 : (i) == 28 ? 0 : (i) == 29 ? 1 : (i) == 30 ? 2 : (i) == 31 ? 6 : -1)
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 4 : (i) == 5 ? 5 : (i) == 6 ? 11 : (i) == 7 ? 12 : (i) == 8 ? 13 : (i) == 9 ? 14 : (i) == 10 ? 15 : (i) == 11 ? 6 : (i) == 12 ? 7 : (i) == 13 ? 8 : (i) == 14 ? 9 : (i) == 15 ? 10 : (i) == 16 ? 11 : (i) == 17 ? 9 : (i) == 18 ? 10 : (i) == 19 ? 11 : (i) == 20 ? 12 : (i) == 21 ? 13 : (i) == 22 ? 14 : (i) == 23 ? 15 : (i) == 24 ? 0 : (i) == 25 ? 1 : (i) == 26 ? 2 : (i) == 27 ? 3 : (i) == 28 ? 4 : (i) == 29 ? 5 : (i) == 30 ? 6 : (i) == 31 ? 7 : -1)
#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 9 : -1)
#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 10 : -1)
#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 11 : -1)
#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 12 : -1)
#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 13 : -1)
#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 14 : -1)
#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 15 : -1)
#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 1 : -1)
#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 4 : -1)
#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 5 : -1)
#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 6 : -1)
#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 7 : -1)
#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 9 : -1)
#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 14 : -1)
#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 15 : -1)
#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 1 : -1)
#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 2 : -1)
#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 3 : -1)
#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 3 : -1)
#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1)
#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 11 : -1)
#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1)
#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1)
#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 6 : -1)
#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 7 : -1)
#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 8 : -1)
#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 9 : -1)
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 8 : (i) == 3 ? 10 : -1)
/** @} End of group EFM32PG12B_AF_Pins */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_af_ports.h
* @brief EFM32PG12B_AF_PORTS register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_AF_Ports
* @{
*****************************************************************************/
/** AF port number for location number i */
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 0 : -1)
#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : -1)
#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1)
#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : (i) == 8 ? 3 : (i) == 9 ? 3 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : -1)
#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : -1)
#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : -1)
#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 0 : -1)
#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 0 : (i) == 10 ? 0 : -1)
#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 0 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : -1)
#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1)
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CC3_PORT(i) (-1)
#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER0_CDTI3_PORT(i) (-1)
#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_TIMER1_CDTI0_PORT(i) (-1)
#define AF_TIMER1_CDTI1_PORT(i) (-1)
#define AF_TIMER1_CDTI2_PORT(i) (-1)
#define AF_TIMER1_CDTI3_PORT(i) (-1)
#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 0 : (i) == 9 ? 0 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 1 : (i) == 19 ? 1 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 2 : (i) == 31 ? 2 : -1)
#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 1 : (i) == 17 ? 1 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 2 : (i) == 29 ? 2 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 2 : (i) == 25 ? 2 : (i) == 26 ? 2 : (i) == 27 ? 2 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_WTIMER0_CC3_PORT(i) (-1)
#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 3 : (i) == 25 ? 3 : (i) == 26 ? 3 : (i) == 27 ? 3 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER0_CDTI3_PORT(i) (-1)
#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 3 : (i) == 11 ? 3 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_WTIMER1_CDTI0_PORT(i) (-1)
#define AF_WTIMER1_CDTI1_PORT(i) (-1)
#define AF_WTIMER1_CDTI2_PORT(i) (-1)
#define AF_WTIMER1_CDTI3_PORT(i) (-1)
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 2 : (i) == 7 ? 2 : (i) == 8 ? 2 : (i) == 9 ? 2 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 3 : (i) == 13 ? 3 : (i) == 14 ? 3 : (i) == 15 ? 3 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART2_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
#define AF_USART2_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART2_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 8 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 5 : (i) == 10 ? 5 : (i) == 11 ? 5 : (i) == 12 ? 5 : (i) == 13 ? 5 : (i) == 14 ? 5 : (i) == 15 ? 5 : (i) == 16 ? 5 : (i) == 17 ? 5 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 0 : (i) == 28 ? 0 : (i) == 29 ? 0 : (i) == 30 ? 0 : (i) == 31 ? 0 : -1)
#define AF_USART3_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : (i) == 8 ? 8 : (i) == 9 ? 8 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 1 : (i) == 16 ? 9 : (i) == 17 ? 9 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 2 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
#define AF_USART3_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 8 : (i) == 8 ? 8 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 1 : (i) == 15 ? 9 : (i) == 16 ? 9 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 2 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 3 : -1)
#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 3 : (i) == 6 ? 8 : (i) == 7 ? 8 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 1 : (i) == 14 ? 9 : (i) == 15 ? 9 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 2 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_USART3_CS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 3 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 1 : (i) == 13 ? 9 : (i) == 14 ? 9 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 10 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 1 : (i) == 12 ? 9 : (i) == 13 ? 9 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 10 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 10 : (i) == 25 ? 10 : (i) == 26 ? 10 : (i) == 27 ? 3 : (i) == 28 ? 3 : (i) == 29 ? 3 : (i) == 30 ? 3 : (i) == 31 ? 3 : -1)
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 5 : (i) == 19 ? 5 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 2 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 3 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 0 : -1)
#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 9 : (i) == 12 ? 9 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 2 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 10 : -1)
#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 9 : (i) == 11 ? 9 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 2 : (i) == 18 ? 2 : (i) == 19 ? 2 : (i) == 20 ? 5 : (i) == 21 ? 5 : (i) == 22 ? 5 : (i) == 23 ? 5 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 10 : (i) == 29 ? 10 : (i) == 30 ? 10 : (i) == 31 ? 0 : -1)
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 1 : (i) == 8 ? 1 : (i) == 9 ? 1 : (i) == 10 ? 1 : (i) == 11 ? 2 : (i) == 12 ? 2 : (i) == 13 ? 2 : (i) == 14 ? 2 : (i) == 15 ? 2 : (i) == 16 ? 2 : (i) == 17 ? 3 : (i) == 18 ? 3 : (i) == 19 ? 3 : (i) == 20 ? 3 : (i) == 21 ? 3 : (i) == 22 ? 3 : (i) == 23 ? 3 : (i) == 24 ? 5 : (i) == 25 ? 5 : (i) == 26 ? 5 : (i) == 27 ? 5 : (i) == 28 ? 5 : (i) == 29 ? 5 : (i) == 30 ? 5 : (i) == 31 ? 5 : -1)
#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 3 : -1)
#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 0 : -1)
#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 9 : -1)
#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 9 : -1)
#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 8 : -1)
#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 8 : -1)
#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1)
#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1)
#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : -1)
#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1)
#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1)
#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1)
#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 8 : (i) == 3 ? 2 : -1)
#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1)
/** @} End of group EFM32PG12B_AF_Ports */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_cryotimer.h
* @brief EFM32PG12B_CRYOTIMER register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_CRYOTIMER
* @{
* @brief EFM32PG12B_CRYOTIMER Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t PERIODSEL; /**< Interrupt Duration */
__IM uint32_t CNT; /**< Counter Value */
__IOM uint32_t EM4WUEN; /**< Wake Up Enable */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
} CRYOTIMER_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_CRYOTIMER_BitFields
* @{
*****************************************************************************/
/* Bit fields for CRYOTIMER CTRL */
#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */
#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */
#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */
#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */
#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */
#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */
#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */
#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */
#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */
#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */
#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
/* Bit fields for CRYOTIMER PERIODSEL */
#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */
#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */
#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */
#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */
#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
/* Bit fields for CRYOTIMER CNT */
#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */
#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */
#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */
#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */
#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */
#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
/* Bit fields for CRYOTIMER EM4WUEN */
#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
/* Bit fields for CRYOTIMER IF */
#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup event/Interrupt */
#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
/* Bit fields for CRYOTIMER IFS */
#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */
#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */
#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */
#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */
#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
/* Bit fields for CRYOTIMER IFC */
#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */
#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */
#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */
#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */
#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
/* Bit fields for CRYOTIMER IEN */
#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */
#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */
#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */
#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
/** @} End of group EFM32PG12B_CRYOTIMER */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_dma_descriptor.h
* @brief EFM32PG12B_DMA_DESCRIPTOR register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_DMA_DESCRIPTOR
* @{
*****************************************************************************/
typedef struct
{
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
__IOM uint32_t CTRL; /**< DMA control register */
__IOM void * __IOM SRC; /**< DMA source address */
__IOM void * __IOM DST; /**< DMA destination address */
__IOM void * __IOM LINK; /**< DMA link address */
} DMA_DESCRIPTOR_TypeDef; /**< @} */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_dmareq.h
* @brief EFM32PG12B_DMAREQ register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_DMAREQ_BitFields
* @{
*****************************************************************************/
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
#define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
#define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
#define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
#define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
#define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
#define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
#define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
#define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
#define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
#define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
#define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */
#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
#define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */
#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
#define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */
#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
#define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */
#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
#define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */
#define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */
#define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
#define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
#define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */
#define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */
#define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */
#define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */
#define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */
/** @} End of group EFM32PG12B_DMAREQ */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_etm.h
* @brief EFM32PG12B_ETM register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_ETM
* @{
* @brief EFM32PG12B_ETM Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t ETMCR; /**< Main Control Register */
__IM uint32_t ETMCCR; /**< Configuration Code Register */
__IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IOM uint32_t ETMSR; /**< ETM Status Register */
__IM uint32_t ETMSCR; /**< ETM System Configuration Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
__IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
uint32_t RESERVED3[68]; /**< Reserved for future use **/
__IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
uint32_t RESERVED4[39]; /**< Reserved for future use **/
__IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
__IM uint32_t ETMIDR; /**< ID Register */
__IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
uint32_t RESERVED5[1]; /**< Reserved for future use **/
__IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
uint32_t RESERVED6[1]; /**< Reserved for future use **/
__IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
uint32_t RESERVED7[1]; /**< Reserved for future use **/
__IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
uint32_t RESERVED8[1]; /**< Reserved for future use **/
__IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
uint32_t RESERVED9[66]; /**< Reserved for future use **/
__IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
uint32_t RESERVED10[754]; /**< Reserved for future use **/
__IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
uint32_t RESERVED11[1]; /**< Reserved for future use **/
__IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
uint32_t RESERVED12[1]; /**< Reserved for future use **/
__IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
uint32_t RESERVED13[1]; /**< Reserved for future use **/
__IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
uint32_t RESERVED14[1]; /**< Reserved for future use **/
__IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
uint32_t RESERVED15[39]; /**< Reserved for future use **/
__IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
__IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
uint32_t RESERVED16[2]; /**< Reserved for future use **/
__IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
__IM uint32_t ETMLSR; /**< Lock Status Register */
__IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
uint32_t RESERVED17[4]; /**< Reserved for future use **/
__IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
__IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
__OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
__OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
__OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
__IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
__IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
__IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
__IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
__IM uint32_t ETMCIDR0; /**< Component ID0 Register */
__IM uint32_t ETMCIDR1; /**< Component ID1 Register */
__IM uint32_t ETMCIDR2; /**< Component ID2 Register */
__IM uint32_t ETMCIDR3; /**< Component ID3 Register */
} ETM_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_ETM_BitFields
* @{
*****************************************************************************/
/* Bit fields for ETM ETMCR */
#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
/* Bit fields for ETM ETMCCR */
#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
/* Bit fields for ETM ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
/* Bit fields for ETM ETMSR */
#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
/* Bit fields for ETM ETMSCR */
#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
/* Bit fields for ETM ETMTEEVR */
#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
/* Bit fields for ETM ETMTECR1 */
#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
/* Bit fields for ETM ETMFFLR */
#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
/* Bit fields for ETM ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
/* Bit fields for ETM ETMSYNCFR */
#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
/* Bit fields for ETM ETMIDR */
#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
/* Bit fields for ETM ETMCCER */
#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
/* Bit fields for ETM ETMTESSEICR */
#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
/* Bit fields for ETM ETMTSEVR */
#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
/* Bit fields for ETM ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
/* Bit fields for ETM ETMIDR2 */
#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
/* Bit fields for ETM ETMPDSR */
#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
/* Bit fields for ETM ETMISCIN */
#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
/* Bit fields for ETM ITTRIGOUT */
#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
/* Bit fields for ETM ETMITATBCTR2 */
#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
/* Bit fields for ETM ETMITATBCTR0 */
#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
/* Bit fields for ETM ETMITCTRL */
#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
/* Bit fields for ETM ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
/* Bit fields for ETM ETMCLAIMCLR */
#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
/* Bit fields for ETM ETMLAR */
#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
/* Bit fields for ETM ETMLSR */
#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
/* Bit fields for ETM ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
/* Bit fields for ETM ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
/* Bit fields for ETM ETMPIDR4 */
#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
/* Bit fields for ETM ETMPIDR5 */
#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
/* Bit fields for ETM ETMPIDR6 */
#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
/* Bit fields for ETM ETMPIDR7 */
#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
/* Bit fields for ETM ETMPIDR0 */
#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
/* Bit fields for ETM ETMPIDR1 */
#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
/* Bit fields for ETM ETMPIDR2 */
#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
/* Bit fields for ETM ETMPIDR3 */
#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
/* Bit fields for ETM ETMCIDR0 */
#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
/* Bit fields for ETM ETMCIDR1 */
#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
/* Bit fields for ETM ETMCIDR2 */
#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
/* Bit fields for ETM ETMCIDR3 */
#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
/** @} End of group EFM32PG12B_ETM */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_fpueh.h
* @brief EFM32PG12B_FPUEH register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_FPUEH
* @{
* @brief EFM32PG12B_FPUEH Register Declaration
*****************************************************************************/
typedef struct
{
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
} FPUEH_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_FPUEH_BitFields
* @{
*****************************************************************************/
/* Bit fields for FPUEH IF */
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
/* Bit fields for FPUEH IFS */
#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
/* Bit fields for FPUEH IFC */
#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
/* Bit fields for FPUEH IEN */
#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
/** @} End of group EFM32PG12B_FPUEH */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_gpcrc.h
* @brief EFM32PG12B_GPCRC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_GPCRC
* @{
* @brief EFM32PG12B_GPCRC Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t INIT; /**< CRC Init Value */
__IOM uint32_t POLY; /**< CRC Polynomial Value */
__IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
__IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
__IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
__IM uint32_t DATA; /**< CRC Data Register */
__IM uint32_t DATAREV; /**< CRC Data Reverse Register */
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
} GPCRC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_GPCRC_BitFields
* @{
*****************************************************************************/
/* Bit fields for GPCRC CTRL */
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
/* Bit fields for GPCRC CMD */
#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
/* Bit fields for GPCRC INIT */
#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
/* Bit fields for GPCRC POLY */
#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
/* Bit fields for GPCRC INPUTDATA */
#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
/* Bit fields for GPCRC INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
/* Bit fields for GPCRC INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
/* Bit fields for GPCRC DATA */
#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
/* Bit fields for GPCRC DATAREV */
#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
/* Bit fields for GPCRC DATABYTEREV */
#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
/** @} End of group EFM32PG12B_GPCRC */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_gpio_p.h
* @brief EFM32PG12B_GPIO_P register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief GPIO_P EFM32PG12B GPIO P
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Port Control Register */
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
__IOM uint32_t MODEH; /**< Port Pin Mode High Register */
__IOM uint32_t DOUT; /**< Port Data Out Register */
uint32_t RESERVED0[2]; /**< Reserved for future use **/
__IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
__IM uint32_t DIN; /**< Port Data In Register */
__IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
uint32_t RESERVED1[1]; /**< Reserved for future use **/
__IOM uint32_t OVTDIS; /**< Over Voltage Disable for all modes */
uint32_t RESERVED2[1]; /**< Reserved future */
} GPIO_P_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_i2c.h
* @brief EFM32PG12B_I2C register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_I2C
* @{
* @brief EFM32PG12B_I2C Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATE; /**< State Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CLKDIV; /**< Clock Division Register */
__IOM uint32_t SADDR; /**< Slave Address Register */
__IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
__IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
__IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
__IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
__IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
} I2C_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_I2C_BitFields
* @{
*****************************************************************************/
/* Bit fields for I2C CTRL */
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
/* Bit fields for I2C CMD */
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
/* Bit fields for I2C STATE */
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
/* Bit fields for I2C STATUS */
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
/* Bit fields for I2C CLKDIV */
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
/* Bit fields for I2C SADDR */
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
/* Bit fields for I2C SADDRMASK */
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
/* Bit fields for I2C RXDATA */
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
/* Bit fields for I2C RXDOUBLE */
#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
/* Bit fields for I2C RXDATAP */
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
/* Bit fields for I2C RXDOUBLEP */
#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
/* Bit fields for I2C TXDATA */
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
/* Bit fields for I2C TXDOUBLE */
#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
/* Bit fields for I2C IF */
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
/* Bit fields for I2C IFS */
#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
/* Bit fields for I2C IFC */
#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
/* Bit fields for I2C IEN */
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
/* Bit fields for I2C ROUTEPEN */
#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
/* Bit fields for I2C ROUTELOC0 */
#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
#define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */
#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
#define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */
#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
#define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
#define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
/** @} End of group EFM32PG12B_I2C */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_idac.h
* @brief EFM32PG12B_IDAC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_IDAC
* @{
* @brief EFM32PG12B_IDAC Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CURPROG; /**< Current Programming Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IM uint32_t STATUS; /**< Status Register */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED3[1]; /**< Reserved for future use **/
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
} IDAC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_IDAC_BitFields
* @{
*****************************************************************************/
/* Bit fields for IDAC CTRL */
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
#define _IDAC_CTRL_MASK 0x00FD7FFFUL /**< Mask for IDAC_CTRL */
#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */
#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */
#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */
#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */
#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */
#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */
#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
#define _IDAC_CTRL_PRSSEL_MASK 0xF00000UL /**< Bit mask for IDAC_PRSSEL */
#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
/* Bit fields for IDAC CURPROG */
#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
/* Bit fields for IDAC DUTYCONFIG */
#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable. */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
/* Bit fields for IDAC STATUS */
#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */
#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */
#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */
#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
/* Bit fields for IDAC IF */
#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */
#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */
#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
/* Bit fields for IDAC IFS */
#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */
#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */
#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */
#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
/* Bit fields for IDAC IFC */
#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */
#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */
#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */
#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
/* Bit fields for IDAC IEN */
#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */
#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */
#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */
#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
/* Bit fields for IDAC APORTREQ */
#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 if the APORT bus connected to APORT1X is requested */
#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is requested */
#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
/* Bit fields for IDAC APORTCONFLICT */
#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 if the bus connected to APORT1X is in conflict with another peripheral */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 if the bus connected to APORT1Y is in conflict with another peripheral */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
/** @} End of group EFM32PG12B_IDAC */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_ldma.h
* @brief EFM32PG12B_LDMA register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_LDMA
* @{
* @brief EFM32PG12B_LDMA Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< DMA Control Register */
__IM uint32_t STATUS; /**< DMA Status Register */
__IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
uint32_t RESERVED0[5]; /**< Reserved for future use **/
__IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
__IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
__IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
__IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
__IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
__IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
__IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
__IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
__IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
uint32_t RESERVED1[7]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable register */
uint32_t RESERVED2[4]; /**< Reserved registers */
LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */
} LDMA_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_LDMA_BitFields
* @{
*****************************************************************************/
/* Bit fields for LDMA CTRL */
#define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
#define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */
#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
#define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */
#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */
#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
/* Bit fields for LDMA STATUS */
#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */
#define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */
#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
#define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */
#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
#define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */
#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */
#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
/* Bit fields for LDMA SYNC */
#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
/* Bit fields for LDMA CHEN */
#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
/* Bit fields for LDMA CHBUSY */
#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
/* Bit fields for LDMA CHDONE */
#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
#define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
/* Bit fields for LDMA DBGHALT */
#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
/* Bit fields for LDMA SWREQ */
#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
/* Bit fields for LDMA REQDIS */
#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
/* Bit fields for LDMA REQPEND */
#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
/* Bit fields for LDMA LINKLOAD */
#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
/* Bit fields for LDMA REQCLEAR */
#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
/* Bit fields for LDMA IF */
#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
#define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
/* Bit fields for LDMA IFS */
#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
#define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */
#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
#define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
/* Bit fields for LDMA IFC */
#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
#define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */
#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
#define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
/* Bit fields for LDMA IEN */
#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
#define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
/* Bit fields for LDMA CH_REQSEL */
#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR /**< Alias for mode CRYPTO0DATA0WR */
#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR 0x00000000UL /**< Mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR /**< Alias for mode CRYPTO0DATA0XWR */
#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR 0x00000001UL /**< Mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD /**< Alias for mode CRYPTO0DATA0RD */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD 0x00000002UL /**< Mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR /**< Alias for mode CRYPTO0DATA1WR */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR 0x00000003UL /**< Mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD /**< Alias for mode CRYPTO0DATA1RD */
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD 0x00000004UL /**< Mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR << 0) /**< Shifted mode CRYPTO1DATA0WR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR << 0) /**< Shifted mode CRYPTO1DATA0XWR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD << 0) /**< Shifted mode CRYPTO1DATA0RD for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR << 0) /**< Shifted mode CRYPTO1DATA1WR for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD << 0) /**< Shifted mode CRYPTO1DATA1RD for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x0000001AUL /**< Mode WTIMER0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x0000001BUL /**< Mode WTIMER1 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 /**< Alias for mode CRYPTO0 */
#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x00000032UL /**< Mode CSEN for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x00000033UL /**< Mode LESENSE for LDMA_CH_REQSEL */
#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 0x00000034UL /**< Mode CRYPTO1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO1 << 16) /**< Shifted mode CRYPTO1 for LDMA_CH_REQSEL */
/* Bit fields for LDMA CH_CFG */
#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
/* Bit fields for LDMA CH_LOOP */
#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
/* Bit fields for LDMA CH_CTRL */
#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
/* Bit fields for LDMA CH_SRC */
#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
/* Bit fields for LDMA CH_DST */
#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
/* Bit fields for LDMA CH_LINK */
#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
/** @} End of group EFM32PG12B_LDMA */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_ldma_ch.h
* @brief EFM32PG12B_LDMA_CH register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LDMA_CH EFM32PG12B LDMA CH
*****************************************************************************/
typedef struct
{
__IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
__IOM uint32_t CFG; /**< Channel Configuration Register */
__IOM uint32_t LOOP; /**< Channel Loop Counter Register */
__IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
__IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
__IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
__IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
uint32_t RESERVED0[5]; /**< Reserved future */
} LDMA_CH_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_lesense_buf.h
* @brief EFM32PG12B_LESENSE_BUF register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_BUF EFM32PG12B LESENSE BUF
*****************************************************************************/
typedef struct
{
__IOM uint32_t DATA; /**< Scan results */
} LESENSE_BUF_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_lesense_ch.h
* @brief EFM32PG12B_LESENSE_CH register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_CH EFM32PG12B LESENSE CH
*****************************************************************************/
typedef struct
{
__IOM uint32_t TIMING; /**< Scan configuration */
__IOM uint32_t INTERACT; /**< Scan configuration */
__IOM uint32_t EVAL; /**< Scan configuration */
uint32_t RESERVED0[1]; /**< Reserved future */
} LESENSE_CH_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_lesense_st.h
* @brief EFM32PG12B_LESENSE_ST register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief LESENSE_ST EFM32PG12B LESENSE ST
*****************************************************************************/
typedef struct
{
__IOM uint32_t TCONFA; /**< State transition configuration A */
__IOM uint32_t TCONFB; /**< State transition configuration B */
} LESENSE_ST_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_letimer.h
* @brief EFM32PG12B_LETIMER register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_LETIMER
* @{
* @brief EFM32PG12B_LETIMER Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CNT; /**< Counter Value Register */
__IOM uint32_t COMP0; /**< Compare Value Register 0 */
__IOM uint32_t COMP1; /**< Compare Value Register 1 */
__IOM uint32_t REP0; /**< Repeat Counter Register 0 */
__IOM uint32_t REP1; /**< Repeat Counter Register 1 */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
uint32_t RESERVED2[2]; /**< Reserved for future use **/
__IOM uint32_t PRSSEL; /**< PRS Input Select Register */
} LETIMER_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_LETIMER_BitFields
* @{
*****************************************************************************/
/* Bit fields for LETIMER CTRL */
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
/* Bit fields for LETIMER CMD */
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
/* Bit fields for LETIMER STATUS */
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
/* Bit fields for LETIMER CNT */
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
/* Bit fields for LETIMER COMP0 */
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
/* Bit fields for LETIMER COMP1 */
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
/* Bit fields for LETIMER REP0 */
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
/* Bit fields for LETIMER REP1 */
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
/* Bit fields for LETIMER IF */
#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
/* Bit fields for LETIMER IFS */
#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */
#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */
#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */
#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */
#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */
#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
/* Bit fields for LETIMER IFC */
#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */
#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */
#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */
#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */
#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */
#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
/* Bit fields for LETIMER IEN */
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */
#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */
#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */
#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */
#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */
#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
/* Bit fields for LETIMER SYNCBUSY */
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
/* Bit fields for LETIMER ROUTEPEN */
#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */
#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */
#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
/* Bit fields for LETIMER ROUTELOC0 */
#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */
#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x1FUL /**< Bit mask for LETIMER_OUT0LOC */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC8 (_LETIMER_ROUTELOC0_OUT0LOC_LOC8 << 0) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC9 (_LETIMER_ROUTELOC0_OUT0LOC_LOC9 << 0) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC10 (_LETIMER_ROUTELOC0_OUT0LOC_LOC10 << 0) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC11 (_LETIMER_ROUTELOC0_OUT0LOC_LOC11 << 0) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC12 (_LETIMER_ROUTELOC0_OUT0LOC_LOC12 << 0) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC13 (_LETIMER_ROUTELOC0_OUT0LOC_LOC13 << 0) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC14 (_LETIMER_ROUTELOC0_OUT0LOC_LOC14 << 0) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC15 (_LETIMER_ROUTELOC0_OUT0LOC_LOC15 << 0) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC16 (_LETIMER_ROUTELOC0_OUT0LOC_LOC16 << 0) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC17 (_LETIMER_ROUTELOC0_OUT0LOC_LOC17 << 0) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC18 (_LETIMER_ROUTELOC0_OUT0LOC_LOC18 << 0) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC19 (_LETIMER_ROUTELOC0_OUT0LOC_LOC19 << 0) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC20 (_LETIMER_ROUTELOC0_OUT0LOC_LOC20 << 0) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC21 (_LETIMER_ROUTELOC0_OUT0LOC_LOC21 << 0) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC22 (_LETIMER_ROUTELOC0_OUT0LOC_LOC22 << 0) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC23 (_LETIMER_ROUTELOC0_OUT0LOC_LOC23 << 0) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC24 (_LETIMER_ROUTELOC0_OUT0LOC_LOC24 << 0) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC25 (_LETIMER_ROUTELOC0_OUT0LOC_LOC25 << 0) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC26 (_LETIMER_ROUTELOC0_OUT0LOC_LOC26 << 0) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC27 (_LETIMER_ROUTELOC0_OUT0LOC_LOC27 << 0) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC28 (_LETIMER_ROUTELOC0_OUT0LOC_LOC28 << 0) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC29 (_LETIMER_ROUTELOC0_OUT0LOC_LOC29 << 0) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC30 (_LETIMER_ROUTELOC0_OUT0LOC_LOC30 << 0) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT0LOC_LOC31 (_LETIMER_ROUTELOC0_OUT0LOC_LOC31 << 0) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */
#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x1F00UL /**< Bit mask for LETIMER_OUT1LOC */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC8 0x00000008UL /**< Mode LOC8 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC9 0x00000009UL /**< Mode LOC9 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC16 0x00000010UL /**< Mode LOC16 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC17 0x00000011UL /**< Mode LOC17 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC18 0x00000012UL /**< Mode LOC18 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC19 0x00000013UL /**< Mode LOC19 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC20 0x00000014UL /**< Mode LOC20 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC21 0x00000015UL /**< Mode LOC21 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC22 0x00000016UL /**< Mode LOC22 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC23 0x00000017UL /**< Mode LOC23 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC24 0x00000018UL /**< Mode LOC24 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC25 0x00000019UL /**< Mode LOC25 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for LETIMER_ROUTELOC0 */
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC8 (_LETIMER_ROUTELOC0_OUT1LOC_LOC8 << 8) /**< Shifted mode LOC8 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC9 (_LETIMER_ROUTELOC0_OUT1LOC_LOC9 << 8) /**< Shifted mode LOC9 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC10 (_LETIMER_ROUTELOC0_OUT1LOC_LOC10 << 8) /**< Shifted mode LOC10 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC11 (_LETIMER_ROUTELOC0_OUT1LOC_LOC11 << 8) /**< Shifted mode LOC11 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC12 (_LETIMER_ROUTELOC0_OUT1LOC_LOC12 << 8) /**< Shifted mode LOC12 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC13 (_LETIMER_ROUTELOC0_OUT1LOC_LOC13 << 8) /**< Shifted mode LOC13 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC14 (_LETIMER_ROUTELOC0_OUT1LOC_LOC14 << 8) /**< Shifted mode LOC14 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC15 (_LETIMER_ROUTELOC0_OUT1LOC_LOC15 << 8) /**< Shifted mode LOC15 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC16 (_LETIMER_ROUTELOC0_OUT1LOC_LOC16 << 8) /**< Shifted mode LOC16 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC17 (_LETIMER_ROUTELOC0_OUT1LOC_LOC17 << 8) /**< Shifted mode LOC17 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC18 (_LETIMER_ROUTELOC0_OUT1LOC_LOC18 << 8) /**< Shifted mode LOC18 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC19 (_LETIMER_ROUTELOC0_OUT1LOC_LOC19 << 8) /**< Shifted mode LOC19 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC20 (_LETIMER_ROUTELOC0_OUT1LOC_LOC20 << 8) /**< Shifted mode LOC20 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC21 (_LETIMER_ROUTELOC0_OUT1LOC_LOC21 << 8) /**< Shifted mode LOC21 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC22 (_LETIMER_ROUTELOC0_OUT1LOC_LOC22 << 8) /**< Shifted mode LOC22 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC23 (_LETIMER_ROUTELOC0_OUT1LOC_LOC23 << 8) /**< Shifted mode LOC23 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC24 (_LETIMER_ROUTELOC0_OUT1LOC_LOC24 << 8) /**< Shifted mode LOC24 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC25 (_LETIMER_ROUTELOC0_OUT1LOC_LOC25 << 8) /**< Shifted mode LOC25 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC26 (_LETIMER_ROUTELOC0_OUT1LOC_LOC26 << 8) /**< Shifted mode LOC26 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC27 (_LETIMER_ROUTELOC0_OUT1LOC_LOC27 << 8) /**< Shifted mode LOC27 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC28 (_LETIMER_ROUTELOC0_OUT1LOC_LOC28 << 8) /**< Shifted mode LOC28 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC29 (_LETIMER_ROUTELOC0_OUT1LOC_LOC29 << 8) /**< Shifted mode LOC29 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC30 (_LETIMER_ROUTELOC0_OUT1LOC_LOC30 << 8) /**< Shifted mode LOC30 for LETIMER_ROUTELOC0 */
#define LETIMER_ROUTELOC0_OUT1LOC_LOC31 (_LETIMER_ROUTELOC0_OUT1LOC_LOC31 << 8) /**< Shifted mode LOC31 for LETIMER_ROUTELOC0 */
/* Bit fields for LETIMER PRSSEL */
#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_MASK 0x0CCCF3CFUL /**< Mask for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0xFUL /**< Bit mask for LETIMER_PRSSTARTSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x3C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0xF000UL /**< Bit mask for LETIMER_PRSCLEARSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
/** @} End of group EFM32PG12B_LETIMER */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_leuart.h
* @brief EFM32PG12B_LEUART register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_LEUART
* @{
* @brief EFM32PG12B_LEUART Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t CLKDIV; /**< Clock Control Register */
__IOM uint32_t STARTFRAME; /**< Start Frame Register */
__IOM uint32_t SIGFRAME; /**< Signal Frame Register */
__IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
__IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
__IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t PULSECTRL; /**< Pulse Control Register */
__IOM uint32_t FREEZE; /**< Freeze Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
uint32_t RESERVED1[2]; /**< Reserved for future use **/
__IOM uint32_t INPUT; /**< LEUART Input Register */
} LEUART_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_LEUART_BitFields
* @{
*****************************************************************************/
/* Bit fields for LEUART CTRL */
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
/* Bit fields for LEUART CMD */
#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
/* Bit fields for LEUART STATUS */
#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */
#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */
#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */
#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */
#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */
#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */
/* Bit fields for LEUART CLKDIV */
#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */
#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */
#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
/* Bit fields for LEUART STARTFRAME */
#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
/* Bit fields for LEUART SIGFRAME */
#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
/* Bit fields for LEUART RXDATAX */
#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
/* Bit fields for LEUART RXDATA */
#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
/* Bit fields for LEUART RXDATAXP */
#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
/* Bit fields for LEUART TXDATAX */
#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
/* Bit fields for LEUART TXDATA */
#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
/* Bit fields for LEUART IF */
#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
/* Bit fields for LEUART IFS */
#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */
#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */
#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */
#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */
#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */
#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */
#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */
#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */
#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
/* Bit fields for LEUART IFC */
#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */
#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */
#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */
#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */
#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */
#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */
#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */
#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */
#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
/* Bit fields for LEUART IEN */
#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */
#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */
#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */
#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */
#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */
#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */
#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */
#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */
#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
/* Bit fields for LEUART PULSECTRL */
#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
/* Bit fields for LEUART FREEZE */
#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
/* Bit fields for LEUART SYNCBUSY */
#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
/* Bit fields for LEUART ROUTEPEN */
#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */
#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */
#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
/* Bit fields for LEUART ROUTELOC0 */
#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */
#define _LEUART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for LEUART_RXLOC */
#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC6 (_LEUART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC7 (_LEUART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC8 (_LEUART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC9 (_LEUART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC10 (_LEUART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC11 (_LEUART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC12 (_LEUART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC13 (_LEUART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC14 (_LEUART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC15 (_LEUART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC16 (_LEUART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC17 (_LEUART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC18 (_LEUART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC19 (_LEUART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC20 (_LEUART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC21 (_LEUART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC22 (_LEUART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC23 (_LEUART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC24 (_LEUART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC25 (_LEUART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC26 (_LEUART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC27 (_LEUART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC28 (_LEUART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC29 (_LEUART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC30 (_LEUART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_RXLOC_LOC31 (_LEUART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */
#define _LEUART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for LEUART_TXLOC */
#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for LEUART_ROUTELOC0 */
#define _LEUART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC6 (_LEUART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC7 (_LEUART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC8 (_LEUART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC9 (_LEUART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC10 (_LEUART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC11 (_LEUART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC12 (_LEUART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC13 (_LEUART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC14 (_LEUART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC15 (_LEUART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC16 (_LEUART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC17 (_LEUART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC18 (_LEUART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC19 (_LEUART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC20 (_LEUART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC21 (_LEUART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC22 (_LEUART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC23 (_LEUART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC24 (_LEUART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC25 (_LEUART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC26 (_LEUART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC27 (_LEUART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC28 (_LEUART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC29 (_LEUART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC30 (_LEUART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for LEUART_ROUTELOC0 */
#define LEUART_ROUTELOC0_TXLOC_LOC31 (_LEUART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for LEUART_ROUTELOC0 */
/* Bit fields for LEUART INPUT */
#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
#define _LEUART_INPUT_MASK 0x0000002FUL /**< Mask for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
#define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */
#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */
#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */
#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
/** @} End of group EFM32PG12B_LEUART */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_msc.h
* @brief EFM32PG12B_MSC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_MSC
* @{
* @brief EFM32PG12B_MSC Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Memory System Control Register */
__IOM uint32_t READCTRL; /**< Read Control Register */
__IOM uint32_t WRITECTRL; /**< Write Control Register */
__IOM uint32_t WRITECMD; /**< Write Command Register */
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IOM uint32_t WDATA; /**< Write Data Register */
__IM uint32_t STATUS; /**< Status Register */
uint32_t RESERVED1[4]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
__IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
__IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
uint32_t RESERVED2[1]; /**< Reserved for future use **/
__IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
uint32_t RESERVED3[1]; /**< Reserved for future use **/
__IOM uint32_t STARTUP; /**< Startup Control */
uint32_t RESERVED4[4]; /**< Reserved for future use **/
__IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */
__IOM uint32_t CMD; /**< Command Register */
uint32_t RESERVED5[6]; /**< Reserved for future use **/
__IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */
__IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */
__IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */
uint32_t RESERVED6[25]; /**< Reserved for future use **/
__IOM uint32_t RAMCTRL; /**< RAM Control enable Register */
} MSC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_MSC_BitFields
* @{
*****************************************************************************/
/* Bit fields for MSC CTRL */
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
#define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */
#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */
#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */
#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */
#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */
/* Bit fields for MSC READCTRL */
#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
#define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */
#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */
#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */
#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
/* Bit fields for MSC WRITECTRL */
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */
#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */
#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */
#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
/* Bit fields for MSC WRITECMD */
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */
#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */
#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */
#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
/* Bit fields for MSC ADDRB */
#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
/* Bit fields for MSC WDATA */
#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
/* Bit fields for MSC STATUS */
#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */
#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */
#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */
#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */
#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */
#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */
#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */
#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
/* Bit fields for MSC IF */
#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
#define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */
#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */
#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */
#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */
#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */
#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
/* Bit fields for MSC IFS */
#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
#define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */
#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */
#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */
#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */
#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */
/* Bit fields for MSC IFC */
#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
#define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */
#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */
#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */
#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */
#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */
/* Bit fields for MSC IEN */
#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
#define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */
#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */
#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */
#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */
#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
/* Bit fields for MSC LOCK */
#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
/* Bit fields for MSC CACHECMD */
#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
/* Bit fields for MSC CACHEHITS */
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
/* Bit fields for MSC CACHEMISSES */
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
/* Bit fields for MSC MASSLOCK */
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
/* Bit fields for MSC STARTUP */
#define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */
#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
#define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
/* Bit fields for MSC BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
/* Bit fields for MSC CMD */
#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */
#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */
#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */
#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */
#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
/* Bit fields for MSC BOOTLOADERCTRL */
#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */
#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */
#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */
#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */
#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */
#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */
#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */
#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */
#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
/* Bit fields for MSC AAPUNLOCKCMD */
#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */
#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */
#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */
/* Bit fields for MSC CACHECONFIG0 */
#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */
#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */
#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */
#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */
#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */
#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
/* Bit fields for MSC RAMCTRL */
#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */
#define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */
#define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */
#define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */
#define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */
#define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */
#define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */
#define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */
#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */
#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */
#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */
#define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */
#define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */
#define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
#define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
/** @} End of group EFM32PG12B_MSC */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_pcnt.h
* @brief EFM32PG12B_PCNT register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_PCNT
* @{
* @brief EFM32PG12B_PCNT Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IM uint32_t CNT; /**< Counter Value Register */
__IM uint32_t TOP; /**< Top Value Register */
__IOM uint32_t TOPB; /**< Top Value Buffer Register */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
uint32_t RESERVED1[4]; /**< Reserved for future use **/
__IOM uint32_t FREEZE; /**< Freeze Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
uint32_t RESERVED2[7]; /**< Reserved for future use **/
__IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
__IOM uint32_t INPUT; /**< PCNT Input Register */
__IOM uint32_t OVSCFG; /**< Oversampling Config Register */
} PCNT_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_PCNT_BitFields
* @{
*****************************************************************************/
/* Bit fields for PCNT CTRL */
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
#define _PCNT_CTRL_MASK 0xBFDBFFFFUL /**< Mask for PCNT_CTRL */
#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */
#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */
#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */
#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */
#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */
#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */
#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */
#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */
#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */
#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */
#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */
#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */
#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */
#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */
#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */
#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */
#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */
#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */
#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */
#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */
#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */
#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */
#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */
#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */
#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */
#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */
#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */
#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */
#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */
#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */
#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */
#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */
#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */
#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */
#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */
#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */
#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */
#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */
#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */
#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */
#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */
#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */
#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */
#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */
#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */
#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */
#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */
#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */
#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS gate enable */
#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS polarity select */
#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */
#define _PCNT_CTRL_TCCPRSSEL_MASK 0x3C000000UL /**< Bit mask for PCNT_TCCPRSSEL */
#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */
#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High frequency value select */
#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */
/* Bit fields for PCNT CMD */
#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
/* Bit fields for PCNT STATUS */
#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
/* Bit fields for PCNT CNT */
#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
/* Bit fields for PCNT TOP */
#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
/* Bit fields for PCNT TOPB */
#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
/* Bit fields for PCNT IF */
#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */
#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered compare Interrupt Read Flag */
#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */
#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */
/* Bit fields for PCNT IFS */
#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */
#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */
#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */
#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */
#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */
#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */
#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */
#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */
/* Bit fields for PCNT IFC */
#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */
#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */
#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */
#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */
#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */
#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */
#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */
#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */
/* Bit fields for PCNT IEN */
#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */
#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */
#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */
#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */
#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */
#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */
#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */
#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */
/* Bit fields for PCNT ROUTELOC0 */
#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */
#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x1FUL /**< Bit mask for PCNT_S0INLOC */
#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S0INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC8 (_PCNT_ROUTELOC0_S0INLOC_LOC8 << 0) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC9 (_PCNT_ROUTELOC0_S0INLOC_LOC9 << 0) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC10 (_PCNT_ROUTELOC0_S0INLOC_LOC10 << 0) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC11 (_PCNT_ROUTELOC0_S0INLOC_LOC11 << 0) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC12 (_PCNT_ROUTELOC0_S0INLOC_LOC12 << 0) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC13 (_PCNT_ROUTELOC0_S0INLOC_LOC13 << 0) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC14 (_PCNT_ROUTELOC0_S0INLOC_LOC14 << 0) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC15 (_PCNT_ROUTELOC0_S0INLOC_LOC15 << 0) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC16 (_PCNT_ROUTELOC0_S0INLOC_LOC16 << 0) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC17 (_PCNT_ROUTELOC0_S0INLOC_LOC17 << 0) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC18 (_PCNT_ROUTELOC0_S0INLOC_LOC18 << 0) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC19 (_PCNT_ROUTELOC0_S0INLOC_LOC19 << 0) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC20 (_PCNT_ROUTELOC0_S0INLOC_LOC20 << 0) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC21 (_PCNT_ROUTELOC0_S0INLOC_LOC21 << 0) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC22 (_PCNT_ROUTELOC0_S0INLOC_LOC22 << 0) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC23 (_PCNT_ROUTELOC0_S0INLOC_LOC23 << 0) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC24 (_PCNT_ROUTELOC0_S0INLOC_LOC24 << 0) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC25 (_PCNT_ROUTELOC0_S0INLOC_LOC25 << 0) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC26 (_PCNT_ROUTELOC0_S0INLOC_LOC26 << 0) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC27 (_PCNT_ROUTELOC0_S0INLOC_LOC27 << 0) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC28 (_PCNT_ROUTELOC0_S0INLOC_LOC28 << 0) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC29 (_PCNT_ROUTELOC0_S0INLOC_LOC29 << 0) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC30 (_PCNT_ROUTELOC0_S0INLOC_LOC30 << 0) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S0INLOC_LOC31 (_PCNT_ROUTELOC0_S0INLOC_LOC31 << 0) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */
#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x1F00UL /**< Bit mask for PCNT_S1INLOC */
#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC8 0x00000008UL /**< Mode LOC8 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC9 0x00000009UL /**< Mode LOC9 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC10 0x0000000AUL /**< Mode LOC10 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC11 0x0000000BUL /**< Mode LOC11 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC12 0x0000000CUL /**< Mode LOC12 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC13 0x0000000DUL /**< Mode LOC13 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC14 0x0000000EUL /**< Mode LOC14 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC15 0x0000000FUL /**< Mode LOC15 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC16 0x00000010UL /**< Mode LOC16 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC17 0x00000011UL /**< Mode LOC17 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC18 0x00000012UL /**< Mode LOC18 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC19 0x00000013UL /**< Mode LOC19 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC20 0x00000014UL /**< Mode LOC20 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC21 0x00000015UL /**< Mode LOC21 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC22 0x00000016UL /**< Mode LOC22 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC23 0x00000017UL /**< Mode LOC23 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC24 0x00000018UL /**< Mode LOC24 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC25 0x00000019UL /**< Mode LOC25 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC26 0x0000001AUL /**< Mode LOC26 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC27 0x0000001BUL /**< Mode LOC27 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC28 0x0000001CUL /**< Mode LOC28 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC29 0x0000001DUL /**< Mode LOC29 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC30 0x0000001EUL /**< Mode LOC30 for PCNT_ROUTELOC0 */
#define _PCNT_ROUTELOC0_S1INLOC_LOC31 0x0000001FUL /**< Mode LOC31 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC8 (_PCNT_ROUTELOC0_S1INLOC_LOC8 << 8) /**< Shifted mode LOC8 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC9 (_PCNT_ROUTELOC0_S1INLOC_LOC9 << 8) /**< Shifted mode LOC9 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC10 (_PCNT_ROUTELOC0_S1INLOC_LOC10 << 8) /**< Shifted mode LOC10 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC11 (_PCNT_ROUTELOC0_S1INLOC_LOC11 << 8) /**< Shifted mode LOC11 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC12 (_PCNT_ROUTELOC0_S1INLOC_LOC12 << 8) /**< Shifted mode LOC12 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC13 (_PCNT_ROUTELOC0_S1INLOC_LOC13 << 8) /**< Shifted mode LOC13 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC14 (_PCNT_ROUTELOC0_S1INLOC_LOC14 << 8) /**< Shifted mode LOC14 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC15 (_PCNT_ROUTELOC0_S1INLOC_LOC15 << 8) /**< Shifted mode LOC15 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC16 (_PCNT_ROUTELOC0_S1INLOC_LOC16 << 8) /**< Shifted mode LOC16 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC17 (_PCNT_ROUTELOC0_S1INLOC_LOC17 << 8) /**< Shifted mode LOC17 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC18 (_PCNT_ROUTELOC0_S1INLOC_LOC18 << 8) /**< Shifted mode LOC18 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC19 (_PCNT_ROUTELOC0_S1INLOC_LOC19 << 8) /**< Shifted mode LOC19 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC20 (_PCNT_ROUTELOC0_S1INLOC_LOC20 << 8) /**< Shifted mode LOC20 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC21 (_PCNT_ROUTELOC0_S1INLOC_LOC21 << 8) /**< Shifted mode LOC21 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC22 (_PCNT_ROUTELOC0_S1INLOC_LOC22 << 8) /**< Shifted mode LOC22 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC23 (_PCNT_ROUTELOC0_S1INLOC_LOC23 << 8) /**< Shifted mode LOC23 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC24 (_PCNT_ROUTELOC0_S1INLOC_LOC24 << 8) /**< Shifted mode LOC24 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC25 (_PCNT_ROUTELOC0_S1INLOC_LOC25 << 8) /**< Shifted mode LOC25 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC26 (_PCNT_ROUTELOC0_S1INLOC_LOC26 << 8) /**< Shifted mode LOC26 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC27 (_PCNT_ROUTELOC0_S1INLOC_LOC27 << 8) /**< Shifted mode LOC27 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC28 (_PCNT_ROUTELOC0_S1INLOC_LOC28 << 8) /**< Shifted mode LOC28 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC29 (_PCNT_ROUTELOC0_S1INLOC_LOC29 << 8) /**< Shifted mode LOC29 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC30 (_PCNT_ROUTELOC0_S1INLOC_LOC30 << 8) /**< Shifted mode LOC30 for PCNT_ROUTELOC0 */
#define PCNT_ROUTELOC0_S1INLOC_LOC31 (_PCNT_ROUTELOC0_S1INLOC_LOC31 << 8) /**< Shifted mode LOC31 for PCNT_ROUTELOC0 */
/* Bit fields for PCNT FREEZE */
#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
/* Bit fields for PCNT SYNCBUSY */
#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */
#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */
#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */
#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */
#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
/* Bit fields for PCNT AUXCNT */
#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
/* Bit fields for PCNT INPUT */
#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */
#define _PCNT_INPUT_MASK 0x00000BEFUL /**< Mask for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */
#define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */
#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */
#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */
#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */
#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */
#define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */
#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */
#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */
#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */
#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */
/* Bit fields for PCNT OVSCFG */
#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */
#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */
#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
/** @} End of group EFM32PG12B_PCNT */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_prs_ch.h
* @brief EFM32PG12B_PRS_CH register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief PRS_CH EFM32PG12B PRS CH
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Channel Control Register */
} PRS_CH_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_prs_signals.h
* @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @addtogroup EFM32PG12B_PRS_Signals
* @{
* @brief PRS Signal names
*****************************************************************************/
#define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */
#define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */
#define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */
#define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */
#define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */
#define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */
#define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */
#define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */
#define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */
#define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */
#define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */
#define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */
#define PRS_ACMP0_OUT ((3 << 8) + 0) /**< PRS Analog comparator output */
#define PRS_ACMP1_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */
#define PRS_ADC0_SINGLE ((5 << 8) + 0) /**< PRS ADC single conversion done */
#define PRS_ADC0_SCAN ((5 << 8) + 1) /**< PRS ADC scan conversion done */
#define PRS_LESENSE_SCANRES0 ((7 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
#define PRS_LESENSE_SCANRES1 ((7 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
#define PRS_LESENSE_SCANRES2 ((7 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
#define PRS_LESENSE_SCANRES3 ((7 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
#define PRS_LESENSE_SCANRES4 ((7 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
#define PRS_LESENSE_SCANRES5 ((7 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
#define PRS_LESENSE_SCANRES6 ((7 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
#define PRS_LESENSE_SCANRES7 ((7 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
#define PRS_LESENSE_SCANRES8 ((8 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
#define PRS_LESENSE_SCANRES9 ((8 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
#define PRS_LESENSE_SCANRES10 ((8 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
#define PRS_LESENSE_SCANRES11 ((8 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
#define PRS_LESENSE_SCANRES12 ((8 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
#define PRS_LESENSE_SCANRES13 ((8 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
#define PRS_LESENSE_SCANRES14 ((8 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
#define PRS_LESENSE_SCANRES15 ((8 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
#define PRS_LESENSE_DEC0 ((9 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */
#define PRS_LESENSE_DEC1 ((9 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */
#define PRS_LESENSE_DEC2 ((9 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */
#define PRS_LESENSE_DECCMP ((9 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */
#define PRS_LESENSE_MEASACT ((10 << 8) + 0) /**< PRS LESENSE Measurement active */
#define PRS_RTCC_CCV0 ((11 << 8) + 1) /**< PRS RTCC Compare 0 */
#define PRS_RTCC_CCV1 ((11 << 8) + 2) /**< PRS RTCC Compare 1 */
#define PRS_RTCC_CCV2 ((11 << 8) + 3) /**< PRS RTCC Compare 2 */
#define PRS_GPIO_PIN0 ((12 << 8) + 0) /**< PRS GPIO pin 0 */
#define PRS_GPIO_PIN1 ((12 << 8) + 1) /**< PRS GPIO pin 1 */
#define PRS_GPIO_PIN2 ((12 << 8) + 2) /**< PRS GPIO pin 2 */
#define PRS_GPIO_PIN3 ((12 << 8) + 3) /**< PRS GPIO pin 3 */
#define PRS_GPIO_PIN4 ((12 << 8) + 4) /**< PRS GPIO pin 4 */
#define PRS_GPIO_PIN5 ((12 << 8) + 5) /**< PRS GPIO pin 5 */
#define PRS_GPIO_PIN6 ((12 << 8) + 6) /**< PRS GPIO pin 6 */
#define PRS_GPIO_PIN7 ((12 << 8) + 7) /**< PRS GPIO pin 7 */
#define PRS_GPIO_PIN8 ((13 << 8) + 0) /**< PRS GPIO pin 8 */
#define PRS_GPIO_PIN9 ((13 << 8) + 1) /**< PRS GPIO pin 9 */
#define PRS_GPIO_PIN10 ((13 << 8) + 2) /**< PRS GPIO pin 10 */
#define PRS_GPIO_PIN11 ((13 << 8) + 3) /**< PRS GPIO pin 11 */
#define PRS_GPIO_PIN12 ((13 << 8) + 4) /**< PRS GPIO pin 12 */
#define PRS_GPIO_PIN13 ((13 << 8) + 5) /**< PRS GPIO pin 13 */
#define PRS_GPIO_PIN14 ((13 << 8) + 6) /**< PRS GPIO pin 14 */
#define PRS_GPIO_PIN15 ((13 << 8) + 7) /**< PRS GPIO pin 15 */
#define PRS_LETIMER0_CH0 ((14 << 8) + 0) /**< PRS LETIMER CH0 Out */
#define PRS_LETIMER0_CH1 ((14 << 8) + 1) /**< PRS LETIMER CH1 Out */
#define PRS_PCNT0_TCC ((15 << 8) + 0) /**< PRS PCNT0 Triggered compare match */
#define PRS_PCNT0_UFOF ((15 << 8) + 1) /**< PRS PCNT0 Counter overflow or underflow */
#define PRS_PCNT0_DIR ((15 << 8) + 2) /**< PRS PCNT0 Counter direction */
#define PRS_PCNT1_TCC ((16 << 8) + 0) /**< PRS PCNT1 Triggered compare match */
#define PRS_PCNT1_UFOF ((16 << 8) + 1) /**< PRS PCNT1 Counter overflow or underflow */
#define PRS_PCNT1_DIR ((16 << 8) + 2) /**< PRS PCNT1 Counter direction */
#define PRS_PCNT2_TCC ((17 << 8) + 0) /**< PRS PCNT2 Triggered compare match */
#define PRS_PCNT2_UFOF ((17 << 8) + 1) /**< PRS PCNT2 Counter overflow or underflow */
#define PRS_PCNT2_DIR ((17 << 8) + 2) /**< PRS PCNT2 Counter direction */
#define PRS_CMU_CLKOUT0 ((18 << 8) + 0) /**< PRS Clock Output 0 */
#define PRS_CMU_CLKOUT1 ((18 << 8) + 1) /**< PRS Clock Output 1 */
#define PRS_VDAC0_CH0 ((24 << 8) + 0) /**< PRS DAC ch0 conversion done */
#define PRS_VDAC0_CH1 ((24 << 8) + 1) /**< PRS DAC ch1 conversion done */
#define PRS_VDAC0_OPA0 ((24 << 8) + 2) /**< PRS OPA0 warmedup or outputvalid based on OPA0PRSOUTMODE mode in OPACTRL. */
#define PRS_VDAC0_OPA1 ((24 << 8) + 3) /**< PRS OPA1 warmedup or outputvalid based on OPA1PRSOUTMODE mode in OPACTRL. */
#define PRS_VDAC0_OPA2 ((24 << 8) + 4) /**< PRS OPA2 warmedup or outputvalid based on OPA2PRSOUTMODE mode in OPACTRL. */
#define PRS_CRYOTIMER_PERIOD ((26 << 8) + 0) /**< PRS CRYOTIMER Output */
#define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS USART 0 IRDA out */
#define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS USART 0 TX complete */
#define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS USART 0 RX Data Valid */
#define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS USART 0 RTS */
#define PRS_USART0_TX ((48 << 8) + 5) /**< PRS USART 0 TX */
#define PRS_USART0_CS ((48 << 8) + 6) /**< PRS USART 0 CS */
#define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS USART 1 TX complete */
#define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS USART 1 RX Data Valid */
#define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS USART 1 RTS */
#define PRS_USART1_TX ((49 << 8) + 5) /**< PRS USART 1 TX */
#define PRS_USART1_CS ((49 << 8) + 6) /**< PRS USART 1 CS */
#define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */
#define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS USART 2 TX complete */
#define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS USART 2 RX Data Valid */
#define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS USART 2 RTS */
#define PRS_USART2_TX ((50 << 8) + 5) /**< PRS USART 2 TX */
#define PRS_USART2_CS ((50 << 8) + 6) /**< PRS USART 2 CS */
#define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS USART 3 TX complete */
#define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS USART 3 RX Data Valid */
#define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS USART 3 RTS */
#define PRS_USART3_TX ((51 << 8) + 5) /**< PRS USART 3 TX */
#define PRS_USART3_CS ((51 << 8) + 6) /**< PRS USART 3 CS */
#define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS Timer 0 Underflow */
#define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS Timer 0 Overflow */
#define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */
#define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */
#define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */
#define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS Timer 1 Underflow */
#define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS Timer 1 Overflow */
#define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */
#define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */
#define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */
#define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */
#define PRS_WTIMER0_UF ((62 << 8) + 0) /**< PRS Timer 2 Underflow */
#define PRS_WTIMER0_OF ((62 << 8) + 1) /**< PRS Timer 2 Overflow */
#define PRS_WTIMER0_CC0 ((62 << 8) + 2) /**< PRS Timer 2 Compare/Capture 0 */
#define PRS_WTIMER0_CC1 ((62 << 8) + 3) /**< PRS Timer 2 Compare/Capture 1 */
#define PRS_WTIMER0_CC2 ((62 << 8) + 4) /**< PRS Timer 2 Compare/Capture 2 */
#define PRS_WTIMER1_UF ((63 << 8) + 0) /**< PRS Timer 3 Underflow */
#define PRS_WTIMER1_OF ((63 << 8) + 1) /**< PRS Timer 3 Overflow */
#define PRS_WTIMER1_CC0 ((63 << 8) + 2) /**< PRS Timer 3 Compare/Capture 0 */
#define PRS_WTIMER1_CC1 ((63 << 8) + 3) /**< PRS Timer 3 Compare/Capture 1 */
#define PRS_WTIMER1_CC2 ((63 << 8) + 4) /**< PRS Timer 3 Compare/Capture 2 */
#define PRS_WTIMER1_CC3 ((63 << 8) + 5) /**< PRS Timer 3 Compare/Capture 3 */
#define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */
#define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */
#define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */
/** @} End of group EFM32PG12B_PRS */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_rmu.h
* @brief EFM32PG12B_RMU register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_RMU
* @{
* @brief EFM32PG12B_RMU Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IM uint32_t RSTCAUSE; /**< Reset Cause Register */
__IOM uint32_t CMD; /**< Command Register */
__IOM uint32_t RST; /**< Reset Control Register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
} RMU_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_RMU_BitFields
* @{
*****************************************************************************/
/* Bit fields for RMU CTRL */
#define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */
#define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */
#define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */
#define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */
#define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
#define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
#define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
#define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
#define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
#define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */
#define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */
#define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */
#define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */
#define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */
#define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */
#define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
#define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
#define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
#define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
#define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
#define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */
#define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */
#define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */
#define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */
#define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */
#define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */
#define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
#define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
#define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */
#define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
#define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
#define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */
#define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */
#define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */
#define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */
#define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */
#define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */
#define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
#define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
#define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
#define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
#define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
#define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */
#define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */
#define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */
#define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */
#define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */
#define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */
#define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */
/* Bit fields for RMU RSTCAUSE */
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
#define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */
#define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */
#define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */
#define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */
#define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */
#define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */
#define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */
#define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */
#define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */
#define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */
#define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */
#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */
#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */
#define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */
#define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
/* Bit fields for RMU CMD */
#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
/* Bit fields for RMU RST */
#define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */
#define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */
/* Bit fields for RMU LOCK */
#define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */
#define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
#define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
#define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
#define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
/** @} End of group EFM32PG12B_RMU */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_romtable.h
* @brief EFM32PG12B_ROMTABLE register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_ROMTABLE
* @{
* @brief Chip Information, Revision numbers
*****************************************************************************/
typedef struct
{
__IM uint32_t PID4; /**< JEP_106_BANK */
__IM uint32_t PID5; /**< Unused */
__IM uint32_t PID6; /**< Unused */
__IM uint32_t PID7; /**< Unused */
__IM uint32_t PID0; /**< Chip family LSB, chip major revision */
__IM uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
__IM uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
__IM uint32_t PID3; /**< Chip minor rev LSB */
__IM uint32_t CID0; /**< Unused */
} ROMTABLE_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_ROMTABLE_BitFields
* @{
*****************************************************************************/
/* Bit fields for EFM32PG12B_ROMTABLE */
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */
#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/** @} End of group EFM32PG12B_ROMTABLE */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_rtcc.h
* @brief EFM32PG12B_RTCC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_RTCC
* @{
* @brief EFM32PG12B_RTCC Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
__IOM uint32_t CNT; /**< Counter Value Register */
__IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
__IOM uint32_t TIME; /**< Time of day register */
__IOM uint32_t DATE; /**< Date register */
__IM uint32_t IF; /**< RTCC Interrupt Flags */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t STATUS; /**< Status register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
__IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */
__IOM uint32_t LOCK; /**< Configuration Lock Register */
__IOM uint32_t EM4WUEN; /**< Wake Up Enable */
RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
uint32_t RESERVED0[37]; /**< Reserved registers */
RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
} RTCC_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_RTCC_BitFields
* @{
*****************************************************************************/
/* Bit fields for RTCC CTRL */
#define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
#define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */
#define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */
#define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */
#define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */
#define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
#define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */
#define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
#define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */
#define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
#define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
#define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */
#define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
#define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
#define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */
#define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */
#define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */
#define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
#define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */
#define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */
#define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
#define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
#define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */
#define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
#define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
#define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */
#define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
#define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
#define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */
#define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
#define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
#define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */
#define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
#define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
#define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
#define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
/* Bit fields for RTCC PRECNT */
#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */
#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */
#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */
#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
/* Bit fields for RTCC CNT */
#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */
#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */
#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */
#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */
#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */
#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
/* Bit fields for RTCC COMBCNT */
#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */
#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */
#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */
#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */
#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
/* Bit fields for RTCC TIME */
#define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */
#define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */
#define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */
#define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */
#define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */
#define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */
#define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */
#define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */
#define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */
#define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */
#define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */
#define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */
#define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */
#define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */
#define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */
#define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */
#define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
#define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */
#define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */
#define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
#define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
/* Bit fields for RTCC DATE */
#define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */
#define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */
#define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */
#define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */
#define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */
#define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */
#define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */
#define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */
#define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */
#define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
#define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
#define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
#define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
#define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
#define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */
#define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */
#define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */
#define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */
#define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */
#define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */
#define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */
#define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */
#define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
#define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */
/* Bit fields for RTCC IF */
#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */
#define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */
#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */
#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */
#define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
#define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */
#define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
#define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */
#define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
#define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */
#define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
#define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
#define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */
#define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */
#define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
#define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
#define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */
#define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
#define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
#define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */
#define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
#define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
#define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */
#define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
#define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
#define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
#define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */
#define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
#define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
#define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
#define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
/* Bit fields for RTCC IFS */
#define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */
#define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */
#define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
#define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */
#define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
#define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */
#define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
#define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
#define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */
#define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
#define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
#define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */
#define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
#define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
#define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */
#define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
#define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
#define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */
#define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */
#define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
#define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
#define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */
#define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
#define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
#define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */
#define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
#define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
#define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */
#define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
#define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
#define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */
#define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
#define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
#define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
#define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
/* Bit fields for RTCC IFC */
#define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */
#define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */
#define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
#define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */
#define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
#define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */
#define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
#define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
#define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */
#define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
#define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
#define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */
#define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
#define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
#define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */
#define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
#define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
#define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */
#define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */
#define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
#define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
#define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */
#define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
#define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
#define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */
#define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
#define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
#define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */
#define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
#define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
#define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */
#define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
#define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
#define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
#define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
/* Bit fields for RTCC IEN */
#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */
#define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */
#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */
#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */
#define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
#define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */
#define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
#define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */
#define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
#define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */
#define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
#define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
#define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */
#define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
#define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */
#define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
#define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
#define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */
#define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
#define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
#define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */
#define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
#define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
#define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */
#define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
#define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
#define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */
#define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
#define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
#define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
#define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
/* Bit fields for RTCC STATUS */
#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */
#define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */
/* Bit fields for RTCC CMD */
#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
#define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
#define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */
#define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
#define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
#define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
#define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
/* Bit fields for RTCC SYNCBUSY */
#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */
#define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */
#define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */
#define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */
#define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */
#define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */
#define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
/* Bit fields for RTCC POWERDOWN */
#define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
#define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
#define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
#define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
#define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
#define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
#define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
/* Bit fields for RTCC LOCK */
#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */
#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
/* Bit fields for RTCC EM4WUEN */
#define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
#define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
#define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
#define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
#define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
#define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
#define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
/* Bit fields for RTCC CC_CTRL */
#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */
#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */
#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */
#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */
#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */
#define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */
#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */
#define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */
#define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */
#define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
#define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */
#define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
#define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */
#define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
#define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
#define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */
#define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */
#define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */
/* Bit fields for RTCC CC_CCV */
#define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */
#define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */
#define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */
#define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */
#define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */
#define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
/* Bit fields for RTCC CC_TIME */
#define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */
#define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */
#define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */
#define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */
#define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
#define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */
#define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */
#define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
#define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */
#define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */
#define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
#define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */
#define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */
#define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
#define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */
#define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */
#define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
#define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */
#define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */
#define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
#define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
/* Bit fields for RTCC CC_DATE */
#define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */
#define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */
#define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */
#define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */
#define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
#define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */
#define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */
#define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
#define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */
#define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
#define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
#define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
#define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
#define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
#define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
/* Bit fields for RTCC RET_REG */
#define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */
#define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */
#define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */
#define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */
#define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
#define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
/** @} End of group EFM32PG12B_RTCC */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_rtcc_cc.h
* @brief EFM32PG12B_RTCC_CC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief RTCC_CC EFM32PG12B RTCC CC
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< CC Channel Control Register */
__IOM uint32_t CCV; /**< Capture/Compare Value Register */
__IOM uint32_t TIME; /**< Capture/Compare Time Register */
__IOM uint32_t DATE; /**< Capture/Compare Date Register */
} RTCC_CC_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_rtcc_ret.h
* @brief EFM32PG12B_RTCC_RET register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief RTCC_RET EFM32PG12B RTCC RET
*****************************************************************************/
typedef struct
{
__IOM uint32_t REG; /**< Retention register */
} RTCC_RET_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_smu.h
* @brief EFM32PG12B_SMU register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_SMU
* @{
* @brief EFM32PG12B_SMU Register Declaration
*****************************************************************************/
typedef struct
{
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
uint32_t RESERVED1[9]; /**< Reserved for future use **/
__IOM uint32_t PPUCTRL; /**< PPU Control Register */
uint32_t RESERVED2[3]; /**< Reserved for future use **/
__IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */
__IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */
uint32_t RESERVED3[14]; /**< Reserved for future use **/
__IM uint32_t PPUFS; /**< PPU Fault Status */
} SMU_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_SMU_BitFields
* @{
*****************************************************************************/
/* Bit fields for SMU IF */
#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */
#define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */
#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */
#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */
#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */
/* Bit fields for SMU IFS */
#define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */
#define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */
#define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */
#define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
#define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
#define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */
#define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */
/* Bit fields for SMU IFC */
#define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */
#define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */
#define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */
#define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
#define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
#define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */
#define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */
/* Bit fields for SMU IEN */
#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */
#define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */
#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */
#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */
#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */
#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */
#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */
/* Bit fields for SMU PPUCTRL */
#define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */
#define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */
#define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */
#define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */
#define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */
#define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */
#define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */
/* Bit fields for SMU PPUPATD0 */
#define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */
#define _SMU_PPUPATD0_MASK 0x3BFF7FA7UL /**< Mask for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */
#define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */
#define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */
#define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */
#define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */
#define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */
#define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ADC0 (0x1UL << 2) /**< Analog to Digital Converter 0 access control bit */
#define _SMU_PPUPATD0_ADC0_SHIFT 2 /**< Shift value for SMU_ADC0 */
#define _SMU_PPUPATD0_ADC0_MASK 0x4UL /**< Bit mask for SMU_ADC0 */
#define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CMU (0x1UL << 5) /**< Clock Management Unit access control bit */
#define _SMU_PPUPATD0_CMU_SHIFT 5 /**< Shift value for SMU_CMU */
#define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */
#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */
#define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */
#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8) /**< Advanced Encryption Standard Accelerator 0 access control bit */
#define _SMU_PPUPATD0_CRYPTO0_SHIFT 8 /**< Shift value for SMU_CRYPTO0 */
#define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL /**< Bit mask for SMU_CRYPTO0 */
#define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9) /**< Advanced Encryption Standard Accelerator 1 access control bit */
#define _SMU_PPUPATD0_CRYPTO1_SHIFT 9 /**< Shift value for SMU_CRYPTO1 */
#define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL /**< Bit mask for SMU_CRYPTO1 */
#define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CSEN (0x1UL << 10) /**< Capacitive touch sense module access control bit */
#define _SMU_PPUPATD0_CSEN_SHIFT 10 /**< Shift value for SMU_CSEN */
#define _SMU_PPUPATD0_CSEN_MASK 0x400UL /**< Bit mask for SMU_CSEN */
#define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_VDAC0 (0x1UL << 11) /**< Digital to Analog Converter 0 access control bit */
#define _SMU_PPUPATD0_VDAC0_SHIFT 11 /**< Shift value for SMU_VDAC0 */
#define _SMU_PPUPATD0_VDAC0_MASK 0x800UL /**< Bit mask for SMU_VDAC0 */
#define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< Peripheral Reflex System access control bit */
#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */
#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */
#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_EMU (0x1UL << 13) /**< Energy Management Unit access control bit */
#define _SMU_PPUPATD0_EMU_SHIFT 13 /**< Shift value for SMU_EMU */
#define _SMU_PPUPATD0_EMU_MASK 0x2000UL /**< Bit mask for SMU_EMU */
#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_FPUEH (0x1UL << 14) /**< FPU Exception Handler access control bit */
#define _SMU_PPUPATD0_FPUEH_SHIFT 14 /**< Shift value for SMU_FPUEH */
#define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL /**< Bit mask for SMU_FPUEH */
#define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_GPCRC (0x1UL << 16) /**< General Purpose CRC access control bit */
#define _SMU_PPUPATD0_GPCRC_SHIFT 16 /**< Shift value for SMU_GPCRC */
#define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL /**< Bit mask for SMU_GPCRC */
#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_GPIO (0x1UL << 17) /**< General purpose Input/Output access control bit */
#define _SMU_PPUPATD0_GPIO_SHIFT 17 /**< Shift value for SMU_GPIO */
#define _SMU_PPUPATD0_GPIO_MASK 0x20000UL /**< Bit mask for SMU_GPIO */
#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_I2C0 (0x1UL << 18) /**< I2C 0 access control bit */
#define _SMU_PPUPATD0_I2C0_SHIFT 18 /**< Shift value for SMU_I2C0 */
#define _SMU_PPUPATD0_I2C0_MASK 0x40000UL /**< Bit mask for SMU_I2C0 */
#define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_I2C1 (0x1UL << 19) /**< I2C 1 access control bit */
#define _SMU_PPUPATD0_I2C1_SHIFT 19 /**< Shift value for SMU_I2C1 */
#define _SMU_PPUPATD0_I2C1_MASK 0x80000UL /**< Bit mask for SMU_I2C1 */
#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_IDAC0 (0x1UL << 20) /**< Current Digital to Analog Converter 0 access control bit */
#define _SMU_PPUPATD0_IDAC0_SHIFT 20 /**< Shift value for SMU_IDAC0 */
#define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL /**< Bit mask for SMU_IDAC0 */
#define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_MSC (0x1UL << 21) /**< Memory System Controller access control bit */
#define _SMU_PPUPATD0_MSC_SHIFT 21 /**< Shift value for SMU_MSC */
#define _SMU_PPUPATD0_MSC_MASK 0x200000UL /**< Bit mask for SMU_MSC */
#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LDMA (0x1UL << 22) /**< Linked Direct Memory Access Controller access control bit */
#define _SMU_PPUPATD0_LDMA_SHIFT 22 /**< Shift value for SMU_LDMA */
#define _SMU_PPUPATD0_LDMA_MASK 0x400000UL /**< Bit mask for SMU_LDMA */
#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LESENSE (0x1UL << 23) /**< Low Energy Sensor Interface access control bit */
#define _SMU_PPUPATD0_LESENSE_SHIFT 23 /**< Shift value for SMU_LESENSE */
#define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL /**< Bit mask for SMU_LESENSE */
#define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LETIMER0 (0x1UL << 24) /**< Low Energy Timer 0 access control bit */
#define _SMU_PPUPATD0_LETIMER0_SHIFT 24 /**< Shift value for SMU_LETIMER0 */
#define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL /**< Bit mask for SMU_LETIMER0 */
#define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LEUART0 (0x1UL << 25) /**< Low Energy UART 0 access control bit */
#define _SMU_PPUPATD0_LEUART0_SHIFT 25 /**< Shift value for SMU_LEUART0 */
#define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL /**< Bit mask for SMU_LEUART0 */
#define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT0 (0x1UL << 27) /**< Pulse Counter 0 access control bit */
#define _SMU_PPUPATD0_PCNT0_SHIFT 27 /**< Shift value for SMU_PCNT0 */
#define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL /**< Bit mask for SMU_PCNT0 */
#define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT1 (0x1UL << 28) /**< Pulse Counter 1 access control bit */
#define _SMU_PPUPATD0_PCNT1_SHIFT 28 /**< Shift value for SMU_PCNT1 */
#define _SMU_PPUPATD0_PCNT1_MASK 0x10000000UL /**< Bit mask for SMU_PCNT1 */
#define _SMU_PPUPATD0_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT1_DEFAULT (_SMU_PPUPATD0_PCNT1_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT2 (0x1UL << 29) /**< Pulse Counter 2 access control bit */
#define _SMU_PPUPATD0_PCNT2_SHIFT 29 /**< Shift value for SMU_PCNT2 */
#define _SMU_PPUPATD0_PCNT2_MASK 0x20000000UL /**< Bit mask for SMU_PCNT2 */
#define _SMU_PPUPATD0_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */
#define SMU_PPUPATD0_PCNT2_DEFAULT (_SMU_PPUPATD0_PCNT2_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
/* Bit fields for SMU PPUPATD1 */
#define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */
#define _SMU_PPUPATD1_MASK 0x0000FFEEUL /**< Mask for SMU_PPUPATD1 */
#define SMU_PPUPATD1_RMU (0x1UL << 1) /**< Reset Management Unit access control bit */
#define _SMU_PPUPATD1_RMU_SHIFT 1 /**< Shift value for SMU_RMU */
#define _SMU_PPUPATD1_RMU_MASK 0x2UL /**< Bit mask for SMU_RMU */
#define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_RTCC (0x1UL << 2) /**< Real-Time Counter and Calendar access control bit */
#define _SMU_PPUPATD1_RTCC_SHIFT 2 /**< Shift value for SMU_RTCC */
#define _SMU_PPUPATD1_RTCC_MASK 0x4UL /**< Bit mask for SMU_RTCC */
#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< Security Management Unit access control bit */
#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */
#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */
#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TIMER0 (0x1UL << 5) /**< Timer 0 access control bit */
#define _SMU_PPUPATD1_TIMER0_SHIFT 5 /**< Shift value for SMU_TIMER0 */
#define _SMU_PPUPATD1_TIMER0_MASK 0x20UL /**< Bit mask for SMU_TIMER0 */
#define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TIMER1 (0x1UL << 6) /**< Timer 1 access control bit */
#define _SMU_PPUPATD1_TIMER1_SHIFT 6 /**< Shift value for SMU_TIMER1 */
#define _SMU_PPUPATD1_TIMER1_MASK 0x40UL /**< Bit mask for SMU_TIMER1 */
#define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TRNG0 (0x1UL << 7) /**< True Random Number Generator 0 access control bit */
#define _SMU_PPUPATD1_TRNG0_SHIFT 7 /**< Shift value for SMU_TRNG0 */
#define _SMU_PPUPATD1_TRNG0_MASK 0x80UL /**< Bit mask for SMU_TRNG0 */
#define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART0 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */
#define _SMU_PPUPATD1_USART0_SHIFT 8 /**< Shift value for SMU_USART0 */
#define _SMU_PPUPATD1_USART0_MASK 0x100UL /**< Bit mask for SMU_USART0 */
#define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART1 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */
#define _SMU_PPUPATD1_USART1_SHIFT 9 /**< Shift value for SMU_USART1 */
#define _SMU_PPUPATD1_USART1_MASK 0x200UL /**< Bit mask for SMU_USART1 */
#define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART2 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */
#define _SMU_PPUPATD1_USART2_SHIFT 10 /**< Shift value for SMU_USART2 */
#define _SMU_PPUPATD1_USART2_MASK 0x400UL /**< Bit mask for SMU_USART2 */
#define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART3 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */
#define _SMU_PPUPATD1_USART3_SHIFT 11 /**< Shift value for SMU_USART3 */
#define _SMU_PPUPATD1_USART3_MASK 0x800UL /**< Bit mask for SMU_USART3 */
#define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WDOG0 (0x1UL << 12) /**< Watchdog 0 access control bit */
#define _SMU_PPUPATD1_WDOG0_SHIFT 12 /**< Shift value for SMU_WDOG0 */
#define _SMU_PPUPATD1_WDOG0_MASK 0x1000UL /**< Bit mask for SMU_WDOG0 */
#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WDOG1 (0x1UL << 13) /**< Watchdog 1 access control bit */
#define _SMU_PPUPATD1_WDOG1_SHIFT 13 /**< Shift value for SMU_WDOG1 */
#define _SMU_PPUPATD1_WDOG1_MASK 0x2000UL /**< Bit mask for SMU_WDOG1 */
#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WTIMER0 (0x1UL << 14) /**< Wide Timer 0 access control bit */
#define _SMU_PPUPATD1_WTIMER0_SHIFT 14 /**< Shift value for SMU_WTIMER0 */
#define _SMU_PPUPATD1_WTIMER0_MASK 0x4000UL /**< Bit mask for SMU_WTIMER0 */
#define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WTIMER1 (0x1UL << 15) /**< Wide Timer 1 access control bit */
#define _SMU_PPUPATD1_WTIMER1_SHIFT 15 /**< Shift value for SMU_WTIMER1 */
#define _SMU_PPUPATD1_WTIMER1_MASK 0x8000UL /**< Bit mask for SMU_WTIMER1 */
#define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */
#define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
/* Bit fields for SMU PPUFS */
#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */
#define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */
#define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */
#define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL /**< Mode ADC0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL /**< Mode CMU for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL /**< Mode CRYOTIMER for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL /**< Mode CRYPTO0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL /**< Mode CRYPTO1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL /**< Mode CSEN for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL /**< Mode VDAC0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL /**< Mode PRS for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL /**< Mode EMU for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL /**< Mode FPUEH for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL /**< Mode GPCRC for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL /**< Mode GPIO for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL /**< Mode I2C0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL /**< Mode I2C1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL /**< Mode IDAC0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL /**< Mode MSC for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL /**< Mode LDMA for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL /**< Mode LESENSE for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL /**< Mode LETIMER0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL /**< Mode LEUART0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL /**< Mode PCNT0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_PCNT1 0x0000001CUL /**< Mode PCNT1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_PCNT2 0x0000001DUL /**< Mode PCNT2 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_RMU 0x00000021UL /**< Mode RMU for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_RTCC 0x00000022UL /**< Mode RTCC for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_SMU 0x00000023UL /**< Mode SMU for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_TIMER0 0x00000025UL /**< Mode TIMER0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_TIMER1 0x00000026UL /**< Mode TIMER1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_USART0 0x00000028UL /**< Mode USART0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_USART1 0x00000029UL /**< Mode USART1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_USART2 0x0000002AUL /**< Mode USART2 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_USART3 0x0000002BUL /**< Mode USART3 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002CUL /**< Mode WDOG0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002DUL /**< Mode WDOG1 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002EUL /**< Mode WTIMER0 for SMU_PPUFS */
#define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000002FUL /**< Mode WTIMER1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0) /**< Shifted mode CRYPTO1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */
#define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */
/** @} End of group EFM32PG12B_SMU */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_timer_cc.h
* @brief EFM32PG12B_TIMER_CC register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief TIMER_CC EFM32PG12B TIMER CC
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< CC Channel Control Register */
__IOM uint32_t CCV; /**< CC Channel Value Register */
__IM uint32_t CCVP; /**< CC Channel Value Peek Register */
__IOM uint32_t CCVB; /**< CC Channel Buffer Register */
} TIMER_CC_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_trng.h
* @brief EFM32PG12B_TRNG register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_TRNG
* @{
* @brief EFM32PG12B_TRNG Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CONTROL; /**< Main Control Register */
__IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
uint32_t RESERVED0[1]; /**< Reserved for future use **/
__IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
__IOM uint32_t KEY0; /**< Key Register 0 */
__IOM uint32_t KEY1; /**< Key Register 1 */
__IOM uint32_t KEY2; /**< Key Register 2 */
__IOM uint32_t KEY3; /**< Key Register 3 */
__IOM uint32_t TESTDATA; /**< Test Data Register */
uint32_t RESERVED1[3]; /**< Reserved for future use **/
__IOM uint32_t STATUS; /**< Status Register */
__IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
uint32_t RESERVED2[50]; /**< Reserved for future use **/
__IM uint32_t FIFO; /**< FIFO Data */
} TRNG_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_TRNG_BitFields
* @{
*****************************************************************************/
/* Bit fields for TRNG CONTROL */
#define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */
#define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */
#define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */
#define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */
#define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */
#define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */
#define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */
#define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */
#define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */
#define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */
#define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */
#define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */
#define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */
#define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */
#define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */
#define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */
#define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */
#define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */
#define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
#define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */
#define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */
#define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */
#define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */
#define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */
#define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */
#define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */
#define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */
#define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */
#define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */
#define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */
#define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */
#define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */
#define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */
#define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */
#define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */
#define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
#define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */
#define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */
#define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */
#define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */
#define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */
#define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */
#define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */
#define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */
#define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */
#define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */
#define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */
#define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
#define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */
#define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */
#define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */
#define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */
#define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */
#define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
#define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
#define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */
#define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */
#define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */
#define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */
#define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
#define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
#define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
#define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */
#define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */
#define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */
/* Bit fields for TRNG FIFOLEVEL */
#define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */
#define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */
#define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */
#define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */
/* Bit fields for TRNG FIFODEPTH */
#define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */
#define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */
#define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */
#define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */
/* Bit fields for TRNG KEY0 */
#define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */
#define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */
#define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */
#define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */
/* Bit fields for TRNG KEY1 */
#define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */
#define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */
#define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */
#define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */
/* Bit fields for TRNG KEY2 */
#define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */
#define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */
#define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */
#define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */
/* Bit fields for TRNG KEY3 */
#define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */
#define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */
#define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */
#define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */
/* Bit fields for TRNG TESTDATA */
#define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */
#define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */
#define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */
#define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */
/* Bit fields for TRNG STATUS */
#define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */
#define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */
#define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */
#define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */
#define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */
#define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */
#define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */
#define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */
#define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */
#define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */
#define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */
#define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */
#define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */
#define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */
#define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */
#define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */
#define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */
#define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */
#define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */
#define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */
#define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */
#define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */
#define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */
#define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */
#define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */
#define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
#define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */
/* Bit fields for TRNG INITWAITVAL */
#define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */
#define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */
#define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */
#define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */
/* Bit fields for TRNG FIFO */
#define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */
#define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */
#define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
#define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
#define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */
#define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */
/** @} End of group EFM32PG12B_TRNG */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_vdac_opa.h
* @brief EFM32PG12B_VDAC_OPA register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief VDAC_OPA EFM32PG12B VDAC OPA
*****************************************************************************/
typedef struct
{
__IM uint32_t APORTREQ; /**< Operational Amplifier APORT Request Status Register */
__IM uint32_t APORTCONFLICT; /**< Operational Amplifier APORT Conflict Status Register */
__IOM uint32_t CTRL; /**< Operational Amplifier Control Register */
__IOM uint32_t TIMER; /**< Operational Amplifier Timer Control Register */
__IOM uint32_t MUX; /**< Operational Amplifier Mux Configuration Register */
__IOM uint32_t OUT; /**< Operational Amplifier Output Configuration Register */
__IOM uint32_t CAL; /**< Operational Amplifier Calibration Register */
uint32_t RESERVED0[1]; /**< Reserved future */
} VDAC_OPA_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_wdog.h
* @brief EFM32PG12B_WDOG register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32PG12B_WDOG
* @{
* @brief EFM32PG12B_WDOG Register Declaration
*****************************************************************************/
typedef struct
{
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
WDOG_PCH_TypeDef PCH[2]; /**< PCH */
uint32_t RESERVED0[2]; /**< Reserved for future use **/
__IM uint32_t IF; /**< Watchdog Interrupt Flags */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
} WDOG_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32PG12B_WDOG_BitFields
* @{
*****************************************************************************/
/* Bit fields for WDOG CTRL */
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
#define _WDOG_CTRL_MASK 0xC7033F7FUL /**< Mask for WDOG_CTRL */
#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_HFCORECLK 0x00000003UL /**< Mode HFCORECLK for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_HFCORECLK (_WDOG_CTRL_CLKSEL_HFCORECLK << 12) /**< Shifted mode HFCORECLK for WDOG_CTRL */
#define _WDOG_CTRL_WARNSEL_SHIFT 16 /**< Shift value for WDOG_WARNSEL */
#define _WDOG_CTRL_WARNSEL_MASK 0x30000UL /**< Bit mask for WDOG_WARNSEL */
#define _WDOG_CTRL_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_WARNSEL_DEFAULT (_WDOG_CTRL_WARNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_WINSEL_SHIFT 24 /**< Shift value for WDOG_WINSEL */
#define _WDOG_CTRL_WINSEL_MASK 0x7000000UL /**< Bit mask for WDOG_WINSEL */
#define _WDOG_CTRL_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_WINSEL_DEFAULT (_WDOG_CTRL_WINSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_CLRSRC (0x1UL << 30) /**< Watchdog Clear Source */
#define _WDOG_CTRL_CLRSRC_SHIFT 30 /**< Shift value for WDOG_CLRSRC */
#define _WDOG_CTRL_CLRSRC_MASK 0x40000000UL /**< Bit mask for WDOG_CLRSRC */
#define _WDOG_CTRL_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CTRL */
#define _WDOG_CTRL_CLRSRC_PCH0 0x00000001UL /**< Mode PCH0 for WDOG_CTRL */
#define WDOG_CTRL_CLRSRC_DEFAULT (_WDOG_CTRL_CLRSRC_DEFAULT << 30) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_CLRSRC_SW (_WDOG_CTRL_CLRSRC_SW << 30) /**< Shifted mode SW for WDOG_CTRL */
#define WDOG_CTRL_CLRSRC_PCH0 (_WDOG_CTRL_CLRSRC_PCH0 << 30) /**< Shifted mode PCH0 for WDOG_CTRL */
#define WDOG_CTRL_WDOGRSTDIS (0x1UL << 31) /**< Watchdog Reset Disable */
#define _WDOG_CTRL_WDOGRSTDIS_SHIFT 31 /**< Shift value for WDOG_WDOGRSTDIS */
#define _WDOG_CTRL_WDOGRSTDIS_MASK 0x80000000UL /**< Bit mask for WDOG_WDOGRSTDIS */
#define _WDOG_CTRL_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CTRL */
#define _WDOG_CTRL_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CTRL */
#define WDOG_CTRL_WDOGRSTDIS_DEFAULT (_WDOG_CTRL_WDOGRSTDIS_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_WDOGRSTDIS_EN (_WDOG_CTRL_WDOGRSTDIS_EN << 31) /**< Shifted mode EN for WDOG_CTRL */
#define WDOG_CTRL_WDOGRSTDIS_DIS (_WDOG_CTRL_WDOGRSTDIS_DIS << 31) /**< Shifted mode DIS for WDOG_CTRL */
/* Bit fields for WDOG CMD */
#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
/* Bit fields for WDOG SYNCBUSY */
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
#define _WDOG_SYNCBUSY_MASK 0x0000000FUL /**< Mask for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_PCH0_PRSCTRL (0x1UL << 2) /**< PCH0_PRSCTRL Register Busy */
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_SHIFT 2 /**< Shift value for WDOG_PCH0_PRSCTRL */
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_MASK 0x4UL /**< Bit mask for WDOG_PCH0_PRSCTRL */
#define _WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH0_PRSCTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_PCH1_PRSCTRL (0x1UL << 3) /**< PCH1_PRSCTRL Register Busy */
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_SHIFT 3 /**< Shift value for WDOG_PCH1_PRSCTRL */
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_MASK 0x8UL /**< Bit mask for WDOG_PCH1_PRSCTRL */
#define _WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT (_WDOG_SYNCBUSY_PCH1_PRSCTRL_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
/* Bit fields for WDOG PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_MASK 0x0000010FUL /**< Mask for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_SHIFT 0 /**< Shift value for WDOG_PRSSEL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_MASK 0xFUL /**< Bit mask for WDOG_PRSSEL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WDOG_PCH_PRSCTRL */
#define _WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT (_WDOG_PCH_PRSCTRL_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 (_WDOG_PCH_PRSCTRL_PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN (0x1UL << 8) /**< PRS missing event will trigger a watchdog reset */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_SHIFT 8 /**< Shift value for WDOG_PRSMISSRSTEN */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_MASK 0x100UL /**< Bit mask for WDOG_PRSMISSRSTEN */
#define _WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_PCH_PRSCTRL */
#define WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT (_WDOG_PCH_PRSCTRL_PRSMISSRSTEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_PCH_PRSCTRL */
/* Bit fields for WDOG IF */
#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */
#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */
#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */
#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */
#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */
#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Channel Zero Event Missing Interrupt Flag */
#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Channel One Event Missing Interrupt Flag */
#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */
#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */
/* Bit fields for WDOG IFS */
#define _WDOG_IFS_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFS */
#define _WDOG_IFS_MASK 0x0000001FUL /**< Mask for WDOG_IFS */
#define WDOG_IFS_TOUT (0x1UL << 0) /**< Set TOUT Interrupt Flag */
#define _WDOG_IFS_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IFS_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IFS_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_TOUT_DEFAULT (_WDOG_IFS_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_WARN (0x1UL << 1) /**< Set WARN Interrupt Flag */
#define _WDOG_IFS_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IFS_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IFS_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_WARN_DEFAULT (_WDOG_IFS_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_WIN (0x1UL << 2) /**< Set WIN Interrupt Flag */
#define _WDOG_IFS_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IFS_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IFS_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_WIN_DEFAULT (_WDOG_IFS_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_PEM0 (0x1UL << 3) /**< Set PEM0 Interrupt Flag */
#define _WDOG_IFS_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IFS_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IFS_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_PEM0_DEFAULT (_WDOG_IFS_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_PEM1 (0x1UL << 4) /**< Set PEM1 Interrupt Flag */
#define _WDOG_IFS_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IFS_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IFS_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFS */
#define WDOG_IFS_PEM1_DEFAULT (_WDOG_IFS_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFS */
/* Bit fields for WDOG IFC */
#define _WDOG_IFC_RESETVALUE 0x00000000UL /**< Default value for WDOG_IFC */
#define _WDOG_IFC_MASK 0x0000001FUL /**< Mask for WDOG_IFC */
#define WDOG_IFC_TOUT (0x1UL << 0) /**< Clear TOUT Interrupt Flag */
#define _WDOG_IFC_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IFC_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IFC_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_TOUT_DEFAULT (_WDOG_IFC_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_WARN (0x1UL << 1) /**< Clear WARN Interrupt Flag */
#define _WDOG_IFC_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IFC_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IFC_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_WARN_DEFAULT (_WDOG_IFC_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_WIN (0x1UL << 2) /**< Clear WIN Interrupt Flag */
#define _WDOG_IFC_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IFC_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IFC_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_WIN_DEFAULT (_WDOG_IFC_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_PEM0 (0x1UL << 3) /**< Clear PEM0 Interrupt Flag */
#define _WDOG_IFC_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IFC_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IFC_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_PEM0_DEFAULT (_WDOG_IFC_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_PEM1 (0x1UL << 4) /**< Clear PEM1 Interrupt Flag */
#define _WDOG_IFC_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IFC_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IFC_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IFC */
#define WDOG_IFC_PEM1_DEFAULT (_WDOG_IFC_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IFC */
/* Bit fields for WDOG IEN */
#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */
#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */
#define WDOG_IEN_TOUT (0x1UL << 0) /**< TOUT Interrupt Enable */
#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */
#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */
#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WARN (0x1UL << 1) /**< WARN Interrupt Enable */
#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */
#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */
#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WIN (0x1UL << 2) /**< WIN Interrupt Enable */
#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */
#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */
#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PEM0 Interrupt Enable */
#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */
#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */
#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PEM1 Interrupt Enable */
#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */
#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */
#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */
#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */
/** @} End of group EFM32PG12B_WDOG */
/** @} End of group Parts */

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/**************************************************************************//**
* @file efm32pg12b_wdog_pch.h
* @brief EFM32PG12B_WDOG_PCH register and bit field definitions
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief WDOG_PCH EFM32PG12B WDOG PCH
*****************************************************************************/
typedef struct
{
__IOM uint32_t PRSCTRL; /**< PRS Control Register */
} WDOG_PCH_TypeDef;
/** @} End of group Parts */

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/**************************************************************************//**
* @file em_device.h
* @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories
* microcontroller devices
*
* This is a convenience header file for defining the part number on the
* build command line, instead of specifying the part specific header file.
*
* @verbatim
* Example: Add "-DEFM32G890F128" to your build options, to define part
* Add "#include "em_device.h" to your source files
*
*
* @endverbatim
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef EM_DEVICE_H
#define EM_DEVICE_H
#if defined(EFM32PG12B500F1024GL125)
#include "efm32pg12b500f1024gl125.h"
#elif defined(EFM32PG12B500F1024GM48)
#include "efm32pg12b500f1024gm48.h"
#elif defined(EFM32PG12B500F1024IL125)
#include "efm32pg12b500f1024il125.h"
#elif defined(EFM32PG12B500F1024IM48)
#include "efm32pg12b500f1024im48.h"
#elif defined(EFM32PG12B500F512GL125)
#include "efm32pg12b500f512gl125.h"
#elif defined(EFM32PG12B500F512GM48)
#include "efm32pg12b500f512gm48.h"
#else
#error "em_device.h: PART NUMBER undefined"
#endif
#endif /* EM_DEVICE_H */

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/***************************************************************************//**
* @file system_efm32pg12b.h
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifndef SYSTEM_EFM32_H
#define SYSTEM_EFM32_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
/*******************************************************************************
***************************** PROTOTYPES **********************************
******************************************************************************/
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void EMU_IRQHandler(void);
void WDOG0_IRQHandler(void);
void LDMA_IRQHandler(void);
void GPIO_EVEN_IRQHandler(void);
void TIMER0_IRQHandler(void);
void USART0_RX_IRQHandler(void);
void USART0_TX_IRQHandler(void);
void ACMP0_IRQHandler(void);
void ADC0_IRQHandler(void);
void IDAC0_IRQHandler(void);
void I2C0_IRQHandler(void);
void GPIO_ODD_IRQHandler(void);
void TIMER1_IRQHandler(void);
void USART1_RX_IRQHandler(void);
void USART1_TX_IRQHandler(void);
void LEUART0_IRQHandler(void);
void PCNT0_IRQHandler(void);
void CMU_IRQHandler(void);
void MSC_IRQHandler(void);
void LETIMER0_IRQHandler(void);
void RTCC_IRQHandler(void);
void CRYOTIMER_IRQHandler(void);
#if (__FPU_PRESENT == 1)
void FPUEH_IRQHandler(void);
#endif
uint32_t SystemCoreClockGet(void);
/**************************************************************************//**
* @brief
* Update CMSIS SystemCoreClock variable.
*
* @details
* CMSIS defines a global variable SystemCoreClock that shall hold the
* core frequency in Hz. If the core frequency is dynamically changed, the
* variable must be kept updated in order to be CMSIS compliant.
*
* Notice that only if changing the core clock frequency through the EFM CMU
* API, this variable will be kept updated. This function is only provided
* for CMSIS compliance and if a user modifies the the core clock outside
* the CMU API.
*****************************************************************************/
static __INLINE void SystemCoreClockUpdate(void)
{
SystemCoreClockGet();
}
uint32_t SystemMaxCoreClockGet(void);
void SystemInit(void);
uint32_t SystemHFClockGet(void);
uint32_t SystemHFXOClockGet(void);
void SystemHFXOClockSet(uint32_t freq);
uint32_t SystemLFRCOClockGet(void);
uint32_t SystemULFRCOClockGet(void);
uint32_t SystemLFXOClockGet(void);
void SystemLFXOClockSet(uint32_t freq);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_EFM32_H */

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/***************************************************************************//**
* @file system_efm32pg12b.c
* @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices.
* @version 5.1.2
******************************************************************************
* @section License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#include <stdint.h>
#include "em_device.h"
/*******************************************************************************
****************************** DEFINES ************************************
******************************************************************************/
/** LFRCO frequency, tuned to below frequency during manufacturing. */
#define EFM32_LFRCO_FREQ (32768UL)
#define EFM32_ULFRCO_FREQ (1000UL)
/*******************************************************************************
************************** LOCAL VARIABLES ********************************
******************************************************************************/
/* System oscillator frequencies. These frequencies are normally constant */
/* for a target, but they are made configurable in order to allow run-time */
/* handling of different boards. The crystal oscillator clocks can be set */
/* compile time to a non-default value by defining respective EFM_nFXO_FREQ */
/* values according to board design. By defining the EFM_nFXO_FREQ to 0, */
/* one indicates that the oscillator is not present, in order to save some */
/* SW footprint. */
#ifndef EFM32_HFRCO_MAX_FREQ
#define EFM32_HFRCO_MAX_FREQ (38000000UL)
#endif
#ifndef EFM32_HFXO_FREQ
#define EFM32_HFXO_FREQ (40000000UL)
#endif
#ifndef EFM32_HFRCO_STARTUP_FREQ
#define EFM32_HFRCO_STARTUP_FREQ (19000000UL)
#endif
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0UL)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0UL)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = 32768UL;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
/*******************************************************************************
************************** GLOBAL VARIABLES *******************************
******************************************************************************/
/**
* @brief
* System System Clock Frequency (Core Clock).
*
* @details
* Required CMSIS global variable that must be kept up-to-date.
*/
uint32_t SystemCoreClock;
/**
* @brief
* System HFRCO frequency
*
* @note
* This is an EFM32 proprietary variable, not part of the CMSIS definition.
*
* @details
* Frequency of the system HFRCO oscillator
*/
uint32_t SystemHfrcoFreq = EFM32_HFRCO_STARTUP_FREQ;
/*******************************************************************************
************************** GLOBAL FUNCTIONS *******************************
******************************************************************************/
/***************************************************************************//**
* @brief
* Get the current core clock frequency.
*
* @details
* Calculate and get the current core clock frequency based on the current
* configuration. Assuming that the SystemCoreClock global variable is
* maintained, the core clock frequency is stored in that variable as well.
* This function will however calculate the core clock based on actual HW
* configuration. It will also update the SystemCoreClock global variable.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current core clock frequency in Hz.
******************************************************************************/
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
uint32_t presc;
ret = SystemHFClockGet();
presc = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) >>
_CMU_HFCOREPRESC_PRESC_SHIFT;
ret /= (presc + 1);
/* Keep CMSIS system clock variable up-to-date */
SystemCoreClock = ret;
return ret;
}
/***************************************************************************//**
* @brief
* Get the maximum core clock frequency.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The maximum core clock frequency in Hz.
******************************************************************************/
uint32_t SystemMaxCoreClockGet(void)
{
return (EFM32_HFRCO_MAX_FREQ > EFM32_HFXO_FREQ ? \
EFM32_HFRCO_MAX_FREQ : EFM32_HFXO_FREQ);
}
/***************************************************************************//**
* @brief
* Get the current HFCLK frequency.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* The current HFCLK frequency in Hz.
******************************************************************************/
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK)
{
case CMU_HFCLKSTATUS_SELECTED_LFXO:
#if (EFM32_LFXO_FREQ > 0)
ret = SystemLFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
case CMU_HFCLKSTATUS_SELECTED_LFRCO:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_HFCLKSTATUS_SELECTED_HFXO:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
#else
/* We should not get here, since core should not be clocked. May */
/* be caused by a misconfiguration though. */
ret = 0;
#endif
break;
default: /* CMU_HFCLKSTATUS_SELECTED_HFRCO */
ret = SystemHfrcoFreq;
break;
}
return ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
>> _CMU_HFPRESC_PRESC_SHIFT));
}
/**************************************************************************//**
* @brief
* Get high frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* HFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemHFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
return SystemHFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set high frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* HFXO frequency in Hz used for target.
*****************************************************************************/
void SystemHFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_HFXO_FREQ > 0)
SystemHFXOClock = freq;
/* Update core clock frequency if HFXO is used to clock core */
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_HFXO)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}
/**************************************************************************//**
* @brief
* Initialize the system.
*
* @details
* Do required generic HW system init.
*
* @note
* This function is invoked during system init, before the main() routine
* and any data has been initialized. For this reason, it cannot do any
* initialization of variables etc.
*****************************************************************************/
void SystemInit(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Set floating point coprosessor access mode. */
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
}
/**************************************************************************//**
* @brief
* Get low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFRCOClockGet(void)
{
/* Currently we assume that this frequency is properly tuned during */
/* manufacturing and is not changed after reset. If future requirements */
/* for re-tuning by user, we can add support for that. */
return EFM32_LFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get ultra low frequency RC oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* ULFRCO frequency in Hz.
*****************************************************************************/
uint32_t SystemULFRCOClockGet(void)
{
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
return EFM32_ULFRCO_FREQ;
}
/**************************************************************************//**
* @brief
* Get low frequency crystal oscillator clock frequency for target system.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @return
* LFXO frequency in Hz.
*****************************************************************************/
uint32_t SystemLFXOClockGet(void)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
return SystemLFXOClock;
#else
return 0;
#endif
}
/**************************************************************************//**
* @brief
* Set low frequency crystal oscillator clock frequency for target system.
*
* @note
* This function is mainly provided for being able to handle target systems
* with different HF crystal oscillator frequencies run-time. If used, it
* should probably only be used once during system startup.
*
* @note
* This is an EFM32 proprietary function, not part of the CMSIS definition.
*
* @param[in] freq
* LFXO frequency in Hz used for target.
*****************************************************************************/
void SystemLFXOClockSet(uint32_t freq)
{
/* External crystal oscillator present? */
#if (EFM32_LFXO_FREQ > 0)
SystemLFXOClock = freq;
/* Update core clock frequency if LFXO is used to clock core */
if ((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) == CMU_HFCLKSTATUS_SELECTED_LFXO)
{
/* The function will update the global variable */
SystemCoreClockGet();
}
#else
(void)freq; /* Unused parameter */
#endif
}

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Silabs Gecko SDK
----------------
Silicon Labs Gecko HAL
######################
Origin:
Silicon Labs Gecko SDK
https://github.com/SiliconLabs/Gecko_SDK
Version:
v5.1.2
Purpose:
Add support for Silicon Labs EXX32 SoCs
Description:
This code component is used to add Zephyr support for Silicon Labs EXX32 SoCs.
To speed up the development process it is based on the Silicon Labs HAL.
The Silicon Labs HAL is split into SoC specific folders. They share the
Peripheral Support library.
The following folders are imported:
platform/Device/SiliconLabs/$(GECKO_DEVICE)
platform/emlib
Dependencies:
This source code depends on headers and sources from Zephyr:
ext/hal/cmsis
URL:
https://github.com/SiliconLabs/Gecko_SDK
commit:
938464c68e6c3b2237388a692f767bb0767ec010
Maintained-by:
External
License:
Zlib
License Link:
https://github.com/SiliconLabs/Gecko_SDK/blob/e8c70a3d4fda8ee09688d6c6cf2a2bafc5f649e9/platform/emlib/ReadMe_emlib.txt#L51-L54
https://github.com/SiliconLabs/Gecko_SDK/blob/e8c70a3d4fda8ee09688d6c6cf2a2bafc5f649e9/platform/Device/ReadMe-Device.txt#L91
Downloaded from https://github.com/SiliconLabs/Gecko_SDK
How to update
+++++++++++++
@ -9,7 +49,7 @@ How to update
* Downloaded current version from https://github.com/SiliconLabs/Gecko_SDK
* Extract
* Replace the necessary files in ext/hal/silabs/gecko/Device and ext/hal/silabs/gecko/emlib
* Ensure that the Makfile and Kbuild-file match the new version of the Gecko SDK
* Ensure that the CMakeLists and Kconfig files match the new version of the Gecko SDK
The following folders are used in this HAL: