soc: arm64: Add MMU table for Intel SoC FPGA Agilex

Add MMU table for Intel SoC FPGA Agilex initial bring up.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

soc/arm64/intel_socfpga/agilex/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex

@@ -0,0 +1,22 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_AGILEX
+
+config SOC
+	default "intel_socfpga_agilex"
+
+# must be >= the highest interrupt number used
+# - include the UART interrupts 173 or 204
+config NUM_IRQS
+	int
+	default 205
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 25000000
+
+config KERNEL_VM_SIZE
+	default 0x40000
+
+endif

soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_AGILEX
+
+config SOC_SERIES
+	default "agilex"
+
+source "soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex*"
+
+endif # SOC_SERIES_AGILEX

soc/arm64/intel_socfpga/agilex/Kconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_AGILEX
+	bool "Intel SoC FPGA Agilex Series"
+	select ARM64
+	select CPU_CORTEX_A53
+	select GIC_V2
+	select SOC_FAMILY_INTEL_SOCFPGA
+	help
+		Enable support for Intel SoC FPGA Series

soc/arm64/intel_socfpga/agilex/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "Intel SoC FPGA Agilex"
+depends on SOC_SERIES_AGILEX
+
+config SOC_AGILEX
+	bool "Intel SoC FPGA Agilex"
+endchoice

soc/arm64/intel_socfpga/agilex/linker.ld

@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <arch/arm64/scripts/linker.ld>

soc/arm64/intel_socfpga/agilex/mmu_regions.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/cpu.h>
+#include <arch/arm64/arm_mmu.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+
+	/* System manager register that required by clock driver */
+	MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
+			      DT_REG_ADDR(DT_NODELABEL(sysmgr)),
+			      DT_REG_SIZE(DT_NODELABEL(sysmgr)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("CLOCK",
+			      DT_REG_ADDR(DT_NODELABEL(clock)),
+			      DT_REG_SIZE(DT_NODELABEL(clock)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("UART0",
+			      DT_REG_ADDR(DT_NODELABEL(uart0)),
+			      DT_REG_SIZE(DT_NODELABEL(uart0)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/arm64/intel_socfpga/agilex/soc.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2021, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_H_
+#define _SOC_H_
+
+/* FPGA config helpers */
+#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR		0x400000
+#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE		0x2000000
+
+/* Register Mapping */
+#define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
+
+#define SOCFPGA_MMC_REG_BASE			0xff808000
+
+#define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE             0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE             0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE           0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE         0xffd21300
+
+#endif /* _SOC_H_ */