drivers: add CC13xx / CC26xx SPI driver
Add driver for the SPI peripheral on the TI CC13xx / CC26xx series SoCs. Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
This commit is contained in:
Brett Witherspoon
Anas Nashif
parent
8d6346ef65
commit
f2eea2ef85
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@ -2,6 +2,7 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_SPI_CC13XX_CC26XX spi_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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@ -204,4 +204,6 @@ source "drivers/spi/Kconfig.sifive"
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source "drivers/spi/Kconfig.nrfx"
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source "drivers/spi/Kconfig.cc13xx_cc26xx"
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endif # SPI
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12
drivers/spi/Kconfig.cc13xx_cc26xx
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12
drivers/spi/Kconfig.cc13xx_cc26xx
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@ -0,0 +1,12 @@
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# Kconfig.spi_cc13xx_cc26xx - TI CC13xx / CC26xx SPI configuration options
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#
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# Copyright (c) 2019 Brett Witherspoon
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SPI_CC13XX_CC26XX
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bool "TI SimpleLink CC13xx / CC26xx SPI driver"
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depends on SOC_SERIES_CC13X2_CC26X2
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help
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Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral
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306
drivers/spi/spi_cc13xx_cc26xx.c
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306
drivers/spi/spi_cc13xx_cc26xx.c
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@ -0,0 +1,306 @@
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/*
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* Copyright (c) 2019 Brett Witherspoon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_cc13xx_cc26xx);
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#include <spi.h>
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#include <sys_clock.h>
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#include <driverlib/prcm.h>
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#include <driverlib/ssi.h>
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#include <driverlib/ioc.h>
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#include "spi_context.h"
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struct spi_cc13xx_cc26xx_config {
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u32_t base;
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u32_t sck_pin;
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u32_t mosi_pin;
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u32_t miso_pin;
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u32_t cs_pin;
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};
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struct spi_cc13xx_cc26xx_data {
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struct spi_context ctx;
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};
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static inline struct spi_cc13xx_cc26xx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct spi_cc13xx_cc26xx_config *
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get_dev_config(struct device *dev)
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{
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return dev->config->config_info;
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}
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static int spi_cc13xx_cc26xx_configure(struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_cc13xx_cc26xx_config *cfg = get_dev_config(dev);
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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u32_t prot;
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if (spi_context_configured(ctx, config)) {
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return 0;
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}
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/* Slave mode has not been implemented */
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if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Slave mode is not supported");
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return -ENOTSUP;
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}
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/* Word sizes other than 8 bits has not been implemented */
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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LOG_ERR("Word sizes other than 8 bits are not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("Transfer LSB first mode is not supported");
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return -EINVAL;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Multiple lines are not supported");
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return -EINVAL;
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}
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if (config->operation & SPI_CS_ACTIVE_HIGH && !config->cs) {
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LOG_ERR("Active high CS requires emulation through a GPIO line.");
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return -EINVAL;
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}
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if (config->frequency < 2000000) {
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LOG_ERR("Frequencies lower than 2 MHz are not supported");
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return -EINVAL;
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}
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if (2 * config->frequency > sys_clock_hw_cycles_per_sec()) {
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LOG_ERR("Frequency greater than supported in master mode");
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return -EINVAL;
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}
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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prot = SSI_FRF_MOTO_MODE_3;
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} else {
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prot = SSI_FRF_MOTO_MODE_2;
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}
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} else {
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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prot = SSI_FRF_MOTO_MODE_1;
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} else {
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prot = SSI_FRF_MOTO_MODE_0;
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}
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}
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IOCPinTypeSsiMaster(cfg->base, cfg->miso_pin, cfg->mosi_pin,
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cfg->cs_pin, cfg->sck_pin);
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ctx->config = config;
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/* This will reconfigure the CS pin as GPIO if same as cfg->cs_pin. */
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spi_context_cs_configure(ctx);
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/* Disable SSI before making configuration changes */
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SSIDisable(cfg->base);
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/* Configure SSI */
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SSIConfigSetExpClk(cfg->base, sys_clock_hw_cycles_per_sec(), prot,
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SSI_MODE_MASTER, config->frequency, 8);
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if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) {
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sys_set_bit(cfg->base + SSI_O_CR1, 0);
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}
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/* Re-enable SSI after making configuration changes */
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SSIEnable(cfg->base);
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return 0;
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}
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static int spi_cc13xx_cc26xx_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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const struct spi_cc13xx_cc26xx_config *cfg = get_dev_config(dev);
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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u32_t txd, rxd;
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int err;
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spi_context_lock(ctx, false, NULL);
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err = spi_cc13xx_cc26xx_configure(dev, config);
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if (err) {
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goto done;
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}
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
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spi_context_cs_control(ctx, true);
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do {
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if (spi_context_tx_buf_on(ctx)) {
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txd = *ctx->tx_buf;
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} else {
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txd = 0U;
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}
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SSIDataPut(cfg->base, txd);
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spi_context_update_tx(ctx, 1, 1);
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SSIDataGet(cfg->base, &rxd);
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if (spi_context_rx_buf_on(ctx)) {
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*ctx->rx_buf = rxd;
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}
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spi_context_update_rx(ctx, 1, 1);
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} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
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spi_context_cs_control(ctx, false);
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done:
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spi_context_release(ctx, err);
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return err;
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}
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static int spi_cc13xx_cc26xx_release(struct device *dev,
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const struct spi_config *config)
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{
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struct spi_context *ctx = &get_dev_data(dev)->ctx;
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if (!spi_context_configured(ctx, config)) {
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return -EINVAL;
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}
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if (SSIBusy(get_dev_config(dev)->base)) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(ctx);
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return 0;
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}
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#if defined(CONFIG_SPI_0) || defined(CONFIG_SPI_1)
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static const struct spi_driver_api spi_cc13xx_cc26xx_driver_api = {
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.transceive = spi_cc13xx_cc26xx_transceive,
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.release = spi_cc13xx_cc26xx_release,
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};
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#else
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#warning "No SPI port configured"
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#endif
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#ifdef CONFIG_SPI_0
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static int spi_cc13xx_cc26xx_init_0(struct device *dev)
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{
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/* Enable SSI0 power domain */
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PRCMPowerDomainOn(PRCM_DOMAIN_SERIAL);
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/* Enable SSI0 peripherals */
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PRCMPeripheralRunEnable(PRCM_PERIPH_SSI0);
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/* Enable in sleep mode until proper power managment is added */
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PRCMPeripheralSleepEnable(PRCM_PERIPH_SSI0);
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PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_SSI0);
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/* Load PRCM settings */
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PRCMLoadSet();
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while (!PRCMLoadGet()) {
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continue;
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}
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/* SSI should not be accessed until power domain is on. */
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while (PRCMPowerDomainStatus(PRCM_DOMAIN_SERIAL) !=
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PRCM_DOMAIN_POWER_ON) {
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continue;
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}
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spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
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return 0;
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}
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static const struct spi_cc13xx_cc26xx_config spi_cc13xx_cc26xx_config_0 = {
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.base = DT_TI_CC13XX_CC26XX_SPI_40000000_BASE_ADDRESS,
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.sck_pin = DT_TI_CC13XX_CC26XX_SPI_40000000_SCK_PIN,
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.mosi_pin = DT_TI_CC13XX_CC26XX_SPI_40000000_MOSI_PIN,
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.miso_pin = DT_TI_CC13XX_CC26XX_SPI_40000000_MISO_PIN,
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#ifdef DT_TI_CC13XX_CC26XX_SPI_40000000_CS_PIN
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.cs_pin = DT_TI_CC13XX_CC26XX_SPI_40000000_CS_PIN,
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#else
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.cs_pin = IOID_UNUSED,
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#endif /* DT_TI_CC13XX_CC26XX_SPI_0_CS_PIN */
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};
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static struct spi_cc13xx_cc26xx_data spi_cc13xx_cc26xx_data_0 = {
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SPI_CONTEXT_INIT_LOCK(spi_cc13xx_cc26xx_data_0, ctx),
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SPI_CONTEXT_INIT_SYNC(spi_cc13xx_cc26xx_data_0, ctx),
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};
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DEVICE_AND_API_INIT(spi_cc13xx_cc26xx_0, DT_TI_CC13XX_CC26XX_SPI_40000000_LABEL,
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spi_cc13xx_cc26xx_init_0, &spi_cc13xx_cc26xx_data_0,
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&spi_cc13xx_cc26xx_config_0, POST_KERNEL,
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CONFIG_SPI_INIT_PRIORITY, &spi_cc13xx_cc26xx_driver_api);
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#endif /* CONFIG_SPI_0 */
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#ifdef CONFIG_SPI_1
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static int spi_cc13xx_cc26xx_init_1(struct device *dev)
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{
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/* Enable SSI1 power domain */
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PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
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/* Enable SSI1 peripherals */
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PRCMPeripheralRunEnable(PRCM_PERIPH_SSI1);
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/* Enable in sleep mode until proper power managment is added */
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PRCMPeripheralSleepEnable(PRCM_PERIPH_SSI1);
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PRCMPeripheralDeepSleepEnable(PRCM_PERIPH_SSI1);
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/* Load PRCM settings */
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PRCMLoadSet();
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while (!PRCMLoadGet()) {
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continue;
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}
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/* SSI should not be accessed until power domain is on. */
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while (PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) !=
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PRCM_DOMAIN_POWER_ON) {
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continue;
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}
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spi_context_unlock_unconditionally(&get_dev_data(dev)->ctx);
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return 0;
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}
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static const struct spi_cc13xx_cc26xx_config spi_cc13xx_cc26xx_config_1 = {
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.base = DT_TI_CC13XX_CC26XX_SPI_40008000_BASE_ADDRESS,
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.sck_pin = DT_TI_CC13XX_CC26XX_SPI_40008000_SCK_PIN,
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.mosi_pin = DT_TI_CC13XX_CC26XX_SPI_40008000_MOSI_PIN,
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.miso_pin = DT_TI_CC13XX_CC26XX_SPI_40008000_MISO_PIN,
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#ifdef DT_TI_CC13XX_CC26XX_SPI_40008000_CS_PIN
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.cs_pin = DT_TI_CC13XX_CC26XX_SPI_40008000_CS_PIN,
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#else
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.cs_pin = IOID_UNUSED,
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#endif /* DT_TI_CC13XX_CC26XX_SPI_1_CS_PIN */
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};
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static struct spi_cc13xx_cc26xx_data spi_cc13xx_cc26xx_data_1 = {
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SPI_CONTEXT_INIT_LOCK(spi_cc13xx_cc26xx_data_1, ctx),
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SPI_CONTEXT_INIT_SYNC(spi_cc13xx_cc26xx_data_1, ctx),
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};
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DEVICE_AND_API_INIT(spi_cc13xx_cc26xx_1, DT_TI_CC13XX_CC26XX_SPI_40008000_LABEL,
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spi_cc13xx_cc26xx_init_1, &spi_cc13xx_cc26xx_data_1,
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&spi_cc13xx_cc26xx_config_1, POST_KERNEL,
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CONFIG_SPI_INIT_PRIORITY, &spi_cc13xx_cc26xx_driver_api);
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#endif /* CONFIG_SPI_1 */
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@ -60,4 +60,11 @@ config I2C_CC13XX_CC26XX
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endif # I2C
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if SPI
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config SPI_CC13XX_CC26XX
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default y
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endif # SPI
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endif # SOC_SERIES_CC13X2_CC26X2
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