soc/x86: Clean up EHL kconfigs
Cleanup along the same lines as the last change to APL/up_squared. Make sure all hardware configuration is at the board level where it belongs and not in the soc, don't play games with defaulting timer drivers. Unify the configuration where possible and make it clearer which setting goes with which driver. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
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@ -1,9 +1,10 @@
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_EHL_CRB
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if BOARD_EHL_CRB || BOARD_EHL_CRB_SBL
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config BOARD
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default "ehl_crb_sbl" if BOARD_EHL_CRB_SBL
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default "ehl_crb"
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config BUILD_OUTPUT_STRIPPED
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@ -12,21 +13,28 @@ config BUILD_OUTPUT_STRIPPED
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config MP_NUM_CPUS
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default 2
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endif # BOARD_EHL_CRB
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if BOARD_EHL_CRB_SBL
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config BOARD
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default "ehl_crb_sbl"
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config BUILD_OUTPUT_STRIPPED
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default y
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config MP_NUM_CPUS
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default 2
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config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
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depends on SHELL_BACKEND_SERIAL
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default n
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endif
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endif # BOARD_EHL_CRB_SBL
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config HPET_TIMER
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default y
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# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 1900000000 if APIC_TSC_DEADLINE_TIMER
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default 1900000000 if APIC_TIMER_TSC
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default 19200000
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if APIC_TIMER
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config APIC_TIMER_IRQ
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default 24
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config APIC_TIMER_TSC_M
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default 3
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config APIC_TIMER_TSC_N
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default 249
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endif
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endif # BOARD_EHL_CRB || BOARD_EHL_CRB_SBL
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@ -9,38 +9,9 @@ if SOC_ELKHART_LAKE
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config SOC
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default "elkhart_lake"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 19200000
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config HPET_TIMER
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default y
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config APIC_TIMER
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default y if !HPET_TIMER
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config PCIE_MMIO_CFG
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default y
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if APIC_TIMER
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config APIC_TIMER_IRQ
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default 24
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config APIC_TIMER_TSC
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default y
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if APIC_TIMER_TSC
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config APIC_TIMER_TSC_M
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default 3
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config APIC_TIMER_TSC_N
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default 249
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endif # APIC_TIMER_TSC
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endif # APIC_TIMER
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config X86_DYNAMIC_IRQ_STUBS
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default 16
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depends on DYNAMIC_INTERRUPTS
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