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drivers: clock_control: add STM32C0 support

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Add STM32C0 support to clock_control driver.

Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit is contained in:
Benjamin Björnsson 2023-02-26 11:01:03 +01:00 committed by Fabio Baltieri
parent 074a6c0f20
commit f38a75f753
5 changed files with 109 additions and 1 deletions
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1
drivers/clock_control/CMakeLists.txt
View file

@ -33,6 +33,7 @@ elseif(CONFIG_SOC_SERIES_STM32U5X)
zephyr_library_sources(clock_stm32_ll_u5.c)
else()
zephyr_library_sources(clock_stm32_ll_common.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32C0X clock_stm32c0.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0_f3.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2_f4_f7.c)

4
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -622,11 +622,13 @@ static void set_up_fixed_clock_sources(void)
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP)
/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
LL_PWR_EnableBkUpAccess();
while (!LL_PWR_IsEnabledBkUpAccess()) {
/* Wait for Backup domain access */
}
#endif /* PWR_CR_DBP || PWR_CR1_DBP */
#if STM32_LSE_DRIVING
/* Configure driving capability */
@ -651,7 +653,9 @@ static void set_up_fixed_clock_sources(void)
}
#endif /* RCC_BDCR_LSESYSEN */
#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP)
LL_PWR_DisableBkUpAccess();
#endif /* PWR_CR_DBP || PWR_CR1_DBP */
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
}

25
drivers/clock_control/clock_stm32c0.c Normal file
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@ -0,0 +1,25 @@
/*
*
* Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include "clock_stm32_ll_common.h"
/**
* @brief Activate default clocks
*/
void config_enable_default_clocks(void)
{
/* Enable the power interface clock */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
}

4
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -11,7 +11,9 @@
#include <zephyr/drivers/clock_control.h>
#if defined(CONFIG_SOC_SERIES_STM32F0X)
#if defined(CONFIG_SOC_SERIES_STM32C0X)
#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32F0X)
#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
#include <zephyr/dt-bindings/clock/stm32f1_clock.h>

76
include/zephyr/dt-bindings/clock/stm32c0_clock.h Normal file
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@ -0,0 +1,76 @@
/*
* Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
/** Bus clocks */
#define STM32_CLOCK_BUS_IOP 0x034
#define STM32_CLOCK_BUS_AHB1 0x038
#define STM32_CLOCK_BUS_APB1 0x03c
#define STM32_CLOCK_BUS_APB1_2 0x040
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
/** Domain clocks */
/* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
/** Fixed clocks */
#define STM32_SRC_HSI48 0x001
#define STM32_SRC_HSE 0x002
#define STM32_SRC_LSE 0x003
#define STM32_SRC_LSI 0x004
/** System clock */
#define STM32_SRC_SYSCLK 0x005
/** Peripheral bus clock */
#define STM32_SRC_PCLK 0x006
#define STM32_CLOCK_REG_MASK 0xFFU
#define STM32_CLOCK_REG_SHIFT 0U
#define STM32_CLOCK_SHIFT_MASK 0x1FU
#define STM32_CLOCK_SHIFT_SHIFT 8U
#define STM32_CLOCK_MASK_MASK 0x7U
#define STM32_CLOCK_MASK_SHIFT 13U
#define STM32_CLOCK_VAL_MASK 0x7U
#define STM32_CLOCK_VAL_SHIFT 16U
/**
* @brief STM32 clock configuration bit field.
*
* - reg (1/2/3) [ 0 : 7 ]
* - shift (0..31) [ 8 : 12 ]
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
* - val (0..7) [ 16 : 18 ]
*
* @param reg RCC_CCIPRx register offset
* @param shift Position within RCC_CCIPRx.
* @param mask Mask for the RCC_CCIPRx field.
* @param val Clock value (0, 1, ... 7).
*/
#define STM32_CLOCK(val, mask, shift, reg) \
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x54
/** @brief RCC_CSR1 register offset */
#define CSR1_REG 0x5C
/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
/** CSR1 devices */
#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR1_REG)
/** Dummy: Add a specificier when no selection is possible */
#define NO_SEL 0xFF
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */