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ext: hal: atmel: import SAM E70 HAL revision B

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This is an import of Atmel SAM E70 HAL version 2.3.98, for the revision
B of the chip. The files have been passed through dos2unix to minimize
the differences with the revision A  which seems to also have been
imported that way.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2019-02-05 00:37:03 +01:00 committed by Anas Nashif
parent dffd779ff3
commit f3bdc057b1
112 changed files with 73036 additions and 0 deletions
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36
ext/hal/atmel/asf/sam/include/same70b/README Normal file
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Atmel SAM E70B
##############
Origin:
Microchip Packs Repository
http://packs.download.atmel.com/
Atmel SAME70 Series Device Support (2.3.98)
http://packs.download.atmel.com/Atmel.SAME70_DFP.2.3.98.atpack
Status:
version 2.3.98
Purpose:
Official package for SAM E70B.
Description:
Atmel Software Framework (ASF) provides a set of low-level
header files that give access to different hardware
peripherals of Atmel's ICs.
URL:
http://packs.download.atmel.com/
http://packs.download.atmel.com/Atmel.SAME70_DFP.2.3.98.atpack
commit:
n/a
Maintained-by:
External
License:
Apache-2.0
License Link:
https://www.apache.org/licenses/LICENSE-2.0

64
ext/hal/atmel/asf/sam/include/same70b/component-version.h Normal file
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/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 2
#define COMPONENT_VERSION_MINOR 3
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version.
//
#define COMPONENT_VERSION 20003
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 98
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "2.3"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2018-01-30 13:59:17"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */

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ext/hal/atmel/asf/sam/include/same70b/component/acc.h Normal file
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/**
* \file
*
* \brief Component description for ACC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_ACC_COMPONENT_H_
#define _SAME70_ACC_COMPONENT_H_
#define _SAME70_ACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Analog Comparator Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ACC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define ACC_6490 /**< (ACC) Module ID */
#define REV_ACC H /**< (ACC) Module revision */
/* -------- ACC_CR : (ACC Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /**< bit: 0 Software Reset */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_CR_OFFSET (0x00) /**< (ACC_CR) Control Register Offset */
#define ACC_CR_SWRST_Pos 0 /**< (ACC_CR) Software Reset Position */
#define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */
#define ACC_CR_SWRST ACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_CR_SWRST_Msk instead */
#define ACC_CR_MASK _U_(0x01) /**< \deprecated (ACC_CR) Register MASK (Use ACC_CR_Msk instead) */
#define ACC_CR_Msk _U_(0x01) /**< (ACC_CR) Register Mask */
/* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SELMINUS:3; /**< bit: 0..2 Selection for Minus Comparator Input */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t SELPLUS:3; /**< bit: 4..6 Selection For Plus Comparator Input */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t ACEN:1; /**< bit: 8 Analog Comparator Enable */
uint32_t EDGETYP:2; /**< bit: 9..10 Edge Type */
uint32_t :1; /**< bit: 11 Reserved */
uint32_t INV:1; /**< bit: 12 Invert Comparator Output */
uint32_t SELFS:1; /**< bit: 13 Selection Of Fault Source */
uint32_t FE:1; /**< bit: 14 Fault Enable */
uint32_t :17; /**< bit: 15..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_MR_OFFSET (0x04) /**< (ACC_MR) Mode Register Offset */
#define ACC_MR_SELMINUS_Pos 0 /**< (ACC_MR) Selection for Minus Comparator Input Position */
#define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */
#define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))
#define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */
#define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */
#define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */
#define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */
#define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */
#define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */
#define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */
#define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */
#define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */
#define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */
#define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */
#define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */
#define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */
#define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */
#define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */
#define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */
#define ACC_MR_SELPLUS_Pos 4 /**< (ACC_MR) Selection For Plus Comparator Input Position */
#define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */
#define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))
#define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */
#define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */
#define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */
#define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */
#define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */
#define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */
#define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */
#define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */
#define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */
#define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */
#define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */
#define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */
#define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */
#define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */
#define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */
#define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */
#define ACC_MR_ACEN_Pos 8 /**< (ACC_MR) Analog Comparator Enable Position */
#define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */
#define ACC_MR_ACEN ACC_MR_ACEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_ACEN_Msk instead */
#define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */
#define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */
#define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */
#define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */
#define ACC_MR_EDGETYP_Pos 9 /**< (ACC_MR) Edge Type Position */
#define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */
#define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))
#define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */
#define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */
#define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */
#define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */
#define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */
#define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */
#define ACC_MR_INV_Pos 12 /**< (ACC_MR) Invert Comparator Output Position */
#define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */
#define ACC_MR_INV ACC_MR_INV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_INV_Msk instead */
#define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */
#define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */
#define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */
#define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */
#define ACC_MR_SELFS_Pos 13 /**< (ACC_MR) Selection Of Fault Source Position */
#define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */
#define ACC_MR_SELFS ACC_MR_SELFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_SELFS_Msk instead */
#define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */
#define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
#define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */
#define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */
#define ACC_MR_FE_Pos 14 /**< (ACC_MR) Fault Enable Position */
#define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */
#define ACC_MR_FE ACC_MR_FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_FE_Msk instead */
#define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */
#define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
#define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */
#define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */
#define ACC_MR_MASK _U_(0x7777) /**< \deprecated (ACC_MR) Register MASK (Use ACC_MR_Msk instead) */
#define ACC_MR_Msk _U_(0x7777) /**< (ACC_MR) Register Mask */
/* -------- ACC_IER : (ACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CE:1; /**< bit: 0 Comparison Edge */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_IER_OFFSET (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */
#define ACC_IER_CE_Pos 0 /**< (ACC_IER) Comparison Edge Position */
#define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */
#define ACC_IER_CE ACC_IER_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IER_CE_Msk instead */
#define ACC_IER_MASK _U_(0x01) /**< \deprecated (ACC_IER) Register MASK (Use ACC_IER_Msk instead) */
#define ACC_IER_Msk _U_(0x01) /**< (ACC_IER) Register Mask */
/* -------- ACC_IDR : (ACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CE:1; /**< bit: 0 Comparison Edge */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_IDR_OFFSET (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */
#define ACC_IDR_CE_Pos 0 /**< (ACC_IDR) Comparison Edge Position */
#define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */
#define ACC_IDR_CE ACC_IDR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IDR_CE_Msk instead */
#define ACC_IDR_MASK _U_(0x01) /**< \deprecated (ACC_IDR) Register MASK (Use ACC_IDR_Msk instead) */
#define ACC_IDR_Msk _U_(0x01) /**< (ACC_IDR) Register Mask */
/* -------- ACC_IMR : (ACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CE:1; /**< bit: 0 Comparison Edge */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_IMR_OFFSET (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */
#define ACC_IMR_CE_Pos 0 /**< (ACC_IMR) Comparison Edge Position */
#define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */
#define ACC_IMR_CE ACC_IMR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IMR_CE_Msk instead */
#define ACC_IMR_MASK _U_(0x01) /**< \deprecated (ACC_IMR) Register MASK (Use ACC_IMR_Msk instead) */
#define ACC_IMR_Msk _U_(0x01) /**< (ACC_IMR) Register Mask */
/* -------- ACC_ISR : (ACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CE:1; /**< bit: 0 Comparison Edge (cleared on read) */
uint32_t SCO:1; /**< bit: 1 Synchronized Comparator Output */
uint32_t :29; /**< bit: 2..30 Reserved */
uint32_t MASK:1; /**< bit: 31 Flag Mask */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_ISR_OFFSET (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */
#define ACC_ISR_CE_Pos 0 /**< (ACC_ISR) Comparison Edge (cleared on read) Position */
#define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */
#define ACC_ISR_CE ACC_ISR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_CE_Msk instead */
#define ACC_ISR_SCO_Pos 1 /**< (ACC_ISR) Synchronized Comparator Output Position */
#define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */
#define ACC_ISR_SCO ACC_ISR_SCO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_SCO_Msk instead */
#define ACC_ISR_MASK_Pos 31 /**< (ACC_ISR) Flag Mask Position */
#define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */
#define ACC_ISR_MASK ACC_ISR_MASK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_MASK_Msk instead */
#define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */
/* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ISEL:1; /**< bit: 0 Current Selection */
uint32_t HYST:2; /**< bit: 1..2 Hysteresis Selection */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_ACR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_ACR_OFFSET (0x94) /**< (ACC_ACR) Analog Control Register Offset */
#define ACC_ACR_ISEL_Pos 0 /**< (ACC_ACR) Current Selection Position */
#define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */
#define ACC_ACR_ISEL ACC_ACR_ISEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ACR_ISEL_Msk instead */
#define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */
#define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */
#define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */
#define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */
#define ACC_ACR_HYST_Pos 1 /**< (ACC_ACR) Hysteresis Selection Position */
#define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */
#define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))
#define ACC_ACR_MASK _U_(0x07) /**< \deprecated (ACC_ACR) Register MASK (Use ACC_ACR_Msk instead) */
#define ACC_ACR_Msk _U_(0x07) /**< (ACC_ACR) Register Mask */
/* -------- ACC_WPMR : (ACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_WPMR_OFFSET (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */
#define ACC_WPMR_WPEN_Pos 0 /**< (ACC_WPMR) Write Protection Enable Position */
#define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */
#define ACC_WPMR_WPEN ACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPMR_WPEN_Msk instead */
#define ACC_WPMR_WPKEY_Pos 8 /**< (ACC_WPMR) Write Protection Key Position */
#define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */
#define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))
#define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define ACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (ACC_WPMR) Register MASK (Use ACC_WPMR_Msk instead) */
#define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */
/* -------- ACC_WPSR : (ACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ACC_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ACC_WPSR_OFFSET (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */
#define ACC_WPSR_WPVS_Pos 0 /**< (ACC_WPSR) Write Protection Violation Status Position */
#define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */
#define ACC_WPSR_WPVS ACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPSR_WPVS_Msk instead */
#define ACC_WPSR_MASK _U_(0x01) /**< \deprecated (ACC_WPSR) Register MASK (Use ACC_WPSR_Msk instead) */
#define ACC_WPSR_Msk _U_(0x01) /**< (ACC_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief ACC hardware registers */
typedef struct {
__O uint32_t ACC_CR; /**< (ACC Offset: 0x00) Control Register */
__IO uint32_t ACC_MR; /**< (ACC Offset: 0x04) Mode Register */
RoReg8 Reserved1[0x1C];
__O uint32_t ACC_IER; /**< (ACC Offset: 0x24) Interrupt Enable Register */
__O uint32_t ACC_IDR; /**< (ACC Offset: 0x28) Interrupt Disable Register */
__I uint32_t ACC_IMR; /**< (ACC Offset: 0x2C) Interrupt Mask Register */
__I uint32_t ACC_ISR; /**< (ACC Offset: 0x30) Interrupt Status Register */
RoReg8 Reserved2[0x60];
__IO uint32_t ACC_ACR; /**< (ACC Offset: 0x94) Analog Control Register */
RoReg8 Reserved3[0x4C];
__IO uint32_t ACC_WPMR; /**< (ACC Offset: 0xE4) Write Protection Mode Register */
__I uint32_t ACC_WPSR; /**< (ACC Offset: 0xE8) Write Protection Status Register */
} Acc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief ACC hardware registers */
typedef struct {
__O ACC_CR_Type ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO ACC_MR_Type ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I uint32_t Reserved1[7];
__O ACC_IER_Type ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
__O ACC_IDR_Type ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
__I ACC_IMR_Type ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
__I ACC_ISR_Type ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */
__I uint32_t Reserved2[24];
__IO ACC_ACR_Type ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */
__I uint32_t Reserved3[19];
__IO ACC_WPMR_Type ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I ACC_WPSR_Type ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Acc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Analog Comparator Controller */
#endif /* _SAME70_ACC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for AES
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_AES_COMPONENT_H_
#define _SAME70_AES_COMPONENT_H_
#define _SAME70_AES_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Advanced Encryption Standard
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AES */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define AES_6149 /**< (AES) Module ID */
#define REV_AES W /**< (AES) Module revision */
/* -------- AES_CR : (AES Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t START:1; /**< bit: 0 Start Processing */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t SWRST:1; /**< bit: 8 Software Reset */
uint32_t :23; /**< bit: 9..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CR_OFFSET (0x00) /**< (AES_CR) Control Register Offset */
#define AES_CR_START_Pos 0 /**< (AES_CR) Start Processing Position */
#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */
#define AES_CR_START AES_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_START_Msk instead */
#define AES_CR_SWRST_Pos 8 /**< (AES_CR) Software Reset Position */
#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */
#define AES_CR_SWRST AES_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_SWRST_Msk instead */
#define AES_CR_MASK _U_(0x101) /**< \deprecated (AES_CR) Register MASK (Use AES_CR_Msk instead) */
#define AES_CR_Msk _U_(0x101) /**< (AES_CR) Register Mask */
/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CIPHER:1; /**< bit: 0 Processing Mode */
uint32_t GTAGEN:1; /**< bit: 1 GCM Automatic Tag Generation Enable */
uint32_t :1; /**< bit: 2 Reserved */
uint32_t DUALBUFF:1; /**< bit: 3 Dual Input Buffer */
uint32_t PROCDLY:4; /**< bit: 4..7 Processing Delay */
uint32_t SMOD:2; /**< bit: 8..9 Start Mode */
uint32_t KEYSIZE:2; /**< bit: 10..11 Key Size */
uint32_t OPMOD:3; /**< bit: 12..14 Operating Mode */
uint32_t LOD:1; /**< bit: 15 Last Output Data Mode */
uint32_t CFBS:3; /**< bit: 16..18 Cipher Feedback Data Size */
uint32_t :1; /**< bit: 19 Reserved */
uint32_t CKEY:4; /**< bit: 20..23 Countermeasure Key */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_MR_OFFSET (0x04) /**< (AES_MR) Mode Register Offset */
#define AES_MR_CIPHER_Pos 0 /**< (AES_MR) Processing Mode Position */
#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */
#define AES_MR_CIPHER AES_MR_CIPHER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CIPHER_Msk instead */
#define AES_MR_GTAGEN_Pos 1 /**< (AES_MR) GCM Automatic Tag Generation Enable Position */
#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */
#define AES_MR_GTAGEN AES_MR_GTAGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_GTAGEN_Msk instead */
#define AES_MR_DUALBUFF_Pos 3 /**< (AES_MR) Dual Input Buffer Position */
#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */
#define AES_MR_DUALBUFF AES_MR_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_DUALBUFF_Msk instead */
#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */
#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */
#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */
#define AES_MR_PROCDLY_Pos 4 /**< (AES_MR) Processing Delay Position */
#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */
#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))
#define AES_MR_SMOD_Pos 8 /**< (AES_MR) Start Mode Position */
#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */
#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))
#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */
#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */
#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */
#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */
#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */
#define AES_MR_KEYSIZE_Pos 10 /**< (AES_MR) Key Size Position */
#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */
#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))
#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */
#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */
#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */
#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */
#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */
#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */
#define AES_MR_OPMOD_Pos 12 /**< (AES_MR) Operating Mode Position */
#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */
#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))
#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */
#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */
#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */
#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */
#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */
#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */
#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */
#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */
#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */
#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */
#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */
#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */
#define AES_MR_LOD_Pos 15 /**< (AES_MR) Last Output Data Mode Position */
#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */
#define AES_MR_LOD AES_MR_LOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_LOD_Msk instead */
#define AES_MR_CFBS_Pos 16 /**< (AES_MR) Cipher Feedback Data Size Position */
#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */
#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))
#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */
#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */
#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */
#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */
#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */
#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */
#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */
#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */
#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */
#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */
#define AES_MR_CKEY_Pos 20 /**< (AES_MR) Countermeasure Key Position */
#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */
#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))
#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */
#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */
#define AES_MR_MASK _U_(0xF7FFFB) /**< \deprecated (AES_MR) Register MASK (Use AES_MR_Msk instead) */
#define AES_MR_Msk _U_(0xF7FFFB) /**< (AES_MR) Register Mask */
/* -------- AES_IER : (AES Offset: 0x10) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Enable */
uint32_t :7; /**< bit: 9..15 Reserved */
uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Enable */
uint32_t :15; /**< bit: 17..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_IER_OFFSET (0x10) /**< (AES_IER) Interrupt Enable Register Offset */
#define AES_IER_DATRDY_Pos 0 /**< (AES_IER) Data Ready Interrupt Enable Position */
#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */
#define AES_IER_DATRDY AES_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_DATRDY_Msk instead */
#define AES_IER_URAD_Pos 8 /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */
#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */
#define AES_IER_URAD AES_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_URAD_Msk instead */
#define AES_IER_TAGRDY_Pos 16 /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */
#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */
#define AES_IER_TAGRDY AES_IER_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_TAGRDY_Msk instead */
#define AES_IER_MASK _U_(0x10101) /**< \deprecated (AES_IER) Register MASK (Use AES_IER_Msk instead) */
#define AES_IER_Msk _U_(0x10101) /**< (AES_IER) Register Mask */
/* -------- AES_IDR : (AES Offset: 0x14) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Disable */
uint32_t :7; /**< bit: 9..15 Reserved */
uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Disable */
uint32_t :15; /**< bit: 17..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_IDR_OFFSET (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */
#define AES_IDR_DATRDY_Pos 0 /**< (AES_IDR) Data Ready Interrupt Disable Position */
#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */
#define AES_IDR_DATRDY AES_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_DATRDY_Msk instead */
#define AES_IDR_URAD_Pos 8 /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */
#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */
#define AES_IDR_URAD AES_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_URAD_Msk instead */
#define AES_IDR_TAGRDY_Pos 16 /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */
#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */
#define AES_IDR_TAGRDY AES_IDR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_TAGRDY_Msk instead */
#define AES_IDR_MASK _U_(0x10101) /**< \deprecated (AES_IDR) Register MASK (Use AES_IDR_Msk instead) */
#define AES_IDR_Msk _U_(0x10101) /**< (AES_IDR) Register Mask */
/* -------- AES_IMR : (AES Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Mask */
uint32_t :7; /**< bit: 9..15 Reserved */
uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Mask */
uint32_t :15; /**< bit: 17..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_IMR_OFFSET (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */
#define AES_IMR_DATRDY_Pos 0 /**< (AES_IMR) Data Ready Interrupt Mask Position */
#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */
#define AES_IMR_DATRDY AES_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_DATRDY_Msk instead */
#define AES_IMR_URAD_Pos 8 /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */
#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */
#define AES_IMR_URAD AES_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_URAD_Msk instead */
#define AES_IMR_TAGRDY_Pos 16 /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */
#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */
#define AES_IMR_TAGRDY AES_IMR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_TAGRDY_Msk instead */
#define AES_IMR_MASK _U_(0x10101) /**< \deprecated (AES_IMR) Register MASK (Use AES_IMR_Msk instead) */
#define AES_IMR_Msk _U_(0x10101) /**< (AES_IMR) Register Mask */
/* -------- AES_ISR : (AES Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */
uint32_t :3; /**< bit: 9..11 Reserved */
uint32_t URAT:4; /**< bit: 12..15 Unspecified Register Access (cleared by writing SWRST in AES_CR) */
uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready */
uint32_t :15; /**< bit: 17..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_ISR_OFFSET (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */
#define AES_ISR_DATRDY_Pos 0 /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */
#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */
#define AES_ISR_DATRDY AES_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_DATRDY_Msk instead */
#define AES_ISR_URAD_Pos 8 /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */
#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */
#define AES_ISR_URAD AES_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_URAD_Msk instead */
#define AES_ISR_URAT_Pos 12 /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */
#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */
#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos))
#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */
#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */
#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */
#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */
#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */
#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */
#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */
#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */
#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */
#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */
#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */
#define AES_ISR_TAGRDY_Pos 16 /**< (AES_ISR) GCM Tag Ready Position */
#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */
#define AES_ISR_TAGRDY AES_ISR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_TAGRDY_Msk instead */
#define AES_ISR_MASK _U_(0x1F101) /**< \deprecated (AES_ISR) Register MASK (Use AES_ISR_Msk instead) */
#define AES_ISR_Msk _U_(0x1F101) /**< (AES_ISR) Register Mask */
/* -------- AES_KEYWR : (AES Offset: 0x20) (/W 32) Key Word Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEYW:32; /**< bit: 0..31 Key Word */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_KEYWR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_KEYWR_OFFSET (0x20) /**< (AES_KEYWR) Key Word Register 0 Offset */
#define AES_KEYWR_KEYW_Pos 0 /**< (AES_KEYWR) Key Word Position */
#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */
#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))
#define AES_KEYWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_KEYWR) Register MASK (Use AES_KEYWR_Msk instead) */
#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */
/* -------- AES_IDATAR : (AES Offset: 0x40) (/W 32) Input Data Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IDATA:32; /**< bit: 0..31 Input Data Word */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_IDATAR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_IDATAR_OFFSET (0x40) /**< (AES_IDATAR) Input Data Register 0 Offset */
#define AES_IDATAR_IDATA_Pos 0 /**< (AES_IDATAR) Input Data Word Position */
#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */
#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))
#define AES_IDATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IDATAR) Register MASK (Use AES_IDATAR_Msk instead) */
#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */
/* -------- AES_ODATAR : (AES Offset: 0x50) (R/ 32) Output Data Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ODATA:32; /**< bit: 0..31 Output Data */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_ODATAR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_ODATAR_OFFSET (0x50) /**< (AES_ODATAR) Output Data Register 0 Offset */
#define AES_ODATAR_ODATA_Pos 0 /**< (AES_ODATAR) Output Data Position */
#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */
#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos))
#define AES_ODATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_ODATAR) Register MASK (Use AES_ODATAR_Msk instead) */
#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */
/* -------- AES_IVR : (AES Offset: 0x60) (/W 32) Initialization Vector Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IV:32; /**< bit: 0..31 Initialization Vector */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_IVR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_IVR_OFFSET (0x60) /**< (AES_IVR) Initialization Vector Register 0 Offset */
#define AES_IVR_IV_Pos 0 /**< (AES_IVR) Initialization Vector Position */
#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */
#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))
#define AES_IVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IVR) Register MASK (Use AES_IVR_Msk instead) */
#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */
/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AADLEN:32; /**< bit: 0..31 Additional Authenticated Data Length */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_AADLENR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_AADLENR_OFFSET (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */
#define AES_AADLENR_AADLEN_Pos 0 /**< (AES_AADLENR) Additional Authenticated Data Length Position */
#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */
#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))
#define AES_AADLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_AADLENR) Register MASK (Use AES_AADLENR_Msk instead) */
#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */
/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CLEN:32; /**< bit: 0..31 Plaintext/Ciphertext Length */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_CLENR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CLENR_OFFSET (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */
#define AES_CLENR_CLEN_Pos 0 /**< (AES_CLENR) Plaintext/Ciphertext Length Position */
#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */
#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))
#define AES_CLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CLENR) Register MASK (Use AES_CLENR_Msk instead) */
#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */
/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GHASH:32; /**< bit: 0..31 Intermediate GCM Hash Word x */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_GHASHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_GHASHR_OFFSET (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register 0 Offset */
#define AES_GHASHR_GHASH_Pos 0 /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */
#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */
#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))
#define AES_GHASHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GHASHR) Register MASK (Use AES_GHASHR_Msk instead) */
#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */
/* -------- AES_TAGR : (AES Offset: 0x88) (R/ 32) GCM Authentication Tag Word Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TAG:32; /**< bit: 0..31 GCM Authentication Tag x */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_TAGR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_TAGR_OFFSET (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register 0 Offset */
#define AES_TAGR_TAG_Pos 0 /**< (AES_TAGR) GCM Authentication Tag x Position */
#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */
#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos))
#define AES_TAGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_TAGR) Register MASK (Use AES_TAGR_Msk instead) */
#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */
/* -------- AES_CTRR : (AES Offset: 0x98) (R/ 32) GCM Encryption Counter Value Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CTR:32; /**< bit: 0..31 GCM Encryption Counter */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_CTRR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CTRR_OFFSET (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */
#define AES_CTRR_CTR_Pos 0 /**< (AES_CTRR) GCM Encryption Counter Position */
#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */
#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos))
#define AES_CTRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CTRR) Register MASK (Use AES_CTRR_Msk instead) */
#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */
/* -------- AES_GCMHR : (AES Offset: 0x9c) (R/W 32) GCM H Word Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t H:32; /**< bit: 0..31 GCM H Word x */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} AES_GCMHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_GCMHR_OFFSET (0x9C) /**< (AES_GCMHR) GCM H Word Register 0 Offset */
#define AES_GCMHR_H_Pos 0 /**< (AES_GCMHR) GCM H Word x Position */
#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */
#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))
#define AES_GCMHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GCMHR) Register MASK (Use AES_GCMHR_Msk instead) */
#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief AES hardware registers */
typedef struct {
__O uint32_t AES_CR; /**< (AES Offset: 0x00) Control Register */
__IO uint32_t AES_MR; /**< (AES Offset: 0x04) Mode Register */
RoReg8 Reserved1[0x8];
__O uint32_t AES_IER; /**< (AES Offset: 0x10) Interrupt Enable Register */
__O uint32_t AES_IDR; /**< (AES Offset: 0x14) Interrupt Disable Register */
__I uint32_t AES_IMR; /**< (AES Offset: 0x18) Interrupt Mask Register */
__I uint32_t AES_ISR; /**< (AES Offset: 0x1C) Interrupt Status Register */
__O uint32_t AES_KEYWR[8]; /**< (AES Offset: 0x20) Key Word Register 0 */
__O uint32_t AES_IDATAR[4]; /**< (AES Offset: 0x40) Input Data Register 0 */
__I uint32_t AES_ODATAR[4]; /**< (AES Offset: 0x50) Output Data Register 0 */
__O uint32_t AES_IVR[4]; /**< (AES Offset: 0x60) Initialization Vector Register 0 */
__IO uint32_t AES_AADLENR; /**< (AES Offset: 0x70) Additional Authenticated Data Length Register */
__IO uint32_t AES_CLENR; /**< (AES Offset: 0x74) Plaintext/Ciphertext Length Register */
__IO uint32_t AES_GHASHR[4]; /**< (AES Offset: 0x78) GCM Intermediate Hash Word Register 0 */
__I uint32_t AES_TAGR[4]; /**< (AES Offset: 0x88) GCM Authentication Tag Word Register 0 */
__I uint32_t AES_CTRR; /**< (AES Offset: 0x98) GCM Encryption Counter Value Register */
__IO uint32_t AES_GCMHR[4]; /**< (AES Offset: 0x9C) GCM H Word Register 0 */
} Aes;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief AES hardware registers */
typedef struct {
__O AES_CR_Type AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO AES_MR_Type AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I uint32_t Reserved1[2];
__O AES_IER_Type AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
__O AES_IDR_Type AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
__I AES_IMR_Type AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
__I AES_ISR_Type AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
__O AES_KEYWR_Type AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register 0 */
__O AES_IDATAR_Type AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register 0 */
__I AES_ODATAR_Type AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register 0 */
__O AES_IVR_Type AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register 0 */
__IO AES_AADLENR_Type AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */
__IO AES_CLENR_Type AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */
__IO AES_GHASHR_Type AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register 0 */
__I AES_TAGR_Type AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register 0 */
__I AES_CTRR_Type AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */
__IO AES_GCMHR_Type AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register 0 */
} Aes;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Advanced Encryption Standard */
#endif /* _SAME70_AES_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for CHIPID
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_CHIPID_COMPONENT_H_
#define _SAME70_CHIPID_COMPONENT_H_
#define _SAME70_CHIPID_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Chip Identifier
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR CHIPID */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define CHIPID_6417 /**< (CHIPID) Module ID */
#define REV_CHIPID ZK /**< (CHIPID) Module revision */
/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) (R/ 32) Chip ID Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VERSION:5; /**< bit: 0..4 Version of the Device */
uint32_t EPROC:3; /**< bit: 5..7 Embedded Processor */
uint32_t NVPSIZ:4; /**< bit: 8..11 Nonvolatile Program Memory Size */
uint32_t NVPSIZ2:4; /**< bit: 12..15 Second Nonvolatile Program Memory Size */
uint32_t SRAMSIZ:4; /**< bit: 16..19 Internal SRAM Size */
uint32_t ARCH:8; /**< bit: 20..27 Architecture Identifier */
uint32_t NVPTYP:3; /**< bit: 28..30 Nonvolatile Program Memory Type */
uint32_t EXT:1; /**< bit: 31 Extension Flag */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} CHIPID_CIDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CHIPID_CIDR_OFFSET (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */
#define CHIPID_CIDR_VERSION_Pos 0 /**< (CHIPID_CIDR) Version of the Device Position */
#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */
#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos))
#define CHIPID_CIDR_EPROC_Pos 5 /**< (CHIPID_CIDR) Embedded Processor Position */
#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */
#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos))
#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */
#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */
#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */
#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */
#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */
#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */
#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */
#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */
#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */
#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */
#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */
#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */
#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */
#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */
#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */
#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */
#define CHIPID_CIDR_NVPSIZ_Pos 8 /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */
#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */
#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos))
#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */
#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */
#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_Pos 12 /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */
#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */
#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos))
#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */
#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_Pos 16 /**< (CHIPID_CIDR) Internal SRAM Size Position */
#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */
#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos))
#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */
#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */
#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
#define CHIPID_CIDR_ARCH_Pos 20 /**< (CHIPID_CIDR) Architecture Identifier Position */
#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */
#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos))
#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */
#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */
#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */
#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */
#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */
#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */
#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */
#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */
#define CHIPID_CIDR_NVPTYP_Pos 28 /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */
#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */
#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos))
#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */
#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */
#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */
#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */
#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */
#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */
#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */
#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */
#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */
#define CHIPID_CIDR_EXT_Pos 31 /**< (CHIPID_CIDR) Extension Flag Position */
#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */
#define CHIPID_CIDR_EXT CHIPID_CIDR_EXT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CHIPID_CIDR_EXT_Msk instead */
#define CHIPID_CIDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_CIDR) Register MASK (Use CHIPID_CIDR_Msk instead) */
#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */
/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) (R/ 32) Chip ID Extension Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXID:32; /**< bit: 0..31 Chip ID Extension */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} CHIPID_EXID_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CHIPID_EXID_OFFSET (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */
#define CHIPID_EXID_EXID_Pos 0 /**< (CHIPID_EXID) Chip ID Extension Position */
#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */
#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos))
#define CHIPID_EXID_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_EXID) Register MASK (Use CHIPID_EXID_Msk instead) */
#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief CHIPID hardware registers */
typedef struct {
__I uint32_t CHIPID_CIDR; /**< (CHIPID Offset: 0x00) Chip ID Register */
__I uint32_t CHIPID_EXID; /**< (CHIPID Offset: 0x04) Chip ID Extension Register */
} Chipid;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief CHIPID hardware registers */
typedef struct {
__I CHIPID_CIDR_Type CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */
__I CHIPID_EXID_Type CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */
} Chipid;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Chip Identifier */
#endif /* _SAME70_CHIPID_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for DACC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_DACC_COMPONENT_H_
#define _SAME70_DACC_COMPONENT_H_
#define _SAME70_DACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Digital-to-Analog Converter Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DACC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define DACC_11246 /**< (DACC) Module ID */
#define REV_DACC E /**< (DACC) Module revision */
/* -------- DACC_CR : (DACC Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /**< bit: 0 Software Reset */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} DACC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_CR_OFFSET (0x00) /**< (DACC_CR) Control Register Offset */
#define DACC_CR_SWRST_Pos 0 /**< (DACC_CR) Software Reset Position */
#define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */
#define DACC_CR_SWRST DACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CR_SWRST_Msk instead */
#define DACC_CR_MASK _U_(0x01) /**< \deprecated (DACC_CR) Register MASK (Use DACC_CR_Msk instead) */
#define DACC_CR_Msk _U_(0x01) /**< (DACC_CR) Register Mask */
/* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MAXS0:1; /**< bit: 0 Max Speed Mode for Channel 0 */
uint32_t MAXS1:1; /**< bit: 1 Max Speed Mode for Channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t WORD:1; /**< bit: 4 Word Transfer Mode */
uint32_t ZERO:1; /**< bit: 5 Must always be written to 0. */
uint32_t :17; /**< bit: 6..22 Reserved */
uint32_t DIFF:1; /**< bit: 23 Differential Mode */
uint32_t PRESCALER:4; /**< bit: 24..27 Peripheral Clock to DAC Clock Ratio */
uint32_t :4; /**< bit: 28..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t MAXS:2; /**< bit: 0..1 Max Speed Mode for Channel x */
uint32_t :30; /**< bit: 2..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_MR_OFFSET (0x04) /**< (DACC_MR) Mode Register Offset */
#define DACC_MR_MAXS0_Pos 0 /**< (DACC_MR) Max Speed Mode for Channel 0 Position */
#define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */
#define DACC_MR_MAXS0 DACC_MR_MAXS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS0_Msk instead */
#define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */
#define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */
#define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */
#define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */
#define DACC_MR_MAXS1_Pos 1 /**< (DACC_MR) Max Speed Mode for Channel 1 Position */
#define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */
#define DACC_MR_MAXS1 DACC_MR_MAXS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS1_Msk instead */
#define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */
#define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */
#define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */
#define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */
#define DACC_MR_WORD_Pos 4 /**< (DACC_MR) Word Transfer Mode Position */
#define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */
#define DACC_MR_WORD DACC_MR_WORD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_WORD_Msk instead */
#define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */
#define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */
#define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */
#define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */
#define DACC_MR_ZERO_Pos 5 /**< (DACC_MR) Must always be written to 0. Position */
#define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */
#define DACC_MR_ZERO DACC_MR_ZERO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_ZERO_Msk instead */
#define DACC_MR_DIFF_Pos 23 /**< (DACC_MR) Differential Mode Position */
#define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */
#define DACC_MR_DIFF DACC_MR_DIFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_DIFF_Msk instead */
#define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */
#define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */
#define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */
#define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */
#define DACC_MR_PRESCALER_Pos 24 /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */
#define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */
#define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))
#define DACC_MR_MASK _U_(0xF800033) /**< \deprecated (DACC_MR) Register MASK (Use DACC_MR_Msk instead) */
#define DACC_MR_Msk _U_(0xF800033) /**< (DACC_MR) Register Mask */
#define DACC_MR_MAXS_Pos 0 /**< (DACC_MR Position) Max Speed Mode for Channel x */
#define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */
#define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos))
/* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TRGEN0:1; /**< bit: 0 Trigger Enable of Channel 0 */
uint32_t TRGEN1:1; /**< bit: 1 Trigger Enable of Channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t TRGSEL0:3; /**< bit: 4..6 Trigger Selection of Channel 0 */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t TRGSEL1:3; /**< bit: 8..10 Trigger Selection of Channel 1 */
uint32_t :5; /**< bit: 11..15 Reserved */
uint32_t OSR0:3; /**< bit: 16..18 Over Sampling Ratio of Channel 0 */
uint32_t :1; /**< bit: 19 Reserved */
uint32_t OSR1:3; /**< bit: 20..22 Over Sampling Ratio of Channel 1 */
uint32_t :9; /**< bit: 23..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t TRGEN:2; /**< bit: 0..1 Trigger Enable of Channel x */
uint32_t :30; /**< bit: 2..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_TRIGR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_TRIGR_OFFSET (0x08) /**< (DACC_TRIGR) Trigger Register Offset */
#define DACC_TRIGR_TRGEN0_Pos 0 /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */
#define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */
#define DACC_TRIGR_TRGEN0 DACC_TRIGR_TRGEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN0_Msk instead */
#define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
#define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */
#define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */
#define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */
#define DACC_TRIGR_TRGEN1_Pos 1 /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */
#define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */
#define DACC_TRIGR_TRGEN1 DACC_TRIGR_TRGEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN1_Msk instead */
#define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
#define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */
#define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */
#define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */
#define DACC_TRIGR_TRGSEL0_Pos 4 /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */
#define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */
#define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))
#define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */
#define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */
#define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */
#define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */
#define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */
#define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */
#define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */
#define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */
#define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DATRG Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 output Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC1 output Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC2 output Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */
#define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */
#define DACC_TRIGR_TRGSEL1_Pos 8 /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */
#define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */
#define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))
#define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */
#define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */
#define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */
#define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */
#define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */
#define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */
#define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */
#define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */
#define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DATRG Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 output Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC1 output Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC2 output Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */
#define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */
#define DACC_TRIGR_OSR0_Pos 16 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */
#define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */
#define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))
#define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */
#define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */
#define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */
#define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */
#define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */
#define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */
#define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */
#define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */
#define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */
#define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */
#define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */
#define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */
#define DACC_TRIGR_OSR1_Pos 20 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */
#define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */
#define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))
#define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */
#define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */
#define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */
#define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */
#define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */
#define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */
#define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */
#define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */
#define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */
#define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */
#define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */
#define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */
#define DACC_TRIGR_MASK _U_(0x770773) /**< \deprecated (DACC_TRIGR) Register MASK (Use DACC_TRIGR_Msk instead) */
#define DACC_TRIGR_Msk _U_(0x770773) /**< (DACC_TRIGR) Register Mask */
#define DACC_TRIGR_TRGEN_Pos 0 /**< (DACC_TRIGR Position) Trigger Enable of Channel x */
#define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */
#define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos))
/* -------- DACC_CHER : (DACC Offset: 0x10) (/W 32) Channel Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CH0:1; /**< bit: 0 Channel 0 Enable */
uint32_t CH1:1; /**< bit: 1 Channel 1 Enable */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t CH:2; /**< bit: 0..1 Channel x Enable */
uint32_t :30; /**< bit: 2..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_CHER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_CHER_OFFSET (0x10) /**< (DACC_CHER) Channel Enable Register Offset */
#define DACC_CHER_CH0_Pos 0 /**< (DACC_CHER) Channel 0 Enable Position */
#define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */
#define DACC_CHER_CH0 DACC_CHER_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH0_Msk instead */
#define DACC_CHER_CH1_Pos 1 /**< (DACC_CHER) Channel 1 Enable Position */
#define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */
#define DACC_CHER_CH1 DACC_CHER_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH1_Msk instead */
#define DACC_CHER_MASK _U_(0x03) /**< \deprecated (DACC_CHER) Register MASK (Use DACC_CHER_Msk instead) */
#define DACC_CHER_Msk _U_(0x03) /**< (DACC_CHER) Register Mask */
#define DACC_CHER_CH_Pos 0 /**< (DACC_CHER Position) Channel x Enable */
#define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */
#define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos))
/* -------- DACC_CHDR : (DACC Offset: 0x14) (/W 32) Channel Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CH0:1; /**< bit: 0 Channel 0 Disable */
uint32_t CH1:1; /**< bit: 1 Channel 1 Disable */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t CH:2; /**< bit: 0..1 Channel x Disable */
uint32_t :30; /**< bit: 2..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_CHDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_CHDR_OFFSET (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */
#define DACC_CHDR_CH0_Pos 0 /**< (DACC_CHDR) Channel 0 Disable Position */
#define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */
#define DACC_CHDR_CH0 DACC_CHDR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH0_Msk instead */
#define DACC_CHDR_CH1_Pos 1 /**< (DACC_CHDR) Channel 1 Disable Position */
#define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */
#define DACC_CHDR_CH1 DACC_CHDR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH1_Msk instead */
#define DACC_CHDR_MASK _U_(0x03) /**< \deprecated (DACC_CHDR) Register MASK (Use DACC_CHDR_Msk instead) */
#define DACC_CHDR_Msk _U_(0x03) /**< (DACC_CHDR) Register Mask */
#define DACC_CHDR_CH_Pos 0 /**< (DACC_CHDR Position) Channel x Disable */
#define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */
#define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos))
/* -------- DACC_CHSR : (DACC Offset: 0x18) (R/ 32) Channel Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CH0:1; /**< bit: 0 Channel 0 Status */
uint32_t CH1:1; /**< bit: 1 Channel 1 Status */
uint32_t :6; /**< bit: 2..7 Reserved */
uint32_t DACRDY0:1; /**< bit: 8 DAC Ready Flag */
uint32_t DACRDY1:1; /**< bit: 9 DAC Ready Flag */
uint32_t :22; /**< bit: 10..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t CH:2; /**< bit: 0..1 Channel x Status */
uint32_t :6; /**< bit: 2..7 Reserved */
uint32_t DACRDY:2; /**< bit: 8..9 DAC Ready Flag */
uint32_t :22; /**< bit: 10..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_CHSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_CHSR_OFFSET (0x18) /**< (DACC_CHSR) Channel Status Register Offset */
#define DACC_CHSR_CH0_Pos 0 /**< (DACC_CHSR) Channel 0 Status Position */
#define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */
#define DACC_CHSR_CH0 DACC_CHSR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH0_Msk instead */
#define DACC_CHSR_CH1_Pos 1 /**< (DACC_CHSR) Channel 1 Status Position */
#define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */
#define DACC_CHSR_CH1 DACC_CHSR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH1_Msk instead */
#define DACC_CHSR_DACRDY0_Pos 8 /**< (DACC_CHSR) DAC Ready Flag Position */
#define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */
#define DACC_CHSR_DACRDY0 DACC_CHSR_DACRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY0_Msk instead */
#define DACC_CHSR_DACRDY1_Pos 9 /**< (DACC_CHSR) DAC Ready Flag Position */
#define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */
#define DACC_CHSR_DACRDY1 DACC_CHSR_DACRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY1_Msk instead */
#define DACC_CHSR_MASK _U_(0x303) /**< \deprecated (DACC_CHSR) Register MASK (Use DACC_CHSR_Msk instead) */
#define DACC_CHSR_Msk _U_(0x303) /**< (DACC_CHSR) Register Mask */
#define DACC_CHSR_CH_Pos 0 /**< (DACC_CHSR Position) Channel x Status */
#define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */
#define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos))
#define DACC_CHSR_DACRDY_Pos 8 /**< (DACC_CHSR Position) DAC Ready Flag */
#define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */
#define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos))
/* -------- DACC_CDR : (DACC Offset: 0x1c) (/W 32) Conversion Data Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA0:16; /**< bit: 0..15 Data to Convert for channel 0 */
uint32_t DATA1:16; /**< bit: 16..31 Data to Convert for channel 1 */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} DACC_CDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_CDR_OFFSET (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */
#define DACC_CDR_DATA0_Pos 0 /**< (DACC_CDR) Data to Convert for channel 0 Position */
#define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */
#define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))
#define DACC_CDR_DATA1_Pos 16 /**< (DACC_CDR) Data to Convert for channel 1 Position */
#define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */
#define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))
#define DACC_CDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (DACC_CDR) Register MASK (Use DACC_CDR_Msk instead) */
#define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */
/* -------- DACC_IER : (DACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Enable of channel 0 */
uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Enable of channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Enable of channel 0 */
uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Enable of channel 1 */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Enable of channel x */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Enable of channel x */
uint32_t :26; /**< bit: 6..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_IER_OFFSET (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */
#define DACC_IER_TXRDY0_Pos 0 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */
#define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */
#define DACC_IER_TXRDY0 DACC_IER_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY0_Msk instead */
#define DACC_IER_TXRDY1_Pos 1 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */
#define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */
#define DACC_IER_TXRDY1 DACC_IER_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY1_Msk instead */
#define DACC_IER_EOC0_Pos 4 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */
#define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */
#define DACC_IER_EOC0 DACC_IER_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC0_Msk instead */
#define DACC_IER_EOC1_Pos 5 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */
#define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */
#define DACC_IER_EOC1 DACC_IER_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC1_Msk instead */
#define DACC_IER_MASK _U_(0x33) /**< \deprecated (DACC_IER) Register MASK (Use DACC_IER_Msk instead) */
#define DACC_IER_Msk _U_(0x33) /**< (DACC_IER) Register Mask */
#define DACC_IER_TXRDY_Pos 0 /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */
#define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */
#define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos))
#define DACC_IER_EOC_Pos 4 /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */
#define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */
#define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos))
/* -------- DACC_IDR : (DACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Disable of channel 0 */
uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Disable of channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Disable of channel 0 */
uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Disable of channel 1 */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Disable of channel x */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Disable of channel x */
uint32_t :26; /**< bit: 6..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_IDR_OFFSET (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */
#define DACC_IDR_TXRDY0_Pos 0 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */
#define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */
#define DACC_IDR_TXRDY0 DACC_IDR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY0_Msk instead */
#define DACC_IDR_TXRDY1_Pos 1 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */
#define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */
#define DACC_IDR_TXRDY1 DACC_IDR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY1_Msk instead */
#define DACC_IDR_EOC0_Pos 4 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */
#define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */
#define DACC_IDR_EOC0 DACC_IDR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC0_Msk instead */
#define DACC_IDR_EOC1_Pos 5 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */
#define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */
#define DACC_IDR_EOC1 DACC_IDR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC1_Msk instead */
#define DACC_IDR_MASK _U_(0x33) /**< \deprecated (DACC_IDR) Register MASK (Use DACC_IDR_Msk instead) */
#define DACC_IDR_Msk _U_(0x33) /**< (DACC_IDR) Register Mask */
#define DACC_IDR_TXRDY_Pos 0 /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */
#define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */
#define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos))
#define DACC_IDR_EOC_Pos 4 /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */
#define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */
#define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos))
/* -------- DACC_IMR : (DACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Mask of channel 0 */
uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Mask of channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Mask of channel 0 */
uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Mask of channel 1 */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Mask of channel x */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Mask of channel x */
uint32_t :26; /**< bit: 6..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_IMR_OFFSET (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */
#define DACC_IMR_TXRDY0_Pos 0 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */
#define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */
#define DACC_IMR_TXRDY0 DACC_IMR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY0_Msk instead */
#define DACC_IMR_TXRDY1_Pos 1 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */
#define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */
#define DACC_IMR_TXRDY1 DACC_IMR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY1_Msk instead */
#define DACC_IMR_EOC0_Pos 4 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */
#define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */
#define DACC_IMR_EOC0 DACC_IMR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC0_Msk instead */
#define DACC_IMR_EOC1_Pos 5 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */
#define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */
#define DACC_IMR_EOC1 DACC_IMR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC1_Msk instead */
#define DACC_IMR_MASK _U_(0x33) /**< \deprecated (DACC_IMR) Register MASK (Use DACC_IMR_Msk instead) */
#define DACC_IMR_Msk _U_(0x33) /**< (DACC_IMR) Register Mask */
#define DACC_IMR_TXRDY_Pos 0 /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */
#define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */
#define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos))
#define DACC_IMR_EOC_Pos 4 /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */
#define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */
#define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos))
/* -------- DACC_ISR : (DACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Flag of channel 0 */
uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Flag of channel 1 */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Flag of channel 0 */
uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Flag of channel 1 */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Flag of channel x */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Flag of channel x */
uint32_t :26; /**< bit: 6..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} DACC_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_ISR_OFFSET (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */
#define DACC_ISR_TXRDY0_Pos 0 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */
#define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */
#define DACC_ISR_TXRDY0 DACC_ISR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY0_Msk instead */
#define DACC_ISR_TXRDY1_Pos 1 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */
#define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */
#define DACC_ISR_TXRDY1 DACC_ISR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY1_Msk instead */
#define DACC_ISR_EOC0_Pos 4 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */
#define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */
#define DACC_ISR_EOC0 DACC_ISR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC0_Msk instead */
#define DACC_ISR_EOC1_Pos 5 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */
#define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */
#define DACC_ISR_EOC1 DACC_ISR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC1_Msk instead */
#define DACC_ISR_MASK _U_(0x33) /**< \deprecated (DACC_ISR) Register MASK (Use DACC_ISR_Msk instead) */
#define DACC_ISR_Msk _U_(0x33) /**< (DACC_ISR) Register Mask */
#define DACC_ISR_TXRDY_Pos 0 /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */
#define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */
#define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos))
#define DACC_ISR_EOC_Pos 4 /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */
#define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */
#define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos))
/* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IBCTLCH0:2; /**< bit: 0..1 Analog Output Current Control */
uint32_t IBCTLCH1:2; /**< bit: 2..3 Analog Output Current Control */
uint32_t :28; /**< bit: 4..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} DACC_ACR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_ACR_OFFSET (0x94) /**< (DACC_ACR) Analog Current Register Offset */
#define DACC_ACR_IBCTLCH0_Pos 0 /**< (DACC_ACR) Analog Output Current Control Position */
#define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */
#define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))
#define DACC_ACR_IBCTLCH1_Pos 2 /**< (DACC_ACR) Analog Output Current Control Position */
#define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */
#define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))
#define DACC_ACR_MASK _U_(0x0F) /**< \deprecated (DACC_ACR) Register MASK (Use DACC_ACR_Msk instead) */
#define DACC_ACR_Msk _U_(0x0F) /**< (DACC_ACR) Register Mask */
/* -------- DACC_WPMR : (DACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protect Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} DACC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_WPMR_OFFSET (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */
#define DACC_WPMR_WPEN_Pos 0 /**< (DACC_WPMR) Write Protection Enable Position */
#define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */
#define DACC_WPMR_WPEN DACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPMR_WPEN_Msk instead */
#define DACC_WPMR_WPKEY_Pos 8 /**< (DACC_WPMR) Write Protect Key Position */
#define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */
#define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))
#define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
#define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */
#define DACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (DACC_WPMR) Register MASK (Use DACC_WPMR_Msk instead) */
#define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */
/* -------- DACC_WPSR : (DACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} DACC_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DACC_WPSR_OFFSET (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */
#define DACC_WPSR_WPVS_Pos 0 /**< (DACC_WPSR) Write Protection Violation Status Position */
#define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */
#define DACC_WPSR_WPVS DACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPSR_WPVS_Msk instead */
#define DACC_WPSR_WPVSRC_Pos 8 /**< (DACC_WPSR) Write Protection Violation Source Position */
#define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */
#define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos))
#define DACC_WPSR_MASK _U_(0xFF01) /**< \deprecated (DACC_WPSR) Register MASK (Use DACC_WPSR_Msk instead) */
#define DACC_WPSR_Msk _U_(0xFF01) /**< (DACC_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief DACC hardware registers */
typedef struct {
__O uint32_t DACC_CR; /**< (DACC Offset: 0x00) Control Register */
__IO uint32_t DACC_MR; /**< (DACC Offset: 0x04) Mode Register */
__IO uint32_t DACC_TRIGR; /**< (DACC Offset: 0x08) Trigger Register */
RoReg8 Reserved1[0x4];
__O uint32_t DACC_CHER; /**< (DACC Offset: 0x10) Channel Enable Register */
__O uint32_t DACC_CHDR; /**< (DACC Offset: 0x14) Channel Disable Register */
__I uint32_t DACC_CHSR; /**< (DACC Offset: 0x18) Channel Status Register */
__O uint32_t DACC_CDR[2]; /**< (DACC Offset: 0x1C) Conversion Data Register 0 */
__O uint32_t DACC_IER; /**< (DACC Offset: 0x24) Interrupt Enable Register */
__O uint32_t DACC_IDR; /**< (DACC Offset: 0x28) Interrupt Disable Register */
__I uint32_t DACC_IMR; /**< (DACC Offset: 0x2C) Interrupt Mask Register */
__I uint32_t DACC_ISR; /**< (DACC Offset: 0x30) Interrupt Status Register */
RoReg8 Reserved2[0x60];
__IO uint32_t DACC_ACR; /**< (DACC Offset: 0x94) Analog Current Register */
RoReg8 Reserved3[0x4C];
__IO uint32_t DACC_WPMR; /**< (DACC Offset: 0xE4) Write Protection Mode Register */
__I uint32_t DACC_WPSR; /**< (DACC Offset: 0xE8) Write Protection Status Register */
} Dacc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief DACC hardware registers */
typedef struct {
__O DACC_CR_Type DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO DACC_MR_Type DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__IO DACC_TRIGR_Type DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */
__I uint32_t Reserved1[1];
__O DACC_CHER_Type DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */
__O DACC_CHDR_Type DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */
__I DACC_CHSR_Type DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */
__O DACC_CDR_Type DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */
__O DACC_IER_Type DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
__O DACC_IDR_Type DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
__I DACC_IMR_Type DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
__I DACC_ISR_Type DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */
__I uint32_t Reserved2[24];
__IO DACC_ACR_Type DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */
__I uint32_t Reserved3[19];
__IO DACC_WPMR_Type DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I DACC_WPSR_Type DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Dacc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Digital-to-Analog Converter Controller */
#endif /* _SAME70_DACC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for EFC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_EFC_COMPONENT_H_
#define _SAME70_EFC_COMPONENT_H_
#define _SAME70_EFC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Embedded Flash Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EFC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define EFC_6450 /**< (EFC) Module ID */
#define REV_EFC X /**< (EFC) Module revision */
/* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FRDY:1; /**< bit: 0 Flash Ready Interrupt Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t FWS:4; /**< bit: 8..11 Flash Wait State */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t SCOD:1; /**< bit: 16 Sequential Code Optimization Disable */
uint32_t :9; /**< bit: 17..25 Reserved */
uint32_t CLOE:1; /**< bit: 26 Code Loop Optimization Enable */
uint32_t :5; /**< bit: 27..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} EEFC_FMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EEFC_FMR_OFFSET (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */
#define EEFC_FMR_FRDY_Pos 0 /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */
#define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */
#define EEFC_FMR_FRDY EEFC_FMR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_FRDY_Msk instead */
#define EEFC_FMR_FWS_Pos 8 /**< (EEFC_FMR) Flash Wait State Position */
#define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */
#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))
#define EEFC_FMR_SCOD_Pos 16 /**< (EEFC_FMR) Sequential Code Optimization Disable Position */
#define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */
#define EEFC_FMR_SCOD EEFC_FMR_SCOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_SCOD_Msk instead */
#define EEFC_FMR_CLOE_Pos 26 /**< (EEFC_FMR) Code Loop Optimization Enable Position */
#define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */
#define EEFC_FMR_CLOE EEFC_FMR_CLOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_CLOE_Msk instead */
#define EEFC_FMR_MASK _U_(0x4010F01) /**< \deprecated (EEFC_FMR) Register MASK (Use EEFC_FMR_Msk instead) */
#define EEFC_FMR_Msk _U_(0x4010F01) /**< (EEFC_FMR) Register Mask */
/* -------- EEFC_FCR : (EFC Offset: 0x04) (/W 32) EEFC Flash Command Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FCMD:8; /**< bit: 0..7 Flash Command */
uint32_t FARG:16; /**< bit: 8..23 Flash Command Argument */
uint32_t FKEY:8; /**< bit: 24..31 Flash Writing Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} EEFC_FCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EEFC_FCR_OFFSET (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */
#define EEFC_FCR_FCMD_Pos 0 /**< (EEFC_FCR) Flash Command Position */
#define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */
#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))
#define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */
#define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */
#define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */
#define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */
#define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */
#define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */
#define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */
#define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */
#define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */
#define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */
#define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */
#define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */
#define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */
#define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */
#define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */
#define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */
#define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */
#define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */
#define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */
#define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */
#define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */
#define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */
#define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */
#define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */
#define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */
#define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */
#define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */
#define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */
#define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */
#define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */
#define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */
#define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */
#define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */
#define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */
#define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */
#define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */
#define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */
#define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */
#define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */
#define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */
#define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */
#define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */
#define EEFC_FCR_FARG_Pos 8 /**< (EEFC_FCR) Flash Command Argument Position */
#define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */
#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))
#define EEFC_FCR_FKEY_Pos 24 /**< (EEFC_FCR) Flash Writing Protection Key Position */
#define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */
#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))
#define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
#define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */
#define EEFC_FCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FCR) Register MASK (Use EEFC_FCR_Msk instead) */
#define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */
/* -------- EEFC_FSR : (EFC Offset: 0x08) (R/ 32) EEFC Flash Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FRDY:1; /**< bit: 0 Flash Ready Status (cleared when Flash is busy) */
uint32_t FCMDE:1; /**< bit: 1 Flash Command Error Status (cleared on read or by writing EEFC_FCR) */
uint32_t FLOCKE:1; /**< bit: 2 Flash Lock Error Status (cleared on read) */
uint32_t FLERR:1; /**< bit: 3 Flash Error Status (cleared when a programming operation starts) */
uint32_t :12; /**< bit: 4..15 Reserved */
uint32_t UECCELSB:1; /**< bit: 16 Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
uint32_t MECCELSB:1; /**< bit: 17 Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
uint32_t UECCEMSB:1; /**< bit: 18 Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
uint32_t MECCEMSB:1; /**< bit: 19 Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
uint32_t :12; /**< bit: 20..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} EEFC_FSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EEFC_FSR_OFFSET (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */
#define EEFC_FSR_FRDY_Pos 0 /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */
#define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */
#define EEFC_FSR_FRDY EEFC_FSR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FRDY_Msk instead */
#define EEFC_FSR_FCMDE_Pos 1 /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */
#define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */
#define EEFC_FSR_FCMDE EEFC_FSR_FCMDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FCMDE_Msk instead */
#define EEFC_FSR_FLOCKE_Pos 2 /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */
#define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */
#define EEFC_FSR_FLOCKE EEFC_FSR_FLOCKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLOCKE_Msk instead */
#define EEFC_FSR_FLERR_Pos 3 /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */
#define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */
#define EEFC_FSR_FLERR EEFC_FSR_FLERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLERR_Msk instead */
#define EEFC_FSR_UECCELSB_Pos 16 /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */
#define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */
#define EEFC_FSR_UECCELSB EEFC_FSR_UECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCELSB_Msk instead */
#define EEFC_FSR_MECCELSB_Pos 17 /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */
#define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */
#define EEFC_FSR_MECCELSB EEFC_FSR_MECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCELSB_Msk instead */
#define EEFC_FSR_UECCEMSB_Pos 18 /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */
#define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */
#define EEFC_FSR_UECCEMSB EEFC_FSR_UECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCEMSB_Msk instead */
#define EEFC_FSR_MECCEMSB_Pos 19 /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */
#define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */
#define EEFC_FSR_MECCEMSB EEFC_FSR_MECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCEMSB_Msk instead */
#define EEFC_FSR_MASK _U_(0xF000F) /**< \deprecated (EEFC_FSR) Register MASK (Use EEFC_FSR_Msk instead) */
#define EEFC_FSR_Msk _U_(0xF000F) /**< (EEFC_FSR) Register Mask */
/* -------- EEFC_FRR : (EFC Offset: 0x0c) (R/ 32) EEFC Flash Result Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FVALUE:32; /**< bit: 0..31 Flash Result Value */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} EEFC_FRR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EEFC_FRR_OFFSET (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */
#define EEFC_FRR_FVALUE_Pos 0 /**< (EEFC_FRR) Flash Result Value Position */
#define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */
#define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos))
#define EEFC_FRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FRR) Register MASK (Use EEFC_FRR_Msk instead) */
#define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */
/* -------- EEFC_WPMR : (EFC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} EEFC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EEFC_WPMR_OFFSET (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */
#define EEFC_WPMR_WPEN_Pos 0 /**< (EEFC_WPMR) Write Protection Enable Position */
#define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */
#define EEFC_WPMR_WPEN EEFC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_WPMR_WPEN_Msk instead */
#define EEFC_WPMR_WPKEY_Pos 8 /**< (EEFC_WPMR) Write Protection Key Position */
#define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */
#define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))
#define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
#define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
#define EEFC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (EEFC_WPMR) Register MASK (Use EEFC_WPMR_Msk instead) */
#define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief EFC hardware registers */
typedef struct {
__IO uint32_t EEFC_FMR; /**< (EFC Offset: 0x00) EEFC Flash Mode Register */
__O uint32_t EEFC_FCR; /**< (EFC Offset: 0x04) EEFC Flash Command Register */
__I uint32_t EEFC_FSR; /**< (EFC Offset: 0x08) EEFC Flash Status Register */
__I uint32_t EEFC_FRR; /**< (EFC Offset: 0x0C) EEFC Flash Result Register */
RoReg8 Reserved1[0xD4];
__IO uint32_t EEFC_WPMR; /**< (EFC Offset: 0xE4) Write Protection Mode Register */
} Efc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief EFC hardware registers */
typedef struct {
__IO EEFC_FMR_Type EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */
__O EEFC_FCR_Type EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */
__I EEFC_FSR_Type EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */
__I EEFC_FRR_Type EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */
__I uint32_t Reserved1[53];
__IO EEFC_WPMR_Type EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
} Efc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Embedded Flash Controller */
#endif /* _SAME70_EFC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for GPBR
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_GPBR_COMPONENT_H_
#define _SAME70_GPBR_COMPONENT_H_
#define _SAME70_GPBR_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 General Purpose Backup Registers
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR GPBR */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define GPBR_6378 /**< (GPBR) Module ID */
#define REV_GPBR J /**< (GPBR) Module revision */
/* -------- GPBR_SYS_GPBR : (GPBR Offset: 0x00) (R/W 32) General Purpose Backup Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GPBR_VALUE:32; /**< bit: 0..31 Value of GPBR x */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} GPBR_SYS_GPBR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GPBR_SYS_GPBR_OFFSET (0x00) /**< (GPBR_SYS_GPBR) General Purpose Backup Register 0 Offset */
#define GPBR_SYS_GPBR_GPBR_VALUE_Pos 0 /**< (GPBR_SYS_GPBR) Value of GPBR x Position */
#define GPBR_SYS_GPBR_GPBR_VALUE_Msk (_U_(0xFFFFFFFF) << GPBR_SYS_GPBR_GPBR_VALUE_Pos) /**< (GPBR_SYS_GPBR) Value of GPBR x Mask */
#define GPBR_SYS_GPBR_GPBR_VALUE(value) (GPBR_SYS_GPBR_GPBR_VALUE_Msk & ((value) << GPBR_SYS_GPBR_GPBR_VALUE_Pos))
#define GPBR_SYS_GPBR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GPBR_SYS_GPBR) Register MASK (Use GPBR_SYS_GPBR_Msk instead) */
#define GPBR_SYS_GPBR_Msk _U_(0xFFFFFFFF) /**< (GPBR_SYS_GPBR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief GPBR hardware registers */
typedef struct {
__IO uint32_t SYS_GPBR[8]; /**< (GPBR Offset: 0x00) General Purpose Backup Register 0 */
} Gpbr;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief GPBR hardware registers */
typedef struct {
__IO GPBR_SYS_GPBR_Type SYS_GPBR[8]; /**< Offset: 0x00 (R/W 32) General Purpose Backup Register 0 */
} Gpbr;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of General Purpose Backup Registers */
#endif /* _SAME70_GPBR_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for I2SC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_I2SC_COMPONENT_H_
#define _SAME70_I2SC_COMPONENT_H_
#define _SAME70_I2SC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Inter-IC Sound Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR I2SC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define I2SC_11241 /**< (I2SC) Module ID */
#define REV_I2SC N /**< (I2SC) Module revision */
/* -------- I2SC_CR : (I2SC Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXEN:1; /**< bit: 0 Receiver Enable */
uint32_t RXDIS:1; /**< bit: 1 Receiver Disable */
uint32_t CKEN:1; /**< bit: 2 Clocks Enable */
uint32_t CKDIS:1; /**< bit: 3 Clocks Disable */
uint32_t TXEN:1; /**< bit: 4 Transmitter Enable */
uint32_t TXDIS:1; /**< bit: 5 Transmitter Disable */
uint32_t :1; /**< bit: 6 Reserved */
uint32_t SWRST:1; /**< bit: 7 Software Reset */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_CR_OFFSET (0x00) /**< (I2SC_CR) Control Register Offset */
#define I2SC_CR_RXEN_Pos 0 /**< (I2SC_CR) Receiver Enable Position */
#define I2SC_CR_RXEN_Msk (_U_(0x1) << I2SC_CR_RXEN_Pos) /**< (I2SC_CR) Receiver Enable Mask */
#define I2SC_CR_RXEN I2SC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXEN_Msk instead */
#define I2SC_CR_RXDIS_Pos 1 /**< (I2SC_CR) Receiver Disable Position */
#define I2SC_CR_RXDIS_Msk (_U_(0x1) << I2SC_CR_RXDIS_Pos) /**< (I2SC_CR) Receiver Disable Mask */
#define I2SC_CR_RXDIS I2SC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXDIS_Msk instead */
#define I2SC_CR_CKEN_Pos 2 /**< (I2SC_CR) Clocks Enable Position */
#define I2SC_CR_CKEN_Msk (_U_(0x1) << I2SC_CR_CKEN_Pos) /**< (I2SC_CR) Clocks Enable Mask */
#define I2SC_CR_CKEN I2SC_CR_CKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKEN_Msk instead */
#define I2SC_CR_CKDIS_Pos 3 /**< (I2SC_CR) Clocks Disable Position */
#define I2SC_CR_CKDIS_Msk (_U_(0x1) << I2SC_CR_CKDIS_Pos) /**< (I2SC_CR) Clocks Disable Mask */
#define I2SC_CR_CKDIS I2SC_CR_CKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKDIS_Msk instead */
#define I2SC_CR_TXEN_Pos 4 /**< (I2SC_CR) Transmitter Enable Position */
#define I2SC_CR_TXEN_Msk (_U_(0x1) << I2SC_CR_TXEN_Pos) /**< (I2SC_CR) Transmitter Enable Mask */
#define I2SC_CR_TXEN I2SC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXEN_Msk instead */
#define I2SC_CR_TXDIS_Pos 5 /**< (I2SC_CR) Transmitter Disable Position */
#define I2SC_CR_TXDIS_Msk (_U_(0x1) << I2SC_CR_TXDIS_Pos) /**< (I2SC_CR) Transmitter Disable Mask */
#define I2SC_CR_TXDIS I2SC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXDIS_Msk instead */
#define I2SC_CR_SWRST_Pos 7 /**< (I2SC_CR) Software Reset Position */
#define I2SC_CR_SWRST_Msk (_U_(0x1) << I2SC_CR_SWRST_Pos) /**< (I2SC_CR) Software Reset Mask */
#define I2SC_CR_SWRST I2SC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_SWRST_Msk instead */
#define I2SC_CR_MASK _U_(0xBF) /**< \deprecated (I2SC_CR) Register MASK (Use I2SC_CR_Msk instead) */
#define I2SC_CR_Msk _U_(0xBF) /**< (I2SC_CR) Register Mask */
/* -------- I2SC_MR : (I2SC Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MODE:1; /**< bit: 0 Inter-IC Sound Controller Mode */
uint32_t :1; /**< bit: 1 Reserved */
uint32_t DATALENGTH:3; /**< bit: 2..4 Data Word Length */
uint32_t :1; /**< bit: 5 Reserved */
uint32_t FORMAT:2; /**< bit: 6..7 Data Format */
uint32_t RXMONO:1; /**< bit: 8 Receive Mono */
uint32_t RXDMA:1; /**< bit: 9 Single or Multiple DMA Controller Channels for Receiver */
uint32_t RXLOOP:1; /**< bit: 10 Loopback Test Mode */
uint32_t :1; /**< bit: 11 Reserved */
uint32_t TXMONO:1; /**< bit: 12 Transmit Mono */
uint32_t TXDMA:1; /**< bit: 13 Single or Multiple DMA Controller Channels for Transmitter */
uint32_t TXSAME:1; /**< bit: 14 Transmit Data when Underrun */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t IMCKDIV:6; /**< bit: 16..21 Selected Clock to I2SC Master Clock Ratio */
uint32_t :2; /**< bit: 22..23 Reserved */
uint32_t IMCKFS:6; /**< bit: 24..29 Master Clock to fs Ratio */
uint32_t IMCKMODE:1; /**< bit: 30 Master Clock Mode */
uint32_t IWS:1; /**< bit: 31 I2SC_WS Slot Width */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_MR_OFFSET (0x04) /**< (I2SC_MR) Mode Register Offset */
#define I2SC_MR_MODE_Pos 0 /**< (I2SC_MR) Inter-IC Sound Controller Mode Position */
#define I2SC_MR_MODE_Msk (_U_(0x1) << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Inter-IC Sound Controller Mode Mask */
#define I2SC_MR_MODE I2SC_MR_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_MODE_Msk instead */
#define I2SC_MR_MODE_SLAVE_Val _U_(0x0) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. */
#define I2SC_MR_MODE_MASTER_Val _U_(0x1) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. */
#define I2SC_MR_MODE_SLAVE (I2SC_MR_MODE_SLAVE_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. Position */
#define I2SC_MR_MODE_MASTER (I2SC_MR_MODE_MASTER_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. Position */
#define I2SC_MR_DATALENGTH_Pos 2 /**< (I2SC_MR) Data Word Length Position */
#define I2SC_MR_DATALENGTH_Msk (_U_(0x7) << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data Word Length Mask */
#define I2SC_MR_DATALENGTH(value) (I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos))
#define I2SC_MR_DATALENGTH_32_BITS_Val _U_(0x0) /**< (I2SC_MR) Data length is set to 32 bits */
#define I2SC_MR_DATALENGTH_24_BITS_Val _U_(0x1) /**< (I2SC_MR) Data length is set to 24 bits */
#define I2SC_MR_DATALENGTH_20_BITS_Val _U_(0x2) /**< (I2SC_MR) Data length is set to 20 bits */
#define I2SC_MR_DATALENGTH_18_BITS_Val _U_(0x3) /**< (I2SC_MR) Data length is set to 18 bits */
#define I2SC_MR_DATALENGTH_16_BITS_Val _U_(0x4) /**< (I2SC_MR) Data length is set to 16 bits */
#define I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val _U_(0x5) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */
#define I2SC_MR_DATALENGTH_8_BITS_Val _U_(0x6) /**< (I2SC_MR) Data length is set to 8 bits */
#define I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val _U_(0x7) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */
#define I2SC_MR_DATALENGTH_32_BITS (I2SC_MR_DATALENGTH_32_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 32 bits Position */
#define I2SC_MR_DATALENGTH_24_BITS (I2SC_MR_DATALENGTH_24_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 24 bits Position */
#define I2SC_MR_DATALENGTH_20_BITS (I2SC_MR_DATALENGTH_20_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 20 bits Position */
#define I2SC_MR_DATALENGTH_18_BITS (I2SC_MR_DATALENGTH_18_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 18 bits Position */
#define I2SC_MR_DATALENGTH_16_BITS (I2SC_MR_DATALENGTH_16_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16 bits Position */
#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. Position */
#define I2SC_MR_DATALENGTH_8_BITS (I2SC_MR_DATALENGTH_8_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8 bits Position */
#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. Position */
#define I2SC_MR_FORMAT_Pos 6 /**< (I2SC_MR) Data Format Position */
#define I2SC_MR_FORMAT_Msk (_U_(0x3) << I2SC_MR_FORMAT_Pos) /**< (I2SC_MR) Data Format Mask */
#define I2SC_MR_FORMAT(value) (I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos))
#define I2SC_MR_FORMAT_I2S_Val _U_(0x0) /**< (I2SC_MR) I2S format, stereo with I2SC_WS low for left channel, and MSB of sample starting one I2SC_CK period after I2SC_WS edge */
#define I2SC_MR_FORMAT_LJ_Val _U_(0x1) /**< (I2SC_MR) Left-justified format, stereo with I2SC_WS high for left channel, and MSB of sample starting on I2SC_WS edge */
#define I2SC_MR_FORMAT_I2S (I2SC_MR_FORMAT_I2S_Val << I2SC_MR_FORMAT_Pos) /**< (I2SC_MR) I2S format, stereo with I2SC_WS low for left channel, and MSB of sample starting one I2SC_CK period after I2SC_WS edge Position */
#define I2SC_MR_FORMAT_LJ (I2SC_MR_FORMAT_LJ_Val << I2SC_MR_FORMAT_Pos) /**< (I2SC_MR) Left-justified format, stereo with I2SC_WS high for left channel, and MSB of sample starting on I2SC_WS edge Position */
#define I2SC_MR_RXMONO_Pos 8 /**< (I2SC_MR) Receive Mono Position */
#define I2SC_MR_RXMONO_Msk (_U_(0x1) << I2SC_MR_RXMONO_Pos) /**< (I2SC_MR) Receive Mono Mask */
#define I2SC_MR_RXMONO I2SC_MR_RXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXMONO_Msk instead */
#define I2SC_MR_RXDMA_Pos 9 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Position */
#define I2SC_MR_RXDMA_Msk (_U_(0x1) << I2SC_MR_RXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Mask */
#define I2SC_MR_RXDMA I2SC_MR_RXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXDMA_Msk instead */
#define I2SC_MR_RXLOOP_Pos 10 /**< (I2SC_MR) Loopback Test Mode Position */
#define I2SC_MR_RXLOOP_Msk (_U_(0x1) << I2SC_MR_RXLOOP_Pos) /**< (I2SC_MR) Loopback Test Mode Mask */
#define I2SC_MR_RXLOOP I2SC_MR_RXLOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXLOOP_Msk instead */
#define I2SC_MR_TXMONO_Pos 12 /**< (I2SC_MR) Transmit Mono Position */
#define I2SC_MR_TXMONO_Msk (_U_(0x1) << I2SC_MR_TXMONO_Pos) /**< (I2SC_MR) Transmit Mono Mask */
#define I2SC_MR_TXMONO I2SC_MR_TXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXMONO_Msk instead */
#define I2SC_MR_TXDMA_Pos 13 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Position */
#define I2SC_MR_TXDMA_Msk (_U_(0x1) << I2SC_MR_TXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Mask */
#define I2SC_MR_TXDMA I2SC_MR_TXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXDMA_Msk instead */
#define I2SC_MR_TXSAME_Pos 14 /**< (I2SC_MR) Transmit Data when Underrun Position */
#define I2SC_MR_TXSAME_Msk (_U_(0x1) << I2SC_MR_TXSAME_Pos) /**< (I2SC_MR) Transmit Data when Underrun Mask */
#define I2SC_MR_TXSAME I2SC_MR_TXSAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXSAME_Msk instead */
#define I2SC_MR_IMCKDIV_Pos 16 /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Position */
#define I2SC_MR_IMCKDIV_Msk (_U_(0x3F) << I2SC_MR_IMCKDIV_Pos) /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Mask */
#define I2SC_MR_IMCKDIV(value) (I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos))
#define I2SC_MR_IMCKFS_Pos 24 /**< (I2SC_MR) Master Clock to fs Ratio Position */
#define I2SC_MR_IMCKFS_Msk (_U_(0x3F) << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Master Clock to fs Ratio Mask */
#define I2SC_MR_IMCKFS(value) (I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos))
#define I2SC_MR_IMCKFS_M2SF32_Val _U_(0x0) /**< (I2SC_MR) Sample frequency ratio set to 32 */
#define I2SC_MR_IMCKFS_M2SF64_Val _U_(0x1) /**< (I2SC_MR) Sample frequency ratio set to 64 */
#define I2SC_MR_IMCKFS_M2SF96_Val _U_(0x2) /**< (I2SC_MR) Sample frequency ratio set to 96 */
#define I2SC_MR_IMCKFS_M2SF128_Val _U_(0x3) /**< (I2SC_MR) Sample frequency ratio set to 128 */
#define I2SC_MR_IMCKFS_M2SF192_Val _U_(0x5) /**< (I2SC_MR) Sample frequency ratio set to 192 */
#define I2SC_MR_IMCKFS_M2SF256_Val _U_(0x7) /**< (I2SC_MR) Sample frequency ratio set to 256 */
#define I2SC_MR_IMCKFS_M2SF384_Val _U_(0xB) /**< (I2SC_MR) Sample frequency ratio set to 384 */
#define I2SC_MR_IMCKFS_M2SF512_Val _U_(0xF) /**< (I2SC_MR) Sample frequency ratio set to 512 */
#define I2SC_MR_IMCKFS_M2SF768_Val _U_(0x17) /**< (I2SC_MR) Sample frequency ratio set to 768 */
#define I2SC_MR_IMCKFS_M2SF1024_Val _U_(0x1F) /**< (I2SC_MR) Sample frequency ratio set to 1024 */
#define I2SC_MR_IMCKFS_M2SF1536_Val _U_(0x2F) /**< (I2SC_MR) Sample frequency ratio set to 1536 */
#define I2SC_MR_IMCKFS_M2SF2048_Val _U_(0x3F) /**< (I2SC_MR) Sample frequency ratio set to 2048 */
#define I2SC_MR_IMCKFS_M2SF32 (I2SC_MR_IMCKFS_M2SF32_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 32 Position */
#define I2SC_MR_IMCKFS_M2SF64 (I2SC_MR_IMCKFS_M2SF64_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 64 Position */
#define I2SC_MR_IMCKFS_M2SF96 (I2SC_MR_IMCKFS_M2SF96_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 96 Position */
#define I2SC_MR_IMCKFS_M2SF128 (I2SC_MR_IMCKFS_M2SF128_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 128 Position */
#define I2SC_MR_IMCKFS_M2SF192 (I2SC_MR_IMCKFS_M2SF192_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 192 Position */
#define I2SC_MR_IMCKFS_M2SF256 (I2SC_MR_IMCKFS_M2SF256_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 256 Position */
#define I2SC_MR_IMCKFS_M2SF384 (I2SC_MR_IMCKFS_M2SF384_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 384 Position */
#define I2SC_MR_IMCKFS_M2SF512 (I2SC_MR_IMCKFS_M2SF512_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 512 Position */
#define I2SC_MR_IMCKFS_M2SF768 (I2SC_MR_IMCKFS_M2SF768_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 768 Position */
#define I2SC_MR_IMCKFS_M2SF1024 (I2SC_MR_IMCKFS_M2SF1024_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1024 Position */
#define I2SC_MR_IMCKFS_M2SF1536 (I2SC_MR_IMCKFS_M2SF1536_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1536 Position */
#define I2SC_MR_IMCKFS_M2SF2048 (I2SC_MR_IMCKFS_M2SF2048_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 2048 Position */
#define I2SC_MR_IMCKMODE_Pos 30 /**< (I2SC_MR) Master Clock Mode Position */
#define I2SC_MR_IMCKMODE_Msk (_U_(0x1) << I2SC_MR_IMCKMODE_Pos) /**< (I2SC_MR) Master Clock Mode Mask */
#define I2SC_MR_IMCKMODE I2SC_MR_IMCKMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IMCKMODE_Msk instead */
#define I2SC_MR_IWS_Pos 31 /**< (I2SC_MR) I2SC_WS Slot Width Position */
#define I2SC_MR_IWS_Msk (_U_(0x1) << I2SC_MR_IWS_Pos) /**< (I2SC_MR) I2SC_WS Slot Width Mask */
#define I2SC_MR_IWS I2SC_MR_IWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IWS_Msk instead */
#define I2SC_MR_MASK _U_(0xFF3F77DD) /**< \deprecated (I2SC_MR) Register MASK (Use I2SC_MR_Msk instead) */
#define I2SC_MR_Msk _U_(0xFF3F77DD) /**< (I2SC_MR) Register Mask */
/* -------- I2SC_SR : (I2SC Offset: 0x08) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXEN:1; /**< bit: 0 Receiver Enabled */
uint32_t RXRDY:1; /**< bit: 1 Receive Ready */
uint32_t RXOR:1; /**< bit: 2 Receive Overrun */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t TXEN:1; /**< bit: 4 Transmitter Enabled */
uint32_t TXRDY:1; /**< bit: 5 Transmit Ready */
uint32_t TXUR:1; /**< bit: 6 Transmit Underrun */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Channel */
uint32_t :10; /**< bit: 10..19 Reserved */
uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Channel */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_SR_OFFSET (0x08) /**< (I2SC_SR) Status Register Offset */
#define I2SC_SR_RXEN_Pos 0 /**< (I2SC_SR) Receiver Enabled Position */
#define I2SC_SR_RXEN_Msk (_U_(0x1) << I2SC_SR_RXEN_Pos) /**< (I2SC_SR) Receiver Enabled Mask */
#define I2SC_SR_RXEN I2SC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXEN_Msk instead */
#define I2SC_SR_RXRDY_Pos 1 /**< (I2SC_SR) Receive Ready Position */
#define I2SC_SR_RXRDY_Msk (_U_(0x1) << I2SC_SR_RXRDY_Pos) /**< (I2SC_SR) Receive Ready Mask */
#define I2SC_SR_RXRDY I2SC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXRDY_Msk instead */
#define I2SC_SR_RXOR_Pos 2 /**< (I2SC_SR) Receive Overrun Position */
#define I2SC_SR_RXOR_Msk (_U_(0x1) << I2SC_SR_RXOR_Pos) /**< (I2SC_SR) Receive Overrun Mask */
#define I2SC_SR_RXOR I2SC_SR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXOR_Msk instead */
#define I2SC_SR_TXEN_Pos 4 /**< (I2SC_SR) Transmitter Enabled Position */
#define I2SC_SR_TXEN_Msk (_U_(0x1) << I2SC_SR_TXEN_Pos) /**< (I2SC_SR) Transmitter Enabled Mask */
#define I2SC_SR_TXEN I2SC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXEN_Msk instead */
#define I2SC_SR_TXRDY_Pos 5 /**< (I2SC_SR) Transmit Ready Position */
#define I2SC_SR_TXRDY_Msk (_U_(0x1) << I2SC_SR_TXRDY_Pos) /**< (I2SC_SR) Transmit Ready Mask */
#define I2SC_SR_TXRDY I2SC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXRDY_Msk instead */
#define I2SC_SR_TXUR_Pos 6 /**< (I2SC_SR) Transmit Underrun Position */
#define I2SC_SR_TXUR_Msk (_U_(0x1) << I2SC_SR_TXUR_Pos) /**< (I2SC_SR) Transmit Underrun Mask */
#define I2SC_SR_TXUR I2SC_SR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXUR_Msk instead */
#define I2SC_SR_RXORCH_Pos 8 /**< (I2SC_SR) Receive Overrun Channel Position */
#define I2SC_SR_RXORCH_Msk (_U_(0x3) << I2SC_SR_RXORCH_Pos) /**< (I2SC_SR) Receive Overrun Channel Mask */
#define I2SC_SR_RXORCH(value) (I2SC_SR_RXORCH_Msk & ((value) << I2SC_SR_RXORCH_Pos))
#define I2SC_SR_TXURCH_Pos 20 /**< (I2SC_SR) Transmit Underrun Channel Position */
#define I2SC_SR_TXURCH_Msk (_U_(0x3) << I2SC_SR_TXURCH_Pos) /**< (I2SC_SR) Transmit Underrun Channel Mask */
#define I2SC_SR_TXURCH(value) (I2SC_SR_TXURCH_Msk & ((value) << I2SC_SR_TXURCH_Pos))
#define I2SC_SR_MASK _U_(0x300377) /**< \deprecated (I2SC_SR) Register MASK (Use I2SC_SR_Msk instead) */
#define I2SC_SR_Msk _U_(0x300377) /**< (I2SC_SR) Register Mask */
/* -------- I2SC_SCR : (I2SC Offset: 0x0c) (/W 32) Status Clear Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /**< bit: 0..1 Reserved */
uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Clear */
uint32_t :3; /**< bit: 3..5 Reserved */
uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Clear */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Clear */
uint32_t :10; /**< bit: 10..19 Reserved */
uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Clear */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_SCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_SCR_OFFSET (0x0C) /**< (I2SC_SCR) Status Clear Register Offset */
#define I2SC_SCR_RXOR_Pos 2 /**< (I2SC_SCR) Receive Overrun Status Clear Position */
#define I2SC_SCR_RXOR_Msk (_U_(0x1) << I2SC_SCR_RXOR_Pos) /**< (I2SC_SCR) Receive Overrun Status Clear Mask */
#define I2SC_SCR_RXOR I2SC_SCR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_RXOR_Msk instead */
#define I2SC_SCR_TXUR_Pos 6 /**< (I2SC_SCR) Transmit Underrun Status Clear Position */
#define I2SC_SCR_TXUR_Msk (_U_(0x1) << I2SC_SCR_TXUR_Pos) /**< (I2SC_SCR) Transmit Underrun Status Clear Mask */
#define I2SC_SCR_TXUR I2SC_SCR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_TXUR_Msk instead */
#define I2SC_SCR_RXORCH_Pos 8 /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Position */
#define I2SC_SCR_RXORCH_Msk (_U_(0x3) << I2SC_SCR_RXORCH_Pos) /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Mask */
#define I2SC_SCR_RXORCH(value) (I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos))
#define I2SC_SCR_TXURCH_Pos 20 /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Position */
#define I2SC_SCR_TXURCH_Msk (_U_(0x3) << I2SC_SCR_TXURCH_Pos) /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Mask */
#define I2SC_SCR_TXURCH(value) (I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos))
#define I2SC_SCR_MASK _U_(0x300344) /**< \deprecated (I2SC_SCR) Register MASK (Use I2SC_SCR_Msk instead) */
#define I2SC_SCR_Msk _U_(0x300344) /**< (I2SC_SCR) Register Mask */
/* -------- I2SC_SSR : (I2SC Offset: 0x10) (/W 32) Status Set Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /**< bit: 0..1 Reserved */
uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Set */
uint32_t :3; /**< bit: 3..5 Reserved */
uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Set */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Set */
uint32_t :10; /**< bit: 10..19 Reserved */
uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Set */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_SSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_SSR_OFFSET (0x10) /**< (I2SC_SSR) Status Set Register Offset */
#define I2SC_SSR_RXOR_Pos 2 /**< (I2SC_SSR) Receive Overrun Status Set Position */
#define I2SC_SSR_RXOR_Msk (_U_(0x1) << I2SC_SSR_RXOR_Pos) /**< (I2SC_SSR) Receive Overrun Status Set Mask */
#define I2SC_SSR_RXOR I2SC_SSR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_RXOR_Msk instead */
#define I2SC_SSR_TXUR_Pos 6 /**< (I2SC_SSR) Transmit Underrun Status Set Position */
#define I2SC_SSR_TXUR_Msk (_U_(0x1) << I2SC_SSR_TXUR_Pos) /**< (I2SC_SSR) Transmit Underrun Status Set Mask */
#define I2SC_SSR_TXUR I2SC_SSR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_TXUR_Msk instead */
#define I2SC_SSR_RXORCH_Pos 8 /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Position */
#define I2SC_SSR_RXORCH_Msk (_U_(0x3) << I2SC_SSR_RXORCH_Pos) /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Mask */
#define I2SC_SSR_RXORCH(value) (I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos))
#define I2SC_SSR_TXURCH_Pos 20 /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Position */
#define I2SC_SSR_TXURCH_Msk (_U_(0x3) << I2SC_SSR_TXURCH_Pos) /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Mask */
#define I2SC_SSR_TXURCH(value) (I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos))
#define I2SC_SSR_MASK _U_(0x300344) /**< \deprecated (I2SC_SSR) Register MASK (Use I2SC_SSR_Msk instead) */
#define I2SC_SSR_Msk _U_(0x300344) /**< (I2SC_SSR) Register Mask */
/* -------- I2SC_IER : (I2SC Offset: 0x14) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /**< bit: 0 Reserved */
uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Enable */
uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Enable */
uint32_t :2; /**< bit: 3..4 Reserved */
uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Enable */
uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Enable */
uint32_t :25; /**< bit: 7..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_IER_OFFSET (0x14) /**< (I2SC_IER) Interrupt Enable Register Offset */
#define I2SC_IER_RXRDY_Pos 1 /**< (I2SC_IER) Receiver Ready Interrupt Enable Position */
#define I2SC_IER_RXRDY_Msk (_U_(0x1) << I2SC_IER_RXRDY_Pos) /**< (I2SC_IER) Receiver Ready Interrupt Enable Mask */
#define I2SC_IER_RXRDY I2SC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXRDY_Msk instead */
#define I2SC_IER_RXOR_Pos 2 /**< (I2SC_IER) Receiver Overrun Interrupt Enable Position */
#define I2SC_IER_RXOR_Msk (_U_(0x1) << I2SC_IER_RXOR_Pos) /**< (I2SC_IER) Receiver Overrun Interrupt Enable Mask */
#define I2SC_IER_RXOR I2SC_IER_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXOR_Msk instead */
#define I2SC_IER_TXRDY_Pos 5 /**< (I2SC_IER) Transmit Ready Interrupt Enable Position */
#define I2SC_IER_TXRDY_Msk (_U_(0x1) << I2SC_IER_TXRDY_Pos) /**< (I2SC_IER) Transmit Ready Interrupt Enable Mask */
#define I2SC_IER_TXRDY I2SC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXRDY_Msk instead */
#define I2SC_IER_TXUR_Pos 6 /**< (I2SC_IER) Transmit Underflow Interrupt Enable Position */
#define I2SC_IER_TXUR_Msk (_U_(0x1) << I2SC_IER_TXUR_Pos) /**< (I2SC_IER) Transmit Underflow Interrupt Enable Mask */
#define I2SC_IER_TXUR I2SC_IER_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXUR_Msk instead */
#define I2SC_IER_MASK _U_(0x66) /**< \deprecated (I2SC_IER) Register MASK (Use I2SC_IER_Msk instead) */
#define I2SC_IER_Msk _U_(0x66) /**< (I2SC_IER) Register Mask */
/* -------- I2SC_IDR : (I2SC Offset: 0x18) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /**< bit: 0 Reserved */
uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */
uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */
uint32_t :2; /**< bit: 3..4 Reserved */
uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */
uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */
uint32_t :25; /**< bit: 7..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_IDR_OFFSET (0x18) /**< (I2SC_IDR) Interrupt Disable Register Offset */
#define I2SC_IDR_RXRDY_Pos 1 /**< (I2SC_IDR) Receiver Ready Interrupt Disable Position */
#define I2SC_IDR_RXRDY_Msk (_U_(0x1) << I2SC_IDR_RXRDY_Pos) /**< (I2SC_IDR) Receiver Ready Interrupt Disable Mask */
#define I2SC_IDR_RXRDY I2SC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXRDY_Msk instead */
#define I2SC_IDR_RXOR_Pos 2 /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Position */
#define I2SC_IDR_RXOR_Msk (_U_(0x1) << I2SC_IDR_RXOR_Pos) /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Mask */
#define I2SC_IDR_RXOR I2SC_IDR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXOR_Msk instead */
#define I2SC_IDR_TXRDY_Pos 5 /**< (I2SC_IDR) Transmit Ready Interrupt Disable Position */
#define I2SC_IDR_TXRDY_Msk (_U_(0x1) << I2SC_IDR_TXRDY_Pos) /**< (I2SC_IDR) Transmit Ready Interrupt Disable Mask */
#define I2SC_IDR_TXRDY I2SC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXRDY_Msk instead */
#define I2SC_IDR_TXUR_Pos 6 /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Position */
#define I2SC_IDR_TXUR_Msk (_U_(0x1) << I2SC_IDR_TXUR_Pos) /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Mask */
#define I2SC_IDR_TXUR I2SC_IDR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXUR_Msk instead */
#define I2SC_IDR_MASK _U_(0x66) /**< \deprecated (I2SC_IDR) Register MASK (Use I2SC_IDR_Msk instead) */
#define I2SC_IDR_Msk _U_(0x66) /**< (I2SC_IDR) Register Mask */
/* -------- I2SC_IMR : (I2SC Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /**< bit: 0 Reserved */
uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */
uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */
uint32_t :2; /**< bit: 3..4 Reserved */
uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */
uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */
uint32_t :25; /**< bit: 7..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_IMR_OFFSET (0x1C) /**< (I2SC_IMR) Interrupt Mask Register Offset */
#define I2SC_IMR_RXRDY_Pos 1 /**< (I2SC_IMR) Receiver Ready Interrupt Disable Position */
#define I2SC_IMR_RXRDY_Msk (_U_(0x1) << I2SC_IMR_RXRDY_Pos) /**< (I2SC_IMR) Receiver Ready Interrupt Disable Mask */
#define I2SC_IMR_RXRDY I2SC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXRDY_Msk instead */
#define I2SC_IMR_RXOR_Pos 2 /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Position */
#define I2SC_IMR_RXOR_Msk (_U_(0x1) << I2SC_IMR_RXOR_Pos) /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Mask */
#define I2SC_IMR_RXOR I2SC_IMR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXOR_Msk instead */
#define I2SC_IMR_TXRDY_Pos 5 /**< (I2SC_IMR) Transmit Ready Interrupt Disable Position */
#define I2SC_IMR_TXRDY_Msk (_U_(0x1) << I2SC_IMR_TXRDY_Pos) /**< (I2SC_IMR) Transmit Ready Interrupt Disable Mask */
#define I2SC_IMR_TXRDY I2SC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXRDY_Msk instead */
#define I2SC_IMR_TXUR_Pos 6 /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Position */
#define I2SC_IMR_TXUR_Msk (_U_(0x1) << I2SC_IMR_TXUR_Pos) /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Mask */
#define I2SC_IMR_TXUR I2SC_IMR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXUR_Msk instead */
#define I2SC_IMR_MASK _U_(0x66) /**< \deprecated (I2SC_IMR) Register MASK (Use I2SC_IMR_Msk instead) */
#define I2SC_IMR_Msk _U_(0x66) /**< (I2SC_IMR) Register Mask */
/* -------- I2SC_RHR : (I2SC Offset: 0x20) (R/ 32) Receiver Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHR:32; /**< bit: 0..31 Receiver Holding Register */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_RHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_RHR_OFFSET (0x20) /**< (I2SC_RHR) Receiver Holding Register Offset */
#define I2SC_RHR_RHR_Pos 0 /**< (I2SC_RHR) Receiver Holding Register Position */
#define I2SC_RHR_RHR_Msk (_U_(0xFFFFFFFF) << I2SC_RHR_RHR_Pos) /**< (I2SC_RHR) Receiver Holding Register Mask */
#define I2SC_RHR_RHR(value) (I2SC_RHR_RHR_Msk & ((value) << I2SC_RHR_RHR_Pos))
#define I2SC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_RHR) Register MASK (Use I2SC_RHR_Msk instead) */
#define I2SC_RHR_Msk _U_(0xFFFFFFFF) /**< (I2SC_RHR) Register Mask */
/* -------- I2SC_THR : (I2SC Offset: 0x24) (/W 32) Transmitter Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t THR:32; /**< bit: 0..31 Transmitter Holding Register */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} I2SC_THR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2SC_THR_OFFSET (0x24) /**< (I2SC_THR) Transmitter Holding Register Offset */
#define I2SC_THR_THR_Pos 0 /**< (I2SC_THR) Transmitter Holding Register Position */
#define I2SC_THR_THR_Msk (_U_(0xFFFFFFFF) << I2SC_THR_THR_Pos) /**< (I2SC_THR) Transmitter Holding Register Mask */
#define I2SC_THR_THR(value) (I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos))
#define I2SC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_THR) Register MASK (Use I2SC_THR_Msk instead) */
#define I2SC_THR_Msk _U_(0xFFFFFFFF) /**< (I2SC_THR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief I2SC hardware registers */
typedef struct {
__O uint32_t I2SC_CR; /**< (I2SC Offset: 0x00) Control Register */
__IO uint32_t I2SC_MR; /**< (I2SC Offset: 0x04) Mode Register */
__I uint32_t I2SC_SR; /**< (I2SC Offset: 0x08) Status Register */
__O uint32_t I2SC_SCR; /**< (I2SC Offset: 0x0C) Status Clear Register */
__O uint32_t I2SC_SSR; /**< (I2SC Offset: 0x10) Status Set Register */
__O uint32_t I2SC_IER; /**< (I2SC Offset: 0x14) Interrupt Enable Register */
__O uint32_t I2SC_IDR; /**< (I2SC Offset: 0x18) Interrupt Disable Register */
__I uint32_t I2SC_IMR; /**< (I2SC Offset: 0x1C) Interrupt Mask Register */
__I uint32_t I2SC_RHR; /**< (I2SC Offset: 0x20) Receiver Holding Register */
__O uint32_t I2SC_THR; /**< (I2SC Offset: 0x24) Transmitter Holding Register */
} I2sc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief I2SC hardware registers */
typedef struct {
__O I2SC_CR_Type I2SC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO I2SC_MR_Type I2SC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I I2SC_SR_Type I2SC_SR; /**< Offset: 0x08 (R/ 32) Status Register */
__O I2SC_SCR_Type I2SC_SCR; /**< Offset: 0x0C ( /W 32) Status Clear Register */
__O I2SC_SSR_Type I2SC_SSR; /**< Offset: 0x10 ( /W 32) Status Set Register */
__O I2SC_IER_Type I2SC_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */
__O I2SC_IDR_Type I2SC_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */
__I I2SC_IMR_Type I2SC_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */
__I I2SC_RHR_Type I2SC_RHR; /**< Offset: 0x20 (R/ 32) Receiver Holding Register */
__O I2SC_THR_Type I2SC_THR; /**< Offset: 0x24 ( /W 32) Transmitter Holding Register */
} I2sc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Inter-IC Sound Controller */
#endif /* _SAME70_I2SC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for ICM
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_ICM_COMPONENT_H_
#define _SAME70_ICM_COMPONENT_H_
#define _SAME70_ICM_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Integrity Check Monitor
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ICM */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define ICM_11105 /**< (ICM) Module ID */
#define REV_ICM H /**< (ICM) Module revision */
/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WBDIS:1; /**< bit: 0 Write Back Disable */
uint32_t EOMDIS:1; /**< bit: 1 End of Monitoring Disable */
uint32_t SLBDIS:1; /**< bit: 2 Secondary List Branching Disable */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t BBC:4; /**< bit: 4..7 Bus Burden Control */
uint32_t ASCD:1; /**< bit: 8 Automatic Switch To Compare Digest */
uint32_t DUALBUFF:1; /**< bit: 9 Dual Input Buffer */
uint32_t :2; /**< bit: 10..11 Reserved */
uint32_t UIHASH:1; /**< bit: 12 User Initial Hash Value */
uint32_t UALGO:3; /**< bit: 13..15 User SHA Algorithm */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_CFG_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_CFG_OFFSET (0x00) /**< (ICM_CFG) Configuration Register Offset */
#define ICM_CFG_WBDIS_Pos 0 /**< (ICM_CFG) Write Back Disable Position */
#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */
#define ICM_CFG_WBDIS ICM_CFG_WBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_WBDIS_Msk instead */
#define ICM_CFG_EOMDIS_Pos 1 /**< (ICM_CFG) End of Monitoring Disable Position */
#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */
#define ICM_CFG_EOMDIS ICM_CFG_EOMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_EOMDIS_Msk instead */
#define ICM_CFG_SLBDIS_Pos 2 /**< (ICM_CFG) Secondary List Branching Disable Position */
#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */
#define ICM_CFG_SLBDIS ICM_CFG_SLBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_SLBDIS_Msk instead */
#define ICM_CFG_BBC_Pos 4 /**< (ICM_CFG) Bus Burden Control Position */
#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */
#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
#define ICM_CFG_ASCD_Pos 8 /**< (ICM_CFG) Automatic Switch To Compare Digest Position */
#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */
#define ICM_CFG_ASCD ICM_CFG_ASCD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_ASCD_Msk instead */
#define ICM_CFG_DUALBUFF_Pos 9 /**< (ICM_CFG) Dual Input Buffer Position */
#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */
#define ICM_CFG_DUALBUFF ICM_CFG_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_DUALBUFF_Msk instead */
#define ICM_CFG_UIHASH_Pos 12 /**< (ICM_CFG) User Initial Hash Value Position */
#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */
#define ICM_CFG_UIHASH ICM_CFG_UIHASH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_UIHASH_Msk instead */
#define ICM_CFG_UALGO_Pos 13 /**< (ICM_CFG) User SHA Algorithm Position */
#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */
#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */
#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */
#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */
#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */
#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */
#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */
#define ICM_CFG_MASK _U_(0xF3F7) /**< \deprecated (ICM_CFG) Register MASK (Use ICM_CFG_Msk instead) */
#define ICM_CFG_Msk _U_(0xF3F7) /**< (ICM_CFG) Register Mask */
/* -------- ICM_CTRL : (ICM Offset: 0x04) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /**< bit: 0 ICM Enable */
uint32_t DISABLE:1; /**< bit: 1 ICM Disable Register */
uint32_t SWRST:1; /**< bit: 2 Software Reset */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t REHASH:4; /**< bit: 4..7 Recompute Internal Hash */
uint32_t RMDIS:4; /**< bit: 8..11 Region Monitoring Disable */
uint32_t RMEN:4; /**< bit: 12..15 Region Monitoring Enable */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_CTRL_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_CTRL_OFFSET (0x04) /**< (ICM_CTRL) Control Register Offset */
#define ICM_CTRL_ENABLE_Pos 0 /**< (ICM_CTRL) ICM Enable Position */
#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */
#define ICM_CTRL_ENABLE ICM_CTRL_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_ENABLE_Msk instead */
#define ICM_CTRL_DISABLE_Pos 1 /**< (ICM_CTRL) ICM Disable Register Position */
#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */
#define ICM_CTRL_DISABLE ICM_CTRL_DISABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_DISABLE_Msk instead */
#define ICM_CTRL_SWRST_Pos 2 /**< (ICM_CTRL) Software Reset Position */
#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */
#define ICM_CTRL_SWRST ICM_CTRL_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_SWRST_Msk instead */
#define ICM_CTRL_REHASH_Pos 4 /**< (ICM_CTRL) Recompute Internal Hash Position */
#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */
#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
#define ICM_CTRL_RMDIS_Pos 8 /**< (ICM_CTRL) Region Monitoring Disable Position */
#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */
#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
#define ICM_CTRL_RMEN_Pos 12 /**< (ICM_CTRL) Region Monitoring Enable Position */
#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */
#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
#define ICM_CTRL_MASK _U_(0xFFF7) /**< \deprecated (ICM_CTRL) Register MASK (Use ICM_CTRL_Msk instead) */
#define ICM_CTRL_Msk _U_(0xFFF7) /**< (ICM_CTRL) Register Mask */
/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /**< bit: 0 ICM Controller Enable Register */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t RAWRMDIS:4; /**< bit: 8..11 Region Monitoring Disabled Raw Status */
uint32_t RMDIS:4; /**< bit: 12..15 Region Monitoring Disabled Status */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_SR_OFFSET (0x08) /**< (ICM_SR) Status Register Offset */
#define ICM_SR_ENABLE_Pos 0 /**< (ICM_SR) ICM Controller Enable Register Position */
#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */
#define ICM_SR_ENABLE ICM_SR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_SR_ENABLE_Msk instead */
#define ICM_SR_RAWRMDIS_Pos 8 /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */
#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */
#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
#define ICM_SR_RMDIS_Pos 12 /**< (ICM_SR) Region Monitoring Disabled Status Position */
#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */
#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
#define ICM_SR_MASK _U_(0xFF01) /**< \deprecated (ICM_SR) Register MASK (Use ICM_SR_Msk instead) */
#define ICM_SR_Msk _U_(0xFF01) /**< (ICM_SR) Register Mask */
/* -------- ICM_IER : (ICM Offset: 0x10) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Enable */
uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Enable */
uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Enable */
uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition detected Interrupt Enable */
uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Enable */
uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */
uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Enable */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IER_OFFSET (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */
#define ICM_IER_RHC_Pos 0 /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */
#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */
#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
#define ICM_IER_RDM_Pos 4 /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */
#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */
#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
#define ICM_IER_RBE_Pos 8 /**< (ICM_IER) Region Bus Error Interrupt Enable Position */
#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */
#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
#define ICM_IER_RWC_Pos 12 /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */
#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */
#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
#define ICM_IER_REC_Pos 16 /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */
#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */
#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
#define ICM_IER_RSU_Pos 20 /**< (ICM_IER) Region Status Updated Interrupt Disable Position */
#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */
#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
#define ICM_IER_URAD_Pos 24 /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */
#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */
#define ICM_IER_URAD ICM_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IER_URAD_Msk instead */
#define ICM_IER_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IER) Register MASK (Use ICM_IER_Msk instead) */
#define ICM_IER_Msk _U_(0x1FFFFFF) /**< (ICM_IER) Register Mask */
/* -------- ICM_IDR : (ICM Offset: 0x14) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Disable */
uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Disable */
uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Disable */
uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */
uint32_t REC:4; /**< bit: 16..19 Region End bit Condition detected Interrupt Disable */
uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */
uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Disable */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IDR_OFFSET (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */
#define ICM_IDR_RHC_Pos 0 /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */
#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */
#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
#define ICM_IDR_RDM_Pos 4 /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */
#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */
#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
#define ICM_IDR_RBE_Pos 8 /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */
#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */
#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
#define ICM_IDR_RWC_Pos 12 /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */
#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */
#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
#define ICM_IDR_REC_Pos 16 /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */
#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */
#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
#define ICM_IDR_RSU_Pos 20 /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */
#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */
#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
#define ICM_IDR_URAD_Pos 24 /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */
#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */
#define ICM_IDR_URAD ICM_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IDR_URAD_Msk instead */
#define ICM_IDR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IDR) Register MASK (Use ICM_IDR_Msk instead) */
#define ICM_IDR_Msk _U_(0x1FFFFFF) /**< (ICM_IDR) Register Mask */
/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Mask */
uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Mask */
uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Mask */
uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */
uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Mask */
uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Mask */
uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Mask */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IMR_OFFSET (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */
#define ICM_IMR_RHC_Pos 0 /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */
#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */
#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
#define ICM_IMR_RDM_Pos 4 /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */
#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */
#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
#define ICM_IMR_RBE_Pos 8 /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */
#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */
#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
#define ICM_IMR_RWC_Pos 12 /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */
#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */
#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
#define ICM_IMR_REC_Pos 16 /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */
#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */
#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
#define ICM_IMR_RSU_Pos 20 /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */
#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */
#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
#define ICM_IMR_URAD_Pos 24 /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */
#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */
#define ICM_IMR_URAD ICM_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IMR_URAD_Msk instead */
#define ICM_IMR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IMR) Register MASK (Use ICM_IMR_Msk instead) */
#define ICM_IMR_Msk _U_(0x1FFFFFF) /**< (ICM_IMR) Register Mask */
/* -------- ICM_ISR : (ICM Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed */
uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch */
uint32_t RBE:4; /**< bit: 8..11 Region Bus Error */
uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected */
uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected */
uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Detected */
uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Status */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_ISR_OFFSET (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */
#define ICM_ISR_RHC_Pos 0 /**< (ICM_ISR) Region Hash Completed Position */
#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */
#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
#define ICM_ISR_RDM_Pos 4 /**< (ICM_ISR) Region Digest Mismatch Position */
#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */
#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
#define ICM_ISR_RBE_Pos 8 /**< (ICM_ISR) Region Bus Error Position */
#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */
#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
#define ICM_ISR_RWC_Pos 12 /**< (ICM_ISR) Region Wrap Condition Detected Position */
#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */
#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
#define ICM_ISR_REC_Pos 16 /**< (ICM_ISR) Region End bit Condition Detected Position */
#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */
#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
#define ICM_ISR_RSU_Pos 20 /**< (ICM_ISR) Region Status Updated Detected Position */
#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */
#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
#define ICM_ISR_URAD_Pos 24 /**< (ICM_ISR) Undefined Register Access Detection Status Position */
#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */
#define ICM_ISR_URAD ICM_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_ISR_URAD_Msk instead */
#define ICM_ISR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_ISR) Register MASK (Use ICM_ISR_Msk instead) */
#define ICM_ISR_Msk _U_(0x1FFFFFF) /**< (ICM_ISR) Register Mask */
/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t URAT:3; /**< bit: 0..2 Undefined Register Access Trace */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_UASR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_UASR_OFFSET (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */
#define ICM_UASR_URAT_Pos 0 /**< (ICM_UASR) Undefined Register Access Trace Position */
#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */
#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
#define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */
#define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */
#define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */
#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */
#define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */
#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */
#define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */
#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */
#define ICM_UASR_MASK _U_(0x07) /**< \deprecated (ICM_UASR) Register MASK (Use ICM_UASR_Msk instead) */
#define ICM_UASR_Msk _U_(0x07) /**< (ICM_UASR) Register Mask */
/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :6; /**< bit: 0..5 Reserved */
uint32_t DASA:26; /**< bit: 6..31 Descriptor Area Start Address */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_DSCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_DSCR_OFFSET (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */
#define ICM_DSCR_DASA_Pos 6 /**< (ICM_DSCR) Descriptor Area Start Address Position */
#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */
#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \deprecated (ICM_DSCR) Register MASK (Use ICM_DSCR_Msk instead) */
#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */
/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :7; /**< bit: 0..6 Reserved */
uint32_t HASA:25; /**< bit: 7..31 Hash Area Start Address */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_HASH_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_HASH_OFFSET (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */
#define ICM_HASH_HASA_Pos 7 /**< (ICM_HASH) Hash Area Start Address Position */
#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */
#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \deprecated (ICM_HASH) Register MASK (Use ICM_HASH_Msk instead) */
#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */
/* -------- ICM_UIHVAL : (ICM Offset: 0x38) (/W 32) User Initial Hash Value 0 Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VAL:32; /**< bit: 0..31 Initial Hash Value */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} ICM_UIHVAL_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_UIHVAL_OFFSET (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */
#define ICM_UIHVAL_VAL_Pos 0 /**< (ICM_UIHVAL) Initial Hash Value Position */
#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */
#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \deprecated (ICM_UIHVAL) Register MASK (Use ICM_UIHVAL_Msk instead) */
#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief ICM hardware registers */
typedef struct {
__IO uint32_t ICM_CFG; /**< (ICM Offset: 0x00) Configuration Register */
__O uint32_t ICM_CTRL; /**< (ICM Offset: 0x04) Control Register */
__I uint32_t ICM_SR; /**< (ICM Offset: 0x08) Status Register */
RoReg8 Reserved1[0x4];
__O uint32_t ICM_IER; /**< (ICM Offset: 0x10) Interrupt Enable Register */
__O uint32_t ICM_IDR; /**< (ICM Offset: 0x14) Interrupt Disable Register */
__I uint32_t ICM_IMR; /**< (ICM Offset: 0x18) Interrupt Mask Register */
__I uint32_t ICM_ISR; /**< (ICM Offset: 0x1C) Interrupt Status Register */
__I uint32_t ICM_UASR; /**< (ICM Offset: 0x20) Undefined Access Status Register */
RoReg8 Reserved2[0xC];
__IO uint32_t ICM_DSCR; /**< (ICM Offset: 0x30) Region Descriptor Area Start Address Register */
__IO uint32_t ICM_HASH; /**< (ICM Offset: 0x34) Region Hash Area Start Address Register */
__O uint32_t ICM_UIHVAL[8]; /**< (ICM Offset: 0x38) User Initial Hash Value 0 Register 0 */
} Icm;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief ICM hardware registers */
typedef struct {
__IO ICM_CFG_Type ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */
__O ICM_CTRL_Type ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */
__I ICM_SR_Type ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */
__I uint32_t Reserved1[1];
__O ICM_IER_Type ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
__O ICM_IDR_Type ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
__I ICM_IMR_Type ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
__I ICM_ISR_Type ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
__I ICM_UASR_Type ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */
__I uint32_t Reserved2[3];
__IO ICM_DSCR_Type ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */
__IO ICM_HASH_Type ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */
__O ICM_UIHVAL_Type ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */
} Icm;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Integrity Check Monitor */
#endif /* _SAME70_ICM_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for MATRIX
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_MATRIX_COMPONENT_H_
#define _SAME70_MATRIX_COMPONENT_H_
#define _SAME70_MATRIX_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 AHB Bus Matrix
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR MATRIX */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define MATRIX_11282 /**< (MATRIX) Module ID */
#define REV_MATRIX L /**< (MATRIX) Module revision */
/* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t M0PR:2; /**< bit: 0..1 Master 0 Priority */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t M1PR:2; /**< bit: 4..5 Master 1 Priority */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t M2PR:2; /**< bit: 8..9 Master 2 Priority */
uint32_t :2; /**< bit: 10..11 Reserved */
uint32_t M3PR:2; /**< bit: 12..13 Master 3 Priority */
uint32_t :2; /**< bit: 14..15 Reserved */
uint32_t M4PR:2; /**< bit: 16..17 Master 4 Priority */
uint32_t :2; /**< bit: 18..19 Reserved */
uint32_t M5PR:2; /**< bit: 20..21 Master 5 Priority */
uint32_t :2; /**< bit: 22..23 Reserved */
uint32_t M6PR:2; /**< bit: 24..25 Master 6 Priority */
uint32_t :6; /**< bit: 26..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_PRAS_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_PRAS_OFFSET (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */
#define MATRIX_PRAS_M0PR_Pos 0 /**< (MATRIX_PRAS) Master 0 Priority Position */
#define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */
#define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))
#define MATRIX_PRAS_M1PR_Pos 4 /**< (MATRIX_PRAS) Master 1 Priority Position */
#define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */
#define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))
#define MATRIX_PRAS_M2PR_Pos 8 /**< (MATRIX_PRAS) Master 2 Priority Position */
#define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */
#define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))
#define MATRIX_PRAS_M3PR_Pos 12 /**< (MATRIX_PRAS) Master 3 Priority Position */
#define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */
#define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))
#define MATRIX_PRAS_M4PR_Pos 16 /**< (MATRIX_PRAS) Master 4 Priority Position */
#define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */
#define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))
#define MATRIX_PRAS_M5PR_Pos 20 /**< (MATRIX_PRAS) Master 5 Priority Position */
#define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */
#define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))
#define MATRIX_PRAS_M6PR_Pos 24 /**< (MATRIX_PRAS) Master 6 Priority Position */
#define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */
#define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))
#define MATRIX_PRAS_MASK _U_(0x3333333) /**< \deprecated (MATRIX_PRAS) Register MASK (Use MATRIX_PRAS_Msk instead) */
#define MATRIX_PRAS_Msk _U_(0x3333333) /**< (MATRIX_PRAS) Register Mask */
/* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t M8PR:2; /**< bit: 0..1 Master 8 Priority */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t M9PR:2; /**< bit: 4..5 Master 9 Priority */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t M10PR:2; /**< bit: 8..9 Master 10 Priority */
uint32_t :2; /**< bit: 10..11 Reserved */
uint32_t M11PR:2; /**< bit: 12..13 Master 11 Priority */
uint32_t :2; /**< bit: 14..15 Reserved */
uint32_t M12PR:2; /**< bit: 16..17 Master 12 Priority */
uint32_t :14; /**< bit: 18..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_PRBS_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_PRBS_OFFSET (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */
#define MATRIX_PRBS_M8PR_Pos 0 /**< (MATRIX_PRBS) Master 8 Priority Position */
#define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */
#define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))
#define MATRIX_PRBS_M9PR_Pos 4 /**< (MATRIX_PRBS) Master 9 Priority Position */
#define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */
#define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))
#define MATRIX_PRBS_M10PR_Pos 8 /**< (MATRIX_PRBS) Master 10 Priority Position */
#define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */
#define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))
#define MATRIX_PRBS_M11PR_Pos 12 /**< (MATRIX_PRBS) Master 11 Priority Position */
#define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */
#define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))
#define MATRIX_PRBS_M12PR_Pos 16 /**< (MATRIX_PRBS) Master 12 Priority Position */
#define MATRIX_PRBS_M12PR_Msk (_U_(0x3) << MATRIX_PRBS_M12PR_Pos) /**< (MATRIX_PRBS) Master 12 Priority Mask */
#define MATRIX_PRBS_M12PR(value) (MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos))
#define MATRIX_PRBS_MASK _U_(0x33333) /**< \deprecated (MATRIX_PRBS) Register MASK (Use MATRIX_PRBS_Msk instead) */
#define MATRIX_PRBS_Msk _U_(0x33333) /**< (MATRIX_PRBS) Register Mask */
/* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ULBT:3; /**< bit: 0..2 Undefined Length Burst Type */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_MCFG_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_MCFG_OFFSET (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */
#define MATRIX_MCFG_ULBT_Pos 0 /**< (MATRIX_MCFG) Undefined Length Burst Type Position */
#define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */
#define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))
#define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
#define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
#define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
#define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
#define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
#define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
#define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
#define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */
#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */
#define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */
#define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */
#define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */
#define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */
#define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */
#define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */
#define MATRIX_MCFG_MASK _U_(0x07) /**< \deprecated (MATRIX_MCFG) Register MASK (Use MATRIX_MCFG_Msk instead) */
#define MATRIX_MCFG_Msk _U_(0x07) /**< (MATRIX_MCFG) Register Mask */
/* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOT_CYCLE:9; /**< bit: 0..8 Maximum Bus Grant Duration for Masters */
uint32_t :7; /**< bit: 9..15 Reserved */
uint32_t DEFMSTR_TYPE:2; /**< bit: 16..17 Default Master Type */
uint32_t FIXED_DEFMSTR:4; /**< bit: 18..21 Fixed Default Master */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_SCFG_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_SCFG_OFFSET (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */
#define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */
#define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 /**< (MATRIX_SCFG) Default Master Type Position */
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */
#define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))
#define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
#define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */
#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */
#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 /**< (MATRIX_SCFG) Fixed Default Master Position */
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */
#define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))
#define MATRIX_SCFG_MASK _U_(0x3F01FF) /**< \deprecated (MATRIX_SCFG) Register MASK (Use MATRIX_SCFG_Msk instead) */
#define MATRIX_SCFG_Msk _U_(0x3F01FF) /**< (MATRIX_SCFG) Register Mask */
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RCB0:1; /**< bit: 0 Remap Command Bit for Master 0 */
uint32_t RCB1:1; /**< bit: 1 Remap Command Bit for Master 1 */
uint32_t RCB2:1; /**< bit: 2 Remap Command Bit for Master 2 */
uint32_t RCB3:1; /**< bit: 3 Remap Command Bit for Master 3 */
uint32_t RCB4:1; /**< bit: 4 Remap Command Bit for Master 4 */
uint32_t RCB5:1; /**< bit: 5 Remap Command Bit for Master 5 */
uint32_t RCB6:1; /**< bit: 6 Remap Command Bit for Master 6 */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t RCB8:1; /**< bit: 8 Remap Command Bit for Master 8 */
uint32_t RCB9:1; /**< bit: 9 Remap Command Bit for Master 9 */
uint32_t RCB10:1; /**< bit: 10 Remap Command Bit for Master 10 */
uint32_t RCB11:1; /**< bit: 11 Remap Command Bit for Master 11 */
uint32_t RCB12:1; /**< bit: 12 Remap Command Bit for Master 12 */
uint32_t :19; /**< bit: 13..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t RCB:12; /**< bit: 0..11 Remap Command Bit for Master x2 */
uint32_t :20; /**< bit: 12..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} MATRIX_MRCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_MRCR_OFFSET (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */
#define MATRIX_MRCR_RCB0_Pos 0 /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */
#define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */
#define MATRIX_MRCR_RCB0 MATRIX_MRCR_RCB0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB0_Msk instead */
#define MATRIX_MRCR_RCB1_Pos 1 /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */
#define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */
#define MATRIX_MRCR_RCB1 MATRIX_MRCR_RCB1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB1_Msk instead */
#define MATRIX_MRCR_RCB2_Pos 2 /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */
#define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */
#define MATRIX_MRCR_RCB2 MATRIX_MRCR_RCB2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB2_Msk instead */
#define MATRIX_MRCR_RCB3_Pos 3 /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */
#define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */
#define MATRIX_MRCR_RCB3 MATRIX_MRCR_RCB3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB3_Msk instead */
#define MATRIX_MRCR_RCB4_Pos 4 /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */
#define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */
#define MATRIX_MRCR_RCB4 MATRIX_MRCR_RCB4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB4_Msk instead */
#define MATRIX_MRCR_RCB5_Pos 5 /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */
#define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */
#define MATRIX_MRCR_RCB5 MATRIX_MRCR_RCB5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB5_Msk instead */
#define MATRIX_MRCR_RCB6_Pos 6 /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */
#define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */
#define MATRIX_MRCR_RCB6 MATRIX_MRCR_RCB6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB6_Msk instead */
#define MATRIX_MRCR_RCB8_Pos 8 /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */
#define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */
#define MATRIX_MRCR_RCB8 MATRIX_MRCR_RCB8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB8_Msk instead */
#define MATRIX_MRCR_RCB9_Pos 9 /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */
#define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */
#define MATRIX_MRCR_RCB9 MATRIX_MRCR_RCB9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB9_Msk instead */
#define MATRIX_MRCR_RCB10_Pos 10 /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */
#define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */
#define MATRIX_MRCR_RCB10 MATRIX_MRCR_RCB10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB10_Msk instead */
#define MATRIX_MRCR_RCB11_Pos 11 /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */
#define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */
#define MATRIX_MRCR_RCB11 MATRIX_MRCR_RCB11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB11_Msk instead */
#define MATRIX_MRCR_RCB12_Pos 12 /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Position */
#define MATRIX_MRCR_RCB12_Msk (_U_(0x1) << MATRIX_MRCR_RCB12_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Mask */
#define MATRIX_MRCR_RCB12 MATRIX_MRCR_RCB12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB12_Msk instead */
#define MATRIX_MRCR_MASK _U_(0x1F7F) /**< \deprecated (MATRIX_MRCR) Register MASK (Use MATRIX_MRCR_Msk instead) */
#define MATRIX_MRCR_Msk _U_(0x1F7F) /**< (MATRIX_MRCR) Register Mask */
#define MATRIX_MRCR_RCB_Pos 0 /**< (MATRIX_MRCR Position) Remap Command Bit for Master x2 */
#define MATRIX_MRCR_RCB_Msk (_U_(0xFFF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */
#define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos))
/* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :16; /**< bit: 0..15 Reserved */
uint32_t CAN0DMABA:16; /**< bit: 16..31 CAN0 DMA Base Address */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} CCFG_CAN0_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCFG_CAN0_OFFSET (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */
#define CCFG_CAN0_CAN0DMABA_Pos 16 /**< (CCFG_CAN0) CAN0 DMA Base Address Position */
#define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */
#define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))
#define CCFG_CAN0_MASK _U_(0xFFFF0000) /**< \deprecated (CCFG_CAN0) Register MASK (Use CCFG_CAN0_Msk instead) */
#define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */
/* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :4; /**< bit: 0..3 Reserved */
uint32_t SYSIO4:1; /**< bit: 4 PB4 or TDI Assignment */
uint32_t SYSIO5:1; /**< bit: 5 PB5 or TDO/TRACESWO Assignment */
uint32_t SYSIO6:1; /**< bit: 6 PB6 or TMS/SWDIO Assignment */
uint32_t SYSIO7:1; /**< bit: 7 PB7 or TCK/SWCLK Assignment */
uint32_t :4; /**< bit: 8..11 Reserved */
uint32_t SYSIO12:1; /**< bit: 12 PB12 or ERASE Assignment */
uint32_t :3; /**< bit: 13..15 Reserved */
uint32_t CAN1DMABA:16; /**< bit: 16..31 CAN1 DMA Base Address */
} bit; /**< Structure used for bit access */
struct {
uint32_t :4; /**< bit: 0..3 Reserved */
uint32_t SYSIO:5; /**< bit: 4..8 PB4 or TDI Assignment */
uint32_t :23; /**< bit: 9..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} CCFG_SYSIO_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCFG_SYSIO_OFFSET (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */
#define CCFG_SYSIO_SYSIO4_Pos 4 /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */
#define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */
#define CCFG_SYSIO_SYSIO4 CCFG_SYSIO_SYSIO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO4_Msk instead */
#define CCFG_SYSIO_SYSIO5_Pos 5 /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */
#define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */
#define CCFG_SYSIO_SYSIO5 CCFG_SYSIO_SYSIO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO5_Msk instead */
#define CCFG_SYSIO_SYSIO6_Pos 6 /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */
#define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */
#define CCFG_SYSIO_SYSIO6 CCFG_SYSIO_SYSIO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO6_Msk instead */
#define CCFG_SYSIO_SYSIO7_Pos 7 /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */
#define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */
#define CCFG_SYSIO_SYSIO7 CCFG_SYSIO_SYSIO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO7_Msk instead */
#define CCFG_SYSIO_SYSIO12_Pos 12 /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */
#define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */
#define CCFG_SYSIO_SYSIO12 CCFG_SYSIO_SYSIO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO12_Msk instead */
#define CCFG_SYSIO_CAN1DMABA_Pos 16 /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */
#define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */
#define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))
#define CCFG_SYSIO_MASK _U_(0xFFFF10F0) /**< \deprecated (CCFG_SYSIO) Register MASK (Use CCFG_SYSIO_Msk instead) */
#define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */
#define CCFG_SYSIO_SYSIO_Pos 4 /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */
#define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */
#define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos))
/* -------- CCFG_PCCR : (MATRIX Offset: 0x118) (R/W 32) Peripheral Clock Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :20; /**< bit: 0..19 Reserved */
uint32_t TC0CC:1; /**< bit: 20 TC0 Clock Configuration */
uint32_t I2SC0CC:1; /**< bit: 21 I2SC0 Clock Configuration */
uint32_t I2SC1CC:1; /**< bit: 22 I2SC1 Clock Configuration */
uint32_t :9; /**< bit: 23..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} CCFG_PCCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCFG_PCCR_OFFSET (0x118) /**< (CCFG_PCCR) Peripheral Clock Configuration Register Offset */
#define CCFG_PCCR_TC0CC_Pos 20 /**< (CCFG_PCCR) TC0 Clock Configuration Position */
#define CCFG_PCCR_TC0CC_Msk (_U_(0x1) << CCFG_PCCR_TC0CC_Pos) /**< (CCFG_PCCR) TC0 Clock Configuration Mask */
#define CCFG_PCCR_TC0CC CCFG_PCCR_TC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_TC0CC_Msk instead */
#define CCFG_PCCR_I2SC0CC_Pos 21 /**< (CCFG_PCCR) I2SC0 Clock Configuration Position */
#define CCFG_PCCR_I2SC0CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC0CC_Pos) /**< (CCFG_PCCR) I2SC0 Clock Configuration Mask */
#define CCFG_PCCR_I2SC0CC CCFG_PCCR_I2SC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC0CC_Msk instead */
#define CCFG_PCCR_I2SC1CC_Pos 22 /**< (CCFG_PCCR) I2SC1 Clock Configuration Position */
#define CCFG_PCCR_I2SC1CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC1CC_Pos) /**< (CCFG_PCCR) I2SC1 Clock Configuration Mask */
#define CCFG_PCCR_I2SC1CC CCFG_PCCR_I2SC1CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC1CC_Msk instead */
#define CCFG_PCCR_MASK _U_(0x700000) /**< \deprecated (CCFG_PCCR) Register MASK (Use CCFG_PCCR_Msk instead) */
#define CCFG_PCCR_Msk _U_(0x700000) /**< (CCFG_PCCR) Register Mask */
/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MATCKG:1; /**< bit: 0 MATRIX Dynamic Clock Gating */
uint32_t BRIDCKG:1; /**< bit: 1 Bridge Dynamic Clock Gating Enable */
uint32_t EFCCKG:1; /**< bit: 2 EFC Dynamic Clock Gating Enable */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} CCFG_DYNCKG_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCFG_DYNCKG_OFFSET (0x11C) /**< (CCFG_DYNCKG) Dynamic Clock Gating Register Offset */
#define CCFG_DYNCKG_MATCKG_Pos 0 /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Position */
#define CCFG_DYNCKG_MATCKG_Msk (_U_(0x1) << CCFG_DYNCKG_MATCKG_Pos) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Mask */
#define CCFG_DYNCKG_MATCKG CCFG_DYNCKG_MATCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_MATCKG_Msk instead */
#define CCFG_DYNCKG_BRIDCKG_Pos 1 /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Position */
#define CCFG_DYNCKG_BRIDCKG_Msk (_U_(0x1) << CCFG_DYNCKG_BRIDCKG_Pos) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Mask */
#define CCFG_DYNCKG_BRIDCKG CCFG_DYNCKG_BRIDCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_BRIDCKG_Msk instead */
#define CCFG_DYNCKG_EFCCKG_Pos 2 /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Position */
#define CCFG_DYNCKG_EFCCKG_Msk (_U_(0x1) << CCFG_DYNCKG_EFCCKG_Pos) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Mask */
#define CCFG_DYNCKG_EFCCKG CCFG_DYNCKG_EFCCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_EFCCKG_Msk instead */
#define CCFG_DYNCKG_MASK _U_(0x07) /**< \deprecated (CCFG_DYNCKG) Register MASK (Use CCFG_DYNCKG_Msk instead) */
#define CCFG_DYNCKG_Msk _U_(0x07) /**< (CCFG_DYNCKG) Register Mask */
/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMC_NFCS0:1; /**< bit: 0 SMC NAND Flash Chip Select 0 Assignment */
uint32_t SMC_NFCS1:1; /**< bit: 1 SMC NAND Flash Chip Select 1 Assignment */
uint32_t SMC_NFCS2:1; /**< bit: 2 SMC NAND Flash Chip Select 2 Assignment */
uint32_t SMC_NFCS3:1; /**< bit: 3 SMC NAND Flash Chip Select 3 Assignment */
uint32_t SDRAMEN:1; /**< bit: 4 SDRAM Enable */
uint32_t :27; /**< bit: 5..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t SMC_NFCS:4; /**< bit: 0..3 SMC NAND Flash Chip Select x Assignment */
uint32_t :28; /**< bit: 4..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} CCFG_SMCNFCS_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCFG_SMCNFCS_OFFSET (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */
#define CCFG_SMCNFCS_SMC_NFCS0_Pos 0 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */
#define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */
#define CCFG_SMCNFCS_SMC_NFCS0 CCFG_SMCNFCS_SMC_NFCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS0_Msk instead */
#define CCFG_SMCNFCS_SMC_NFCS1_Pos 1 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */
#define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */
#define CCFG_SMCNFCS_SMC_NFCS1 CCFG_SMCNFCS_SMC_NFCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS1_Msk instead */
#define CCFG_SMCNFCS_SMC_NFCS2_Pos 2 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */
#define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */
#define CCFG_SMCNFCS_SMC_NFCS2 CCFG_SMCNFCS_SMC_NFCS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS2_Msk instead */
#define CCFG_SMCNFCS_SMC_NFCS3_Pos 3 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */
#define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */
#define CCFG_SMCNFCS_SMC_NFCS3 CCFG_SMCNFCS_SMC_NFCS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS3_Msk instead */
#define CCFG_SMCNFCS_SDRAMEN_Pos 4 /**< (CCFG_SMCNFCS) SDRAM Enable Position */
#define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */
#define CCFG_SMCNFCS_SDRAMEN CCFG_SMCNFCS_SDRAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SDRAMEN_Msk instead */
#define CCFG_SMCNFCS_MASK _U_(0x1F) /**< \deprecated (CCFG_SMCNFCS) Register MASK (Use CCFG_SMCNFCS_Msk instead) */
#define CCFG_SMCNFCS_Msk _U_(0x1F) /**< (CCFG_SMCNFCS) Register Mask */
#define CCFG_SMCNFCS_SMC_NFCS_Pos 0 /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */
#define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */
#define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos))
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1e4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_WPMR_OFFSET (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */
#define MATRIX_WPMR_WPEN_Pos 0 /**< (MATRIX_WPMR) Write Protection Enable Position */
#define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */
#define MATRIX_WPMR_WPEN MATRIX_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPMR_WPEN_Msk instead */
#define MATRIX_WPMR_WPKEY_Pos 8 /**< (MATRIX_WPMR) Write Protection Key Position */
#define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */
#define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))
#define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define MATRIX_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (MATRIX_WPMR) Register MASK (Use MATRIX_WPMR_Msk instead) */
#define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1e8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} MATRIX_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MATRIX_WPSR_OFFSET (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */
#define MATRIX_WPSR_WPVS_Pos 0 /**< (MATRIX_WPSR) Write Protection Violation Status Position */
#define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */
#define MATRIX_WPSR_WPVS MATRIX_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPSR_WPVS_Msk instead */
#define MATRIX_WPSR_WPVSRC_Pos 8 /**< (MATRIX_WPSR) Write Protection Violation Source Position */
#define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */
#define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos))
#define MATRIX_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (MATRIX_WPSR) Register MASK (Use MATRIX_WPSR_Msk instead) */
#define MATRIX_WPSR_Msk _U_(0xFFFF01) /**< (MATRIX_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief MATRIX_PR hardware registers */
typedef struct {
__IO uint32_t MATRIX_PRAS; /**< (MATRIX_PR Offset: 0x00) Priority Register A for Slave 0 */
__IO uint32_t MATRIX_PRBS; /**< (MATRIX_PR Offset: 0x04) Priority Register B for Slave 0 */
} MatrixPr;
#define MATRIXPR_NUMBER 9
/** \brief MATRIX hardware registers */
typedef struct {
__IO uint32_t MATRIX_MCFG[13]; /**< (MATRIX Offset: 0x00) Master Configuration Register 0 */
RoReg8 Reserved1[0xC];
__IO uint32_t MATRIX_SCFG[9]; /**< (MATRIX Offset: 0x40) Slave Configuration Register 0 */
RoReg8 Reserved2[0x1C];
MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */
RoReg8 Reserved3[0x38];
__IO uint32_t MATRIX_MRCR; /**< (MATRIX Offset: 0x100) Master Remap Control Register */
RoReg8 Reserved4[0xC];
__IO uint32_t CCFG_CAN0; /**< (MATRIX Offset: 0x110) CAN0 Configuration Register */
__IO uint32_t CCFG_SYSIO; /**< (MATRIX Offset: 0x114) System I/O and CAN1 Configuration Register */
__IO uint32_t CCFG_PCCR; /**< (MATRIX Offset: 0x118) Peripheral Clock Configuration Register */
__IO uint32_t CCFG_DYNCKG; /**< (MATRIX Offset: 0x11C) Dynamic Clock Gating Register */
RoReg8 Reserved5[0x4];
__IO uint32_t CCFG_SMCNFCS; /**< (MATRIX Offset: 0x124) SMC NAND Flash Chip Select Configuration Register */
RoReg8 Reserved6[0xBC];
__IO uint32_t MATRIX_WPMR; /**< (MATRIX Offset: 0x1E4) Write Protection Mode Register */
__I uint32_t MATRIX_WPSR; /**< (MATRIX Offset: 0x1E8) Write Protection Status Register */
} Matrix;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief MATRIX_PR hardware registers */
typedef struct {
__IO MATRIX_PRAS_Type MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */
__IO MATRIX_PRBS_Type MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */
} MatrixPr;
/** \brief MATRIX hardware registers */
typedef struct {
__IO MATRIX_MCFG_Type MATRIX_MCFG[13]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */
__I uint32_t Reserved1[3];
__IO MATRIX_SCFG_Type MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */
__I uint32_t Reserved2[7];
MatrixPr MATRIX_PR[9]; /**< Offset: 0x80 Priority Register A for Slave 0 */
__I uint32_t Reserved3[14];
__IO MATRIX_MRCR_Type MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */
__I uint32_t Reserved4[3];
__IO CCFG_CAN0_Type CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */
__IO CCFG_SYSIO_Type CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */
__IO CCFG_PCCR_Type CCFG_PCCR; /**< Offset: 0x118 (R/W 32) Peripheral Clock Configuration Register */
__IO CCFG_DYNCKG_Type CCFG_DYNCKG; /**< Offset: 0x11C (R/W 32) Dynamic Clock Gating Register */
__I uint32_t Reserved5[1];
__IO CCFG_SMCNFCS_Type CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */
__I uint32_t Reserved6[47];
__IO MATRIX_WPMR_Type MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */
__I MATRIX_WPSR_Type MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */
} Matrix;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of AHB Bus Matrix */
#endif /* _SAME70_MATRIX_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for QSPI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_QSPI_COMPONENT_H_
#define _SAME70_QSPI_COMPONENT_H_
#define _SAME70_QSPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Quad Serial Peripheral Interface
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR QSPI */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define QSPI_11171 /**< (QSPI) Module ID */
#define REV_QSPI J /**< (QSPI) Module revision */
/* -------- QSPI_CR : (QSPI Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t QSPIEN:1; /**< bit: 0 QSPI Enable */
uint32_t QSPIDIS:1; /**< bit: 1 QSPI Disable */
uint32_t :5; /**< bit: 2..6 Reserved */
uint32_t SWRST:1; /**< bit: 7 QSPI Software Reset */
uint32_t :16; /**< bit: 8..23 Reserved */
uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_CR_OFFSET (0x00) /**< (QSPI_CR) Control Register Offset */
#define QSPI_CR_QSPIEN_Pos 0 /**< (QSPI_CR) QSPI Enable Position */
#define QSPI_CR_QSPIEN_Msk (_U_(0x1) << QSPI_CR_QSPIEN_Pos) /**< (QSPI_CR) QSPI Enable Mask */
#define QSPI_CR_QSPIEN QSPI_CR_QSPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIEN_Msk instead */
#define QSPI_CR_QSPIDIS_Pos 1 /**< (QSPI_CR) QSPI Disable Position */
#define QSPI_CR_QSPIDIS_Msk (_U_(0x1) << QSPI_CR_QSPIDIS_Pos) /**< (QSPI_CR) QSPI Disable Mask */
#define QSPI_CR_QSPIDIS QSPI_CR_QSPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIDIS_Msk instead */
#define QSPI_CR_SWRST_Pos 7 /**< (QSPI_CR) QSPI Software Reset Position */
#define QSPI_CR_SWRST_Msk (_U_(0x1) << QSPI_CR_SWRST_Pos) /**< (QSPI_CR) QSPI Software Reset Mask */
#define QSPI_CR_SWRST QSPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_SWRST_Msk instead */
#define QSPI_CR_LASTXFER_Pos 24 /**< (QSPI_CR) Last Transfer Position */
#define QSPI_CR_LASTXFER_Msk (_U_(0x1) << QSPI_CR_LASTXFER_Pos) /**< (QSPI_CR) Last Transfer Mask */
#define QSPI_CR_LASTXFER QSPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_LASTXFER_Msk instead */
#define QSPI_CR_MASK _U_(0x1000083) /**< \deprecated (QSPI_CR) Register MASK (Use QSPI_CR_Msk instead) */
#define QSPI_CR_Msk _U_(0x1000083) /**< (QSPI_CR) Register Mask */
/* -------- QSPI_MR : (QSPI Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMM:1; /**< bit: 0 Serial Memory Mode */
uint32_t LLB:1; /**< bit: 1 Local Loopback Enable */
uint32_t WDRBT:1; /**< bit: 2 Wait Data Read Before Transfer */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t CSMODE:2; /**< bit: 4..5 Chip Select Mode */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t NBBITS:4; /**< bit: 8..11 Number Of Bits Per Transfer */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t DLYBCT:8; /**< bit: 16..23 Delay Between Consecutive Transfers */
uint32_t DLYCS:8; /**< bit: 24..31 Minimum Inactive QCS Delay */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_MR_OFFSET (0x04) /**< (QSPI_MR) Mode Register Offset */
#define QSPI_MR_SMM_Pos 0 /**< (QSPI_MR) Serial Memory Mode Position */
#define QSPI_MR_SMM_Msk (_U_(0x1) << QSPI_MR_SMM_Pos) /**< (QSPI_MR) Serial Memory Mode Mask */
#define QSPI_MR_SMM QSPI_MR_SMM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_SMM_Msk instead */
#define QSPI_MR_SMM_SPI_Val _U_(0x0) /**< (QSPI_MR) The QSPI is in SPI mode. */
#define QSPI_MR_SMM_MEMORY_Val _U_(0x1) /**< (QSPI_MR) The QSPI is in Serial Memory mode. */
#define QSPI_MR_SMM_SPI (QSPI_MR_SMM_SPI_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in SPI mode. Position */
#define QSPI_MR_SMM_MEMORY (QSPI_MR_SMM_MEMORY_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in Serial Memory mode. Position */
#define QSPI_MR_LLB_Pos 1 /**< (QSPI_MR) Local Loopback Enable Position */
#define QSPI_MR_LLB_Msk (_U_(0x1) << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local Loopback Enable Mask */
#define QSPI_MR_LLB QSPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_LLB_Msk instead */
#define QSPI_MR_LLB_DISABLED_Val _U_(0x0) /**< (QSPI_MR) Local loopback path disabled. */
#define QSPI_MR_LLB_ENABLED_Val _U_(0x1) /**< (QSPI_MR) Local loopback path enabled. */
#define QSPI_MR_LLB_DISABLED (QSPI_MR_LLB_DISABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path disabled. Position */
#define QSPI_MR_LLB_ENABLED (QSPI_MR_LLB_ENABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path enabled. Position */
#define QSPI_MR_WDRBT_Pos 2 /**< (QSPI_MR) Wait Data Read Before Transfer Position */
#define QSPI_MR_WDRBT_Msk (_U_(0x1) << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) Wait Data Read Before Transfer Mask */
#define QSPI_MR_WDRBT QSPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_WDRBT_Msk instead */
#define QSPI_MR_WDRBT_DISABLED_Val _U_(0x0) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */
#define QSPI_MR_WDRBT_ENABLED_Val _U_(0x1) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */
#define QSPI_MR_WDRBT_DISABLED (QSPI_MR_WDRBT_DISABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. Position */
#define QSPI_MR_WDRBT_ENABLED (QSPI_MR_WDRBT_ENABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. Position */
#define QSPI_MR_CSMODE_Pos 4 /**< (QSPI_MR) Chip Select Mode Position */
#define QSPI_MR_CSMODE_Msk (_U_(0x3) << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) Chip Select Mode Mask */
#define QSPI_MR_CSMODE(value) (QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))
#define QSPI_MR_CSMODE_NOT_RELOADED_Val _U_(0x0) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */
#define QSPI_MR_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */
#define QSPI_MR_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. */
#define QSPI_MR_CSMODE_NOT_RELOADED (QSPI_MR_CSMODE_NOT_RELOADED_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. Position */
#define QSPI_MR_CSMODE_LASTXFER (QSPI_MR_CSMODE_LASTXFER_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. Position */
#define QSPI_MR_CSMODE_SYSTEMATICALLY (QSPI_MR_CSMODE_SYSTEMATICALLY_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. Position */
#define QSPI_MR_NBBITS_Pos 8 /**< (QSPI_MR) Number Of Bits Per Transfer Position */
#define QSPI_MR_NBBITS_Msk (_U_(0xF) << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) Number Of Bits Per Transfer Mask */
#define QSPI_MR_NBBITS(value) (QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))
#define QSPI_MR_NBBITS_8_BIT_Val _U_(0x0) /**< (QSPI_MR) 8 bits for transfer */
#define QSPI_MR_NBBITS_16_BIT_Val _U_(0x8) /**< (QSPI_MR) 16 bits for transfer */
#define QSPI_MR_NBBITS_8_BIT (QSPI_MR_NBBITS_8_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 8 bits for transfer Position */
#define QSPI_MR_NBBITS_16_BIT (QSPI_MR_NBBITS_16_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 16 bits for transfer Position */
#define QSPI_MR_DLYBCT_Pos 16 /**< (QSPI_MR) Delay Between Consecutive Transfers Position */
#define QSPI_MR_DLYBCT_Msk (_U_(0xFF) << QSPI_MR_DLYBCT_Pos) /**< (QSPI_MR) Delay Between Consecutive Transfers Mask */
#define QSPI_MR_DLYBCT(value) (QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))
#define QSPI_MR_DLYCS_Pos 24 /**< (QSPI_MR) Minimum Inactive QCS Delay Position */
#define QSPI_MR_DLYCS_Msk (_U_(0xFF) << QSPI_MR_DLYCS_Pos) /**< (QSPI_MR) Minimum Inactive QCS Delay Mask */
#define QSPI_MR_DLYCS(value) (QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))
#define QSPI_MR_MASK _U_(0xFFFF0F37) /**< \deprecated (QSPI_MR) Register MASK (Use QSPI_MR_Msk instead) */
#define QSPI_MR_Msk _U_(0xFFFF0F37) /**< (QSPI_MR) Register Mask */
/* -------- QSPI_RDR : (QSPI Offset: 0x08) (R/ 32) Receive Data Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RD:16; /**< bit: 0..15 Receive Data */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_RDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_RDR_OFFSET (0x08) /**< (QSPI_RDR) Receive Data Register Offset */
#define QSPI_RDR_RD_Pos 0 /**< (QSPI_RDR) Receive Data Position */
#define QSPI_RDR_RD_Msk (_U_(0xFFFF) << QSPI_RDR_RD_Pos) /**< (QSPI_RDR) Receive Data Mask */
#define QSPI_RDR_RD(value) (QSPI_RDR_RD_Msk & ((value) << QSPI_RDR_RD_Pos))
#define QSPI_RDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_RDR) Register MASK (Use QSPI_RDR_Msk instead) */
#define QSPI_RDR_Msk _U_(0xFFFF) /**< (QSPI_RDR) Register Mask */
/* -------- QSPI_TDR : (QSPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TD:16; /**< bit: 0..15 Transmit Data */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_TDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_TDR_OFFSET (0x0C) /**< (QSPI_TDR) Transmit Data Register Offset */
#define QSPI_TDR_TD_Pos 0 /**< (QSPI_TDR) Transmit Data Position */
#define QSPI_TDR_TD_Msk (_U_(0xFFFF) << QSPI_TDR_TD_Pos) /**< (QSPI_TDR) Transmit Data Mask */
#define QSPI_TDR_TD(value) (QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))
#define QSPI_TDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_TDR) Register MASK (Use QSPI_TDR_Msk instead) */
#define QSPI_TDR_Msk _U_(0xFFFF) /**< (QSPI_TDR) Register Mask */
/* -------- QSPI_SR : (QSPI Offset: 0x10) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */
uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */
uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty (cleared by writing SPI_TDR) */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t CSR:1; /**< bit: 8 Chip Select Rise (cleared on read) */
uint32_t CSS:1; /**< bit: 9 Chip Select Status */
uint32_t INSTRE:1; /**< bit: 10 Instruction End Status (cleared on read) */
uint32_t :13; /**< bit: 11..23 Reserved */
uint32_t QSPIENS:1; /**< bit: 24 QSPI Enable Status */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SR_OFFSET (0x10) /**< (QSPI_SR) Status Register Offset */
#define QSPI_SR_RDRF_Pos 0 /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */
#define QSPI_SR_RDRF_Msk (_U_(0x1) << QSPI_SR_RDRF_Pos) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */
#define QSPI_SR_RDRF QSPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_RDRF_Msk instead */
#define QSPI_SR_TDRE_Pos 1 /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */
#define QSPI_SR_TDRE_Msk (_U_(0x1) << QSPI_SR_TDRE_Pos) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */
#define QSPI_SR_TDRE QSPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TDRE_Msk instead */
#define QSPI_SR_TXEMPTY_Pos 2 /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */
#define QSPI_SR_TXEMPTY_Msk (_U_(0x1) << QSPI_SR_TXEMPTY_Pos) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */
#define QSPI_SR_TXEMPTY QSPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TXEMPTY_Msk instead */
#define QSPI_SR_OVRES_Pos 3 /**< (QSPI_SR) Overrun Error Status (cleared on read) Position */
#define QSPI_SR_OVRES_Msk (_U_(0x1) << QSPI_SR_OVRES_Pos) /**< (QSPI_SR) Overrun Error Status (cleared on read) Mask */
#define QSPI_SR_OVRES QSPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_OVRES_Msk instead */
#define QSPI_SR_CSR_Pos 8 /**< (QSPI_SR) Chip Select Rise (cleared on read) Position */
#define QSPI_SR_CSR_Msk (_U_(0x1) << QSPI_SR_CSR_Pos) /**< (QSPI_SR) Chip Select Rise (cleared on read) Mask */
#define QSPI_SR_CSR QSPI_SR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSR_Msk instead */
#define QSPI_SR_CSS_Pos 9 /**< (QSPI_SR) Chip Select Status Position */
#define QSPI_SR_CSS_Msk (_U_(0x1) << QSPI_SR_CSS_Pos) /**< (QSPI_SR) Chip Select Status Mask */
#define QSPI_SR_CSS QSPI_SR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSS_Msk instead */
#define QSPI_SR_INSTRE_Pos 10 /**< (QSPI_SR) Instruction End Status (cleared on read) Position */
#define QSPI_SR_INSTRE_Msk (_U_(0x1) << QSPI_SR_INSTRE_Pos) /**< (QSPI_SR) Instruction End Status (cleared on read) Mask */
#define QSPI_SR_INSTRE QSPI_SR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_INSTRE_Msk instead */
#define QSPI_SR_QSPIENS_Pos 24 /**< (QSPI_SR) QSPI Enable Status Position */
#define QSPI_SR_QSPIENS_Msk (_U_(0x1) << QSPI_SR_QSPIENS_Pos) /**< (QSPI_SR) QSPI Enable Status Mask */
#define QSPI_SR_QSPIENS QSPI_SR_QSPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_QSPIENS_Msk instead */
#define QSPI_SR_MASK _U_(0x100070F) /**< \deprecated (QSPI_SR) Register MASK (Use QSPI_SR_Msk instead) */
#define QSPI_SR_Msk _U_(0x100070F) /**< (QSPI_SR) Register Mask */
/* -------- QSPI_IER : (QSPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */
uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Enable */
uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Enable */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Enable */
uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Enable */
uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Enable */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_IER_OFFSET (0x14) /**< (QSPI_IER) Interrupt Enable Register Offset */
#define QSPI_IER_RDRF_Pos 0 /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Position */
#define QSPI_IER_RDRF_Msk (_U_(0x1) << QSPI_IER_RDRF_Pos) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Mask */
#define QSPI_IER_RDRF QSPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_RDRF_Msk instead */
#define QSPI_IER_TDRE_Pos 1 /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Position */
#define QSPI_IER_TDRE_Msk (_U_(0x1) << QSPI_IER_TDRE_Pos) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Mask */
#define QSPI_IER_TDRE QSPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TDRE_Msk instead */
#define QSPI_IER_TXEMPTY_Pos 2 /**< (QSPI_IER) Transmission Registers Empty Enable Position */
#define QSPI_IER_TXEMPTY_Msk (_U_(0x1) << QSPI_IER_TXEMPTY_Pos) /**< (QSPI_IER) Transmission Registers Empty Enable Mask */
#define QSPI_IER_TXEMPTY QSPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TXEMPTY_Msk instead */
#define QSPI_IER_OVRES_Pos 3 /**< (QSPI_IER) Overrun Error Interrupt Enable Position */
#define QSPI_IER_OVRES_Msk (_U_(0x1) << QSPI_IER_OVRES_Pos) /**< (QSPI_IER) Overrun Error Interrupt Enable Mask */
#define QSPI_IER_OVRES QSPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_OVRES_Msk instead */
#define QSPI_IER_CSR_Pos 8 /**< (QSPI_IER) Chip Select Rise Interrupt Enable Position */
#define QSPI_IER_CSR_Msk (_U_(0x1) << QSPI_IER_CSR_Pos) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Mask */
#define QSPI_IER_CSR QSPI_IER_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSR_Msk instead */
#define QSPI_IER_CSS_Pos 9 /**< (QSPI_IER) Chip Select Status Interrupt Enable Position */
#define QSPI_IER_CSS_Msk (_U_(0x1) << QSPI_IER_CSS_Pos) /**< (QSPI_IER) Chip Select Status Interrupt Enable Mask */
#define QSPI_IER_CSS QSPI_IER_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSS_Msk instead */
#define QSPI_IER_INSTRE_Pos 10 /**< (QSPI_IER) Instruction End Interrupt Enable Position */
#define QSPI_IER_INSTRE_Msk (_U_(0x1) << QSPI_IER_INSTRE_Pos) /**< (QSPI_IER) Instruction End Interrupt Enable Mask */
#define QSPI_IER_INSTRE QSPI_IER_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_INSTRE_Msk instead */
#define QSPI_IER_MASK _U_(0x70F) /**< \deprecated (QSPI_IER) Register MASK (Use QSPI_IER_Msk instead) */
#define QSPI_IER_Msk _U_(0x70F) /**< (QSPI_IER) Register Mask */
/* -------- QSPI_IDR : (QSPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */
uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Disable */
uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Disable */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Disable */
uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Disable */
uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Disable */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_IDR_OFFSET (0x18) /**< (QSPI_IDR) Interrupt Disable Register Offset */
#define QSPI_IDR_RDRF_Pos 0 /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Position */
#define QSPI_IDR_RDRF_Msk (_U_(0x1) << QSPI_IDR_RDRF_Pos) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Mask */
#define QSPI_IDR_RDRF QSPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_RDRF_Msk instead */
#define QSPI_IDR_TDRE_Pos 1 /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Position */
#define QSPI_IDR_TDRE_Msk (_U_(0x1) << QSPI_IDR_TDRE_Pos) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Mask */
#define QSPI_IDR_TDRE QSPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TDRE_Msk instead */
#define QSPI_IDR_TXEMPTY_Pos 2 /**< (QSPI_IDR) Transmission Registers Empty Disable Position */
#define QSPI_IDR_TXEMPTY_Msk (_U_(0x1) << QSPI_IDR_TXEMPTY_Pos) /**< (QSPI_IDR) Transmission Registers Empty Disable Mask */
#define QSPI_IDR_TXEMPTY QSPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TXEMPTY_Msk instead */
#define QSPI_IDR_OVRES_Pos 3 /**< (QSPI_IDR) Overrun Error Interrupt Disable Position */
#define QSPI_IDR_OVRES_Msk (_U_(0x1) << QSPI_IDR_OVRES_Pos) /**< (QSPI_IDR) Overrun Error Interrupt Disable Mask */
#define QSPI_IDR_OVRES QSPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_OVRES_Msk instead */
#define QSPI_IDR_CSR_Pos 8 /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Position */
#define QSPI_IDR_CSR_Msk (_U_(0x1) << QSPI_IDR_CSR_Pos) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Mask */
#define QSPI_IDR_CSR QSPI_IDR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSR_Msk instead */
#define QSPI_IDR_CSS_Pos 9 /**< (QSPI_IDR) Chip Select Status Interrupt Disable Position */
#define QSPI_IDR_CSS_Msk (_U_(0x1) << QSPI_IDR_CSS_Pos) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Mask */
#define QSPI_IDR_CSS QSPI_IDR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSS_Msk instead */
#define QSPI_IDR_INSTRE_Pos 10 /**< (QSPI_IDR) Instruction End Interrupt Disable Position */
#define QSPI_IDR_INSTRE_Msk (_U_(0x1) << QSPI_IDR_INSTRE_Pos) /**< (QSPI_IDR) Instruction End Interrupt Disable Mask */
#define QSPI_IDR_INSTRE QSPI_IDR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_INSTRE_Msk instead */
#define QSPI_IDR_MASK _U_(0x70F) /**< \deprecated (QSPI_IDR) Register MASK (Use QSPI_IDR_Msk instead) */
#define QSPI_IDR_Msk _U_(0x70F) /**< (QSPI_IDR) Register Mask */
/* -------- QSPI_IMR : (QSPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */
uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Mask */
uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Mask */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Mask */
uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Mask */
uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Mask */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_IMR_OFFSET (0x1C) /**< (QSPI_IMR) Interrupt Mask Register Offset */
#define QSPI_IMR_RDRF_Pos 0 /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Position */
#define QSPI_IMR_RDRF_Msk (_U_(0x1) << QSPI_IMR_RDRF_Pos) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Mask */
#define QSPI_IMR_RDRF QSPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_RDRF_Msk instead */
#define QSPI_IMR_TDRE_Pos 1 /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Position */
#define QSPI_IMR_TDRE_Msk (_U_(0x1) << QSPI_IMR_TDRE_Pos) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Mask */
#define QSPI_IMR_TDRE QSPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TDRE_Msk instead */
#define QSPI_IMR_TXEMPTY_Pos 2 /**< (QSPI_IMR) Transmission Registers Empty Mask Position */
#define QSPI_IMR_TXEMPTY_Msk (_U_(0x1) << QSPI_IMR_TXEMPTY_Pos) /**< (QSPI_IMR) Transmission Registers Empty Mask Mask */
#define QSPI_IMR_TXEMPTY QSPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TXEMPTY_Msk instead */
#define QSPI_IMR_OVRES_Pos 3 /**< (QSPI_IMR) Overrun Error Interrupt Mask Position */
#define QSPI_IMR_OVRES_Msk (_U_(0x1) << QSPI_IMR_OVRES_Pos) /**< (QSPI_IMR) Overrun Error Interrupt Mask Mask */
#define QSPI_IMR_OVRES QSPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_OVRES_Msk instead */
#define QSPI_IMR_CSR_Pos 8 /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Position */
#define QSPI_IMR_CSR_Msk (_U_(0x1) << QSPI_IMR_CSR_Pos) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Mask */
#define QSPI_IMR_CSR QSPI_IMR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSR_Msk instead */
#define QSPI_IMR_CSS_Pos 9 /**< (QSPI_IMR) Chip Select Status Interrupt Mask Position */
#define QSPI_IMR_CSS_Msk (_U_(0x1) << QSPI_IMR_CSS_Pos) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Mask */
#define QSPI_IMR_CSS QSPI_IMR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSS_Msk instead */
#define QSPI_IMR_INSTRE_Pos 10 /**< (QSPI_IMR) Instruction End Interrupt Mask Position */
#define QSPI_IMR_INSTRE_Msk (_U_(0x1) << QSPI_IMR_INSTRE_Pos) /**< (QSPI_IMR) Instruction End Interrupt Mask Mask */
#define QSPI_IMR_INSTRE QSPI_IMR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_INSTRE_Msk instead */
#define QSPI_IMR_MASK _U_(0x70F) /**< \deprecated (QSPI_IMR) Register MASK (Use QSPI_IMR_Msk instead) */
#define QSPI_IMR_Msk _U_(0x70F) /**< (QSPI_IMR) Register Mask */
/* -------- QSPI_SCR : (QSPI Offset: 0x20) (R/W 32) Serial Clock Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CPOL:1; /**< bit: 0 Clock Polarity */
uint32_t CPHA:1; /**< bit: 1 Clock Phase */
uint32_t :6; /**< bit: 2..7 Reserved */
uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Baud Rate */
uint32_t DLYBS:8; /**< bit: 16..23 Delay Before QSCK */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_SCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SCR_OFFSET (0x20) /**< (QSPI_SCR) Serial Clock Register Offset */
#define QSPI_SCR_CPOL_Pos 0 /**< (QSPI_SCR) Clock Polarity Position */
#define QSPI_SCR_CPOL_Msk (_U_(0x1) << QSPI_SCR_CPOL_Pos) /**< (QSPI_SCR) Clock Polarity Mask */
#define QSPI_SCR_CPOL QSPI_SCR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPOL_Msk instead */
#define QSPI_SCR_CPHA_Pos 1 /**< (QSPI_SCR) Clock Phase Position */
#define QSPI_SCR_CPHA_Msk (_U_(0x1) << QSPI_SCR_CPHA_Pos) /**< (QSPI_SCR) Clock Phase Mask */
#define QSPI_SCR_CPHA QSPI_SCR_CPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPHA_Msk instead */
#define QSPI_SCR_SCBR_Pos 8 /**< (QSPI_SCR) Serial Clock Baud Rate Position */
#define QSPI_SCR_SCBR_Msk (_U_(0xFF) << QSPI_SCR_SCBR_Pos) /**< (QSPI_SCR) Serial Clock Baud Rate Mask */
#define QSPI_SCR_SCBR(value) (QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))
#define QSPI_SCR_DLYBS_Pos 16 /**< (QSPI_SCR) Delay Before QSCK Position */
#define QSPI_SCR_DLYBS_Msk (_U_(0xFF) << QSPI_SCR_DLYBS_Pos) /**< (QSPI_SCR) Delay Before QSCK Mask */
#define QSPI_SCR_DLYBS(value) (QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))
#define QSPI_SCR_MASK _U_(0xFFFF03) /**< \deprecated (QSPI_SCR) Register MASK (Use QSPI_SCR_Msk instead) */
#define QSPI_SCR_Msk _U_(0xFFFF03) /**< (QSPI_SCR) Register Mask */
/* -------- QSPI_IAR : (QSPI Offset: 0x30) (R/W 32) Instruction Address Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:32; /**< bit: 0..31 Address */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_IAR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_IAR_OFFSET (0x30) /**< (QSPI_IAR) Instruction Address Register Offset */
#define QSPI_IAR_ADDR_Pos 0 /**< (QSPI_IAR) Address Position */
#define QSPI_IAR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_IAR_ADDR_Pos) /**< (QSPI_IAR) Address Mask */
#define QSPI_IAR_ADDR(value) (QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))
#define QSPI_IAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_IAR) Register MASK (Use QSPI_IAR_Msk instead) */
#define QSPI_IAR_Msk _U_(0xFFFFFFFF) /**< (QSPI_IAR) Register Mask */
/* -------- QSPI_ICR : (QSPI Offset: 0x34) (R/W 32) Instruction Code Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INST:8; /**< bit: 0..7 Instruction Code */
uint32_t :8; /**< bit: 8..15 Reserved */
uint32_t OPT:8; /**< bit: 16..23 Option Code */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_ICR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_ICR_OFFSET (0x34) /**< (QSPI_ICR) Instruction Code Register Offset */
#define QSPI_ICR_INST_Pos 0 /**< (QSPI_ICR) Instruction Code Position */
#define QSPI_ICR_INST_Msk (_U_(0xFF) << QSPI_ICR_INST_Pos) /**< (QSPI_ICR) Instruction Code Mask */
#define QSPI_ICR_INST(value) (QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))
#define QSPI_ICR_OPT_Pos 16 /**< (QSPI_ICR) Option Code Position */
#define QSPI_ICR_OPT_Msk (_U_(0xFF) << QSPI_ICR_OPT_Pos) /**< (QSPI_ICR) Option Code Mask */
#define QSPI_ICR_OPT(value) (QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))
#define QSPI_ICR_MASK _U_(0xFF00FF) /**< \deprecated (QSPI_ICR) Register MASK (Use QSPI_ICR_Msk instead) */
#define QSPI_ICR_Msk _U_(0xFF00FF) /**< (QSPI_ICR) Register Mask */
/* -------- QSPI_IFR : (QSPI Offset: 0x38) (R/W 32) Instruction Frame Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WIDTH:3; /**< bit: 0..2 Width of Instruction Code, Address, Option Code and Data */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t INSTEN:1; /**< bit: 4 Instruction Enable */
uint32_t ADDREN:1; /**< bit: 5 Address Enable */
uint32_t OPTEN:1; /**< bit: 6 Option Enable */
uint32_t DATAEN:1; /**< bit: 7 Data Enable */
uint32_t OPTL:2; /**< bit: 8..9 Option Code Length */
uint32_t ADDRL:1; /**< bit: 10 Address Length */
uint32_t :1; /**< bit: 11 Reserved */
uint32_t TFRTYP:2; /**< bit: 12..13 Data Transfer Type */
uint32_t CRM:1; /**< bit: 14 Continuous Read Mode */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t NBDUM:5; /**< bit: 16..20 Number Of Dummy Cycles */
uint32_t :11; /**< bit: 21..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_IFR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_IFR_OFFSET (0x38) /**< (QSPI_IFR) Instruction Frame Register Offset */
#define QSPI_IFR_WIDTH_Pos 0 /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Position */
#define QSPI_IFR_WIDTH_Msk (_U_(0x7) << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Mask */
#define QSPI_IFR_WIDTH(value) (QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))
#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
#define QSPI_IFR_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
#define QSPI_IFR_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
#define QSPI_IFR_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_IFR_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_IFR_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_IFR_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */
#define QSPI_IFR_WIDTH_DUAL_OUTPUT (QSPI_IFR_WIDTH_DUAL_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */
#define QSPI_IFR_WIDTH_QUAD_OUTPUT (QSPI_IFR_WIDTH_QUAD_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */
#define QSPI_IFR_WIDTH_DUAL_IO (QSPI_IFR_WIDTH_DUAL_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */
#define QSPI_IFR_WIDTH_QUAD_IO (QSPI_IFR_WIDTH_QUAD_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */
#define QSPI_IFR_WIDTH_DUAL_CMD (QSPI_IFR_WIDTH_DUAL_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */
#define QSPI_IFR_WIDTH_QUAD_CMD (QSPI_IFR_WIDTH_QUAD_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */
#define QSPI_IFR_INSTEN_Pos 4 /**< (QSPI_IFR) Instruction Enable Position */
#define QSPI_IFR_INSTEN_Msk (_U_(0x1) << QSPI_IFR_INSTEN_Pos) /**< (QSPI_IFR) Instruction Enable Mask */
#define QSPI_IFR_INSTEN QSPI_IFR_INSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_INSTEN_Msk instead */
#define QSPI_IFR_ADDREN_Pos 5 /**< (QSPI_IFR) Address Enable Position */
#define QSPI_IFR_ADDREN_Msk (_U_(0x1) << QSPI_IFR_ADDREN_Pos) /**< (QSPI_IFR) Address Enable Mask */
#define QSPI_IFR_ADDREN QSPI_IFR_ADDREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDREN_Msk instead */
#define QSPI_IFR_OPTEN_Pos 6 /**< (QSPI_IFR) Option Enable Position */
#define QSPI_IFR_OPTEN_Msk (_U_(0x1) << QSPI_IFR_OPTEN_Pos) /**< (QSPI_IFR) Option Enable Mask */
#define QSPI_IFR_OPTEN QSPI_IFR_OPTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_OPTEN_Msk instead */
#define QSPI_IFR_DATAEN_Pos 7 /**< (QSPI_IFR) Data Enable Position */
#define QSPI_IFR_DATAEN_Msk (_U_(0x1) << QSPI_IFR_DATAEN_Pos) /**< (QSPI_IFR) Data Enable Mask */
#define QSPI_IFR_DATAEN QSPI_IFR_DATAEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_DATAEN_Msk instead */
#define QSPI_IFR_OPTL_Pos 8 /**< (QSPI_IFR) Option Code Length Position */
#define QSPI_IFR_OPTL_Msk (_U_(0x3) << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) Option Code Length Mask */
#define QSPI_IFR_OPTL(value) (QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))
#define QSPI_IFR_OPTL_OPTION_1BIT_Val _U_(0x0) /**< (QSPI_IFR) The option code is 1 bit long. */
#define QSPI_IFR_OPTL_OPTION_2BIT_Val _U_(0x1) /**< (QSPI_IFR) The option code is 2 bits long. */
#define QSPI_IFR_OPTL_OPTION_4BIT_Val _U_(0x2) /**< (QSPI_IFR) The option code is 4 bits long. */
#define QSPI_IFR_OPTL_OPTION_8BIT_Val _U_(0x3) /**< (QSPI_IFR) The option code is 8 bits long. */
#define QSPI_IFR_OPTL_OPTION_1BIT (QSPI_IFR_OPTL_OPTION_1BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 1 bit long. Position */
#define QSPI_IFR_OPTL_OPTION_2BIT (QSPI_IFR_OPTL_OPTION_2BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 2 bits long. Position */
#define QSPI_IFR_OPTL_OPTION_4BIT (QSPI_IFR_OPTL_OPTION_4BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 4 bits long. Position */
#define QSPI_IFR_OPTL_OPTION_8BIT (QSPI_IFR_OPTL_OPTION_8BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 8 bits long. Position */
#define QSPI_IFR_ADDRL_Pos 10 /**< (QSPI_IFR) Address Length Position */
#define QSPI_IFR_ADDRL_Msk (_U_(0x1) << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) Address Length Mask */
#define QSPI_IFR_ADDRL QSPI_IFR_ADDRL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDRL_Msk instead */
#define QSPI_IFR_ADDRL_24_BIT_Val _U_(0x0) /**< (QSPI_IFR) The address is 24 bits long. */
#define QSPI_IFR_ADDRL_32_BIT_Val _U_(0x1) /**< (QSPI_IFR) The address is 32 bits long. */
#define QSPI_IFR_ADDRL_24_BIT (QSPI_IFR_ADDRL_24_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 24 bits long. Position */
#define QSPI_IFR_ADDRL_32_BIT (QSPI_IFR_ADDRL_32_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 32 bits long. Position */
#define QSPI_IFR_TFRTYP_Pos 12 /**< (QSPI_IFR) Data Transfer Type Position */
#define QSPI_IFR_TFRTYP_Msk (_U_(0x3) << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Data Transfer Type Mask */
#define QSPI_IFR_TFRTYP(value) (QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))
#define QSPI_IFR_TFRTYP_TRSFR_READ_Val _U_(0x0) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */
#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val _U_(0x1) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */
#define QSPI_IFR_TFRTYP_TRSFR_WRITE_Val _U_(0x2) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */
#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val _U_(0x3) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */
#define QSPI_IFR_TFRTYP_TRSFR_READ (QSPI_IFR_TFRTYP_TRSFR_READ_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. Position */
#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. Position */
#define QSPI_IFR_TFRTYP_TRSFR_WRITE (QSPI_IFR_TFRTYP_TRSFR_WRITE_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. Position */
#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */
#define QSPI_IFR_CRM_Pos 14 /**< (QSPI_IFR) Continuous Read Mode Position */
#define QSPI_IFR_CRM_Msk (_U_(0x1) << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) Continuous Read Mode Mask */
#define QSPI_IFR_CRM QSPI_IFR_CRM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_CRM_Msk instead */
#define QSPI_IFR_CRM_DISABLED_Val _U_(0x0) /**< (QSPI_IFR) The Continuous Read mode is disabled. */
#define QSPI_IFR_CRM_ENABLED_Val _U_(0x1) /**< (QSPI_IFR) The Continuous Read mode is enabled. */
#define QSPI_IFR_CRM_DISABLED (QSPI_IFR_CRM_DISABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is disabled. Position */
#define QSPI_IFR_CRM_ENABLED (QSPI_IFR_CRM_ENABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is enabled. Position */
#define QSPI_IFR_NBDUM_Pos 16 /**< (QSPI_IFR) Number Of Dummy Cycles Position */
#define QSPI_IFR_NBDUM_Msk (_U_(0x1F) << QSPI_IFR_NBDUM_Pos) /**< (QSPI_IFR) Number Of Dummy Cycles Mask */
#define QSPI_IFR_NBDUM(value) (QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))
#define QSPI_IFR_MASK _U_(0x1F77F7) /**< \deprecated (QSPI_IFR) Register MASK (Use QSPI_IFR_Msk instead) */
#define QSPI_IFR_Msk _U_(0x1F77F7) /**< (QSPI_IFR) Register Mask */
/* -------- QSPI_SMR : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SCREN:1; /**< bit: 0 Scrambling/Unscrambling Enable */
uint32_t RVDIS:1; /**< bit: 1 Scrambling/Unscrambling Random Value Disable */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_SMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SMR_OFFSET (0x40) /**< (QSPI_SMR) Scrambling Mode Register Offset */
#define QSPI_SMR_SCREN_Pos 0 /**< (QSPI_SMR) Scrambling/Unscrambling Enable Position */
#define QSPI_SMR_SCREN_Msk (_U_(0x1) << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Mask */
#define QSPI_SMR_SCREN QSPI_SMR_SCREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_SCREN_Msk instead */
#define QSPI_SMR_SCREN_DISABLED_Val _U_(0x0) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. */
#define QSPI_SMR_SCREN_ENABLED_Val _U_(0x1) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. */
#define QSPI_SMR_SCREN_DISABLED (QSPI_SMR_SCREN_DISABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. Position */
#define QSPI_SMR_SCREN_ENABLED (QSPI_SMR_SCREN_ENABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. Position */
#define QSPI_SMR_RVDIS_Pos 1 /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Position */
#define QSPI_SMR_RVDIS_Msk (_U_(0x1) << QSPI_SMR_RVDIS_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Mask */
#define QSPI_SMR_RVDIS QSPI_SMR_RVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_RVDIS_Msk instead */
#define QSPI_SMR_MASK _U_(0x03) /**< \deprecated (QSPI_SMR) Register MASK (Use QSPI_SMR_Msk instead) */
#define QSPI_SMR_Msk _U_(0x03) /**< (QSPI_SMR) Register Mask */
/* -------- QSPI_SKR : (QSPI Offset: 0x44) (/W 32) Scrambling Key Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRK:32; /**< bit: 0..31 Scrambling User Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_SKR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SKR_OFFSET (0x44) /**< (QSPI_SKR) Scrambling Key Register Offset */
#define QSPI_SKR_USRK_Pos 0 /**< (QSPI_SKR) Scrambling User Key Position */
#define QSPI_SKR_USRK_Msk (_U_(0xFFFFFFFF) << QSPI_SKR_USRK_Pos) /**< (QSPI_SKR) Scrambling User Key Mask */
#define QSPI_SKR_USRK(value) (QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))
#define QSPI_SKR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_SKR) Register MASK (Use QSPI_SKR_Msk instead) */
#define QSPI_SKR_Msk _U_(0xFFFFFFFF) /**< (QSPI_SKR) Register Mask */
/* -------- QSPI_WPMR : (QSPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_WPMR_OFFSET (0xE4) /**< (QSPI_WPMR) Write Protection Mode Register Offset */
#define QSPI_WPMR_WPEN_Pos 0 /**< (QSPI_WPMR) Write Protection Enable Position */
#define QSPI_WPMR_WPEN_Msk (_U_(0x1) << QSPI_WPMR_WPEN_Pos) /**< (QSPI_WPMR) Write Protection Enable Mask */
#define QSPI_WPMR_WPEN QSPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPMR_WPEN_Msk instead */
#define QSPI_WPMR_WPKEY_Pos 8 /**< (QSPI_WPMR) Write Protection Key Position */
#define QSPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Write Protection Key Mask */
#define QSPI_WPMR_WPKEY(value) (QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))
#define QSPI_WPMR_WPKEY_PASSWD_Val _U_(0x515350) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
#define QSPI_WPMR_WPKEY_PASSWD (QSPI_WPMR_WPKEY_PASSWD_Val << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */
#define QSPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (QSPI_WPMR) Register MASK (Use QSPI_WPMR_Msk instead) */
#define QSPI_WPMR_Msk _U_(0xFFFFFF01) /**< (QSPI_WPMR) Register Mask */
/* -------- QSPI_WPSR : (QSPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} QSPI_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_WPSR_OFFSET (0xE8) /**< (QSPI_WPSR) Write Protection Status Register Offset */
#define QSPI_WPSR_WPVS_Pos 0 /**< (QSPI_WPSR) Write Protection Violation Status Position */
#define QSPI_WPSR_WPVS_Msk (_U_(0x1) << QSPI_WPSR_WPVS_Pos) /**< (QSPI_WPSR) Write Protection Violation Status Mask */
#define QSPI_WPSR_WPVS QSPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPSR_WPVS_Msk instead */
#define QSPI_WPSR_WPVSRC_Pos 8 /**< (QSPI_WPSR) Write Protection Violation Source Position */
#define QSPI_WPSR_WPVSRC_Msk (_U_(0xFF) << QSPI_WPSR_WPVSRC_Pos) /**< (QSPI_WPSR) Write Protection Violation Source Mask */
#define QSPI_WPSR_WPVSRC(value) (QSPI_WPSR_WPVSRC_Msk & ((value) << QSPI_WPSR_WPVSRC_Pos))
#define QSPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (QSPI_WPSR) Register MASK (Use QSPI_WPSR_Msk instead) */
#define QSPI_WPSR_Msk _U_(0xFF01) /**< (QSPI_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief QSPI hardware registers */
typedef struct {
__O uint32_t QSPI_CR; /**< (QSPI Offset: 0x00) Control Register */
__IO uint32_t QSPI_MR; /**< (QSPI Offset: 0x04) Mode Register */
__I uint32_t QSPI_RDR; /**< (QSPI Offset: 0x08) Receive Data Register */
__O uint32_t QSPI_TDR; /**< (QSPI Offset: 0x0C) Transmit Data Register */
__I uint32_t QSPI_SR; /**< (QSPI Offset: 0x10) Status Register */
__O uint32_t QSPI_IER; /**< (QSPI Offset: 0x14) Interrupt Enable Register */
__O uint32_t QSPI_IDR; /**< (QSPI Offset: 0x18) Interrupt Disable Register */
__I uint32_t QSPI_IMR; /**< (QSPI Offset: 0x1C) Interrupt Mask Register */
__IO uint32_t QSPI_SCR; /**< (QSPI Offset: 0x20) Serial Clock Register */
RoReg8 Reserved1[0xC];
__IO uint32_t QSPI_IAR; /**< (QSPI Offset: 0x30) Instruction Address Register */
__IO uint32_t QSPI_ICR; /**< (QSPI Offset: 0x34) Instruction Code Register */
__IO uint32_t QSPI_IFR; /**< (QSPI Offset: 0x38) Instruction Frame Register */
RoReg8 Reserved2[0x4];
__IO uint32_t QSPI_SMR; /**< (QSPI Offset: 0x40) Scrambling Mode Register */
__O uint32_t QSPI_SKR; /**< (QSPI Offset: 0x44) Scrambling Key Register */
RoReg8 Reserved3[0x9C];
__IO uint32_t QSPI_WPMR; /**< (QSPI Offset: 0xE4) Write Protection Mode Register */
__I uint32_t QSPI_WPSR; /**< (QSPI Offset: 0xE8) Write Protection Status Register */
} Qspi;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief QSPI hardware registers */
typedef struct {
__O QSPI_CR_Type QSPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO QSPI_MR_Type QSPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I QSPI_RDR_Type QSPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */
__O QSPI_TDR_Type QSPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */
__I QSPI_SR_Type QSPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */
__O QSPI_IER_Type QSPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */
__O QSPI_IDR_Type QSPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */
__I QSPI_IMR_Type QSPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */
__IO QSPI_SCR_Type QSPI_SCR; /**< Offset: 0x20 (R/W 32) Serial Clock Register */
__I uint32_t Reserved1[3];
__IO QSPI_IAR_Type QSPI_IAR; /**< Offset: 0x30 (R/W 32) Instruction Address Register */
__IO QSPI_ICR_Type QSPI_ICR; /**< Offset: 0x34 (R/W 32) Instruction Code Register */
__IO QSPI_IFR_Type QSPI_IFR; /**< Offset: 0x38 (R/W 32) Instruction Frame Register */
__I uint32_t Reserved2[1];
__IO QSPI_SMR_Type QSPI_SMR; /**< Offset: 0x40 (R/W 32) Scrambling Mode Register */
__O QSPI_SKR_Type QSPI_SKR; /**< Offset: 0x44 ( /W 32) Scrambling Key Register */
__I uint32_t Reserved3[39];
__IO QSPI_WPMR_Type QSPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I QSPI_WPSR_Type QSPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Qspi;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Quad Serial Peripheral Interface */
#endif /* _SAME70_QSPI_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for RSTC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RSTC_COMPONENT_H_
#define _SAME70_RSTC_COMPONENT_H_
#define _SAME70_RSTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Reset Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RSTC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define RSTC_11009 /**< (RSTC) Module ID */
#define REV_RSTC N /**< (RSTC) Module revision */
/* -------- RSTC_CR : (RSTC Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PROCRST:1; /**< bit: 0 Processor Reset */
uint32_t :2; /**< bit: 1..2 Reserved */
uint32_t EXTRST:1; /**< bit: 3 External Reset */
uint32_t :20; /**< bit: 4..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 System Reset Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSTC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_CR_OFFSET (0x00) /**< (RSTC_CR) Control Register Offset */
#define RSTC_CR_PROCRST_Pos 0 /**< (RSTC_CR) Processor Reset Position */
#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */
#define RSTC_CR_PROCRST RSTC_CR_PROCRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_PROCRST_Msk instead */
#define RSTC_CR_EXTRST_Pos 3 /**< (RSTC_CR) External Reset Position */
#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */
#define RSTC_CR_EXTRST RSTC_CR_EXTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_EXTRST_Msk instead */
#define RSTC_CR_KEY_Pos 24 /**< (RSTC_CR) System Reset Key Position */
#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */
#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))
#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */
#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */
#define RSTC_CR_MASK _U_(0xFF000009) /**< \deprecated (RSTC_CR) Register MASK (Use RSTC_CR_Msk instead) */
#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */
/* -------- RSTC_SR : (RSTC Offset: 0x04) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t URSTS:1; /**< bit: 0 User Reset Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t RSTTYP:3; /**< bit: 8..10 Reset Type */
uint32_t :5; /**< bit: 11..15 Reserved */
uint32_t NRSTL:1; /**< bit: 16 NRST Pin Level */
uint32_t SRCMP:1; /**< bit: 17 Software Reset Command in Progress */
uint32_t :14; /**< bit: 18..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSTC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_SR_OFFSET (0x04) /**< (RSTC_SR) Status Register Offset */
#define RSTC_SR_URSTS_Pos 0 /**< (RSTC_SR) User Reset Status Position */
#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */
#define RSTC_SR_URSTS RSTC_SR_URSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_URSTS_Msk instead */
#define RSTC_SR_RSTTYP_Pos 8 /**< (RSTC_SR) Reset Type Position */
#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */
#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos))
#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */
#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */
#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */
#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */
#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */
#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */
#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */
#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */
#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */
#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */
#define RSTC_SR_NRSTL_Pos 16 /**< (RSTC_SR) NRST Pin Level Position */
#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */
#define RSTC_SR_NRSTL RSTC_SR_NRSTL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_NRSTL_Msk instead */
#define RSTC_SR_SRCMP_Pos 17 /**< (RSTC_SR) Software Reset Command in Progress Position */
#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */
#define RSTC_SR_SRCMP RSTC_SR_SRCMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_SRCMP_Msk instead */
#define RSTC_SR_MASK _U_(0x30701) /**< \deprecated (RSTC_SR) Register MASK (Use RSTC_SR_Msk instead) */
#define RSTC_SR_Msk _U_(0x30701) /**< (RSTC_SR) Register Mask */
/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t URSTEN:1; /**< bit: 0 User Reset Enable */
uint32_t :3; /**< bit: 1..3 Reserved */
uint32_t URSTIEN:1; /**< bit: 4 User Reset Interrupt Enable */
uint32_t :3; /**< bit: 5..7 Reserved */
uint32_t ERSTL:4; /**< bit: 8..11 External Reset Length */
uint32_t :12; /**< bit: 12..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 Write Access Password */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSTC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_MR_OFFSET (0x08) /**< (RSTC_MR) Mode Register Offset */
#define RSTC_MR_URSTEN_Pos 0 /**< (RSTC_MR) User Reset Enable Position */
#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */
#define RSTC_MR_URSTEN RSTC_MR_URSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTEN_Msk instead */
#define RSTC_MR_URSTIEN_Pos 4 /**< (RSTC_MR) User Reset Interrupt Enable Position */
#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */
#define RSTC_MR_URSTIEN RSTC_MR_URSTIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTIEN_Msk instead */
#define RSTC_MR_ERSTL_Pos 8 /**< (RSTC_MR) External Reset Length Position */
#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */
#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))
#define RSTC_MR_KEY_Pos 24 /**< (RSTC_MR) Write Access Password Position */
#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */
#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))
#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
#define RSTC_MR_MASK _U_(0xFF000F11) /**< \deprecated (RSTC_MR) Register MASK (Use RSTC_MR_Msk instead) */
#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief RSTC hardware registers */
typedef struct {
__O uint32_t RSTC_CR; /**< (RSTC Offset: 0x00) Control Register */
__I uint32_t RSTC_SR; /**< (RSTC Offset: 0x04) Status Register */
__IO uint32_t RSTC_MR; /**< (RSTC Offset: 0x08) Mode Register */
} Rstc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief RSTC hardware registers */
typedef struct {
__O RSTC_CR_Type RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__I RSTC_SR_Type RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */
__IO RSTC_MR_Type RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */
} Rstc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Reset Controller */
#endif /* _SAME70_RSTC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for RSWDT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RSWDT_COMPONENT_H_
#define _SAME70_RSWDT_COMPONENT_H_
#define _SAME70_RSWDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Reinforced Safety Watchdog Timer
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RSWDT */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define RSWDT_11110 /**< (RSWDT) Module ID */
#define REV_RSWDT G /**< (RSWDT) Module revision */
/* -------- RSWDT_CR : (RSWDT Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */
uint32_t :23; /**< bit: 1..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 Password */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSWDT_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSWDT_CR_OFFSET (0x00) /**< (RSWDT_CR) Control Register Offset */
#define RSWDT_CR_WDRSTT_Pos 0 /**< (RSWDT_CR) Watchdog Restart Position */
#define RSWDT_CR_WDRSTT_Msk (_U_(0x1) << RSWDT_CR_WDRSTT_Pos) /**< (RSWDT_CR) Watchdog Restart Mask */
#define RSWDT_CR_WDRSTT RSWDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_CR_WDRSTT_Msk instead */
#define RSWDT_CR_KEY_Pos 24 /**< (RSWDT_CR) Password Position */
#define RSWDT_CR_KEY_Msk (_U_(0xFF) << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Password Mask */
#define RSWDT_CR_KEY(value) (RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))
#define RSWDT_CR_KEY_PASSWD_Val _U_(0xC4) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. */
#define RSWDT_CR_KEY_PASSWD (RSWDT_CR_KEY_PASSWD_Val << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. Position */
#define RSWDT_CR_MASK _U_(0xFF000001) /**< \deprecated (RSWDT_CR) Register MASK (Use RSWDT_CR_Msk instead) */
#define RSWDT_CR_Msk _U_(0xFF000001) /**< (RSWDT_CR) Register Mask */
/* -------- RSWDT_MR : (RSWDT Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */
uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */
uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */
uint32_t :1; /**< bit: 14 Reserved */
uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */
uint32_t ALLONES:12; /**< bit: 16..27 Must Always Be Written with 0xFFF */
uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */
uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSWDT_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSWDT_MR_OFFSET (0x04) /**< (RSWDT_MR) Mode Register Offset */
#define RSWDT_MR_WDV_Pos 0 /**< (RSWDT_MR) Watchdog Counter Value Position */
#define RSWDT_MR_WDV_Msk (_U_(0xFFF) << RSWDT_MR_WDV_Pos) /**< (RSWDT_MR) Watchdog Counter Value Mask */
#define RSWDT_MR_WDV(value) (RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))
#define RSWDT_MR_WDFIEN_Pos 12 /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Position */
#define RSWDT_MR_WDFIEN_Msk (_U_(0x1) << RSWDT_MR_WDFIEN_Pos) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Mask */
#define RSWDT_MR_WDFIEN RSWDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDFIEN_Msk instead */
#define RSWDT_MR_WDRSTEN_Pos 13 /**< (RSWDT_MR) Watchdog Reset Enable Position */
#define RSWDT_MR_WDRSTEN_Msk (_U_(0x1) << RSWDT_MR_WDRSTEN_Pos) /**< (RSWDT_MR) Watchdog Reset Enable Mask */
#define RSWDT_MR_WDRSTEN RSWDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDRSTEN_Msk instead */
#define RSWDT_MR_WDDIS_Pos 15 /**< (RSWDT_MR) Watchdog Disable Position */
#define RSWDT_MR_WDDIS_Msk (_U_(0x1) << RSWDT_MR_WDDIS_Pos) /**< (RSWDT_MR) Watchdog Disable Mask */
#define RSWDT_MR_WDDIS RSWDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDIS_Msk instead */
#define RSWDT_MR_ALLONES_Pos 16 /**< (RSWDT_MR) Must Always Be Written with 0xFFF Position */
#define RSWDT_MR_ALLONES_Msk (_U_(0xFFF) << RSWDT_MR_ALLONES_Pos) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Mask */
#define RSWDT_MR_ALLONES(value) (RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))
#define RSWDT_MR_WDDBGHLT_Pos 28 /**< (RSWDT_MR) Watchdog Debug Halt Position */
#define RSWDT_MR_WDDBGHLT_Msk (_U_(0x1) << RSWDT_MR_WDDBGHLT_Pos) /**< (RSWDT_MR) Watchdog Debug Halt Mask */
#define RSWDT_MR_WDDBGHLT RSWDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDBGHLT_Msk instead */
#define RSWDT_MR_WDIDLEHLT_Pos 29 /**< (RSWDT_MR) Watchdog Idle Halt Position */
#define RSWDT_MR_WDIDLEHLT_Msk (_U_(0x1) << RSWDT_MR_WDIDLEHLT_Pos) /**< (RSWDT_MR) Watchdog Idle Halt Mask */
#define RSWDT_MR_WDIDLEHLT RSWDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDIDLEHLT_Msk instead */
#define RSWDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (RSWDT_MR) Register MASK (Use RSWDT_MR_Msk instead) */
#define RSWDT_MR_Msk _U_(0x3FFFBFFF) /**< (RSWDT_MR) Register Mask */
/* -------- RSWDT_SR : (RSWDT Offset: 0x08) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RSWDT_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSWDT_SR_OFFSET (0x08) /**< (RSWDT_SR) Status Register Offset */
#define RSWDT_SR_WDUNF_Pos 0 /**< (RSWDT_SR) Watchdog Underflow Position */
#define RSWDT_SR_WDUNF_Msk (_U_(0x1) << RSWDT_SR_WDUNF_Pos) /**< (RSWDT_SR) Watchdog Underflow Mask */
#define RSWDT_SR_WDUNF RSWDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_SR_WDUNF_Msk instead */
#define RSWDT_SR_MASK _U_(0x01) /**< \deprecated (RSWDT_SR) Register MASK (Use RSWDT_SR_Msk instead) */
#define RSWDT_SR_Msk _U_(0x01) /**< (RSWDT_SR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief RSWDT hardware registers */
typedef struct {
__O uint32_t RSWDT_CR; /**< (RSWDT Offset: 0x00) Control Register */
__IO uint32_t RSWDT_MR; /**< (RSWDT Offset: 0x04) Mode Register */
__I uint32_t RSWDT_SR; /**< (RSWDT Offset: 0x08) Status Register */
} Rswdt;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief RSWDT hardware registers */
typedef struct {
__O RSWDT_CR_Type RSWDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO RSWDT_MR_Type RSWDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I RSWDT_SR_Type RSWDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */
} Rswdt;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Reinforced Safety Watchdog Timer */
#endif /* _SAME70_RSWDT_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for RTC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RTC_COMPONENT_H_
#define _SAME70_RTC_COMPONENT_H_
#define _SAME70_RTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Real-time Clock
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RTC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define RTC_6056 /**< (RTC) Module ID */
#define REV_RTC ZB /**< (RTC) Module revision */
/* -------- RTC_CR : (RTC Offset: 0x00) (R/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t UPDTIM:1; /**< bit: 0 Update Request Time Register */
uint32_t UPDCAL:1; /**< bit: 1 Update Request Calendar Register */
uint32_t :6; /**< bit: 2..7 Reserved */
uint32_t TIMEVSEL:2; /**< bit: 8..9 Time Event Selection */
uint32_t :6; /**< bit: 10..15 Reserved */
uint32_t CALEVSEL:2; /**< bit: 16..17 Calendar Event Selection */
uint32_t :14; /**< bit: 18..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_CR_OFFSET (0x00) /**< (RTC_CR) Control Register Offset */
#define RTC_CR_UPDTIM_Pos 0 /**< (RTC_CR) Update Request Time Register Position */
#define RTC_CR_UPDTIM_Msk (_U_(0x1) << RTC_CR_UPDTIM_Pos) /**< (RTC_CR) Update Request Time Register Mask */
#define RTC_CR_UPDTIM RTC_CR_UPDTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDTIM_Msk instead */
#define RTC_CR_UPDCAL_Pos 1 /**< (RTC_CR) Update Request Calendar Register Position */
#define RTC_CR_UPDCAL_Msk (_U_(0x1) << RTC_CR_UPDCAL_Pos) /**< (RTC_CR) Update Request Calendar Register Mask */
#define RTC_CR_UPDCAL RTC_CR_UPDCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDCAL_Msk instead */
#define RTC_CR_TIMEVSEL_Pos 8 /**< (RTC_CR) Time Event Selection Position */
#define RTC_CR_TIMEVSEL_Msk (_U_(0x3) << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Time Event Selection Mask */
#define RTC_CR_TIMEVSEL(value) (RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))
#define RTC_CR_TIMEVSEL_MINUTE_Val _U_(0x0) /**< (RTC_CR) Minute change */
#define RTC_CR_TIMEVSEL_HOUR_Val _U_(0x1) /**< (RTC_CR) Hour change */
#define RTC_CR_TIMEVSEL_MIDNIGHT_Val _U_(0x2) /**< (RTC_CR) Every day at midnight */
#define RTC_CR_TIMEVSEL_NOON_Val _U_(0x3) /**< (RTC_CR) Every day at noon */
#define RTC_CR_TIMEVSEL_MINUTE (RTC_CR_TIMEVSEL_MINUTE_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Minute change Position */
#define RTC_CR_TIMEVSEL_HOUR (RTC_CR_TIMEVSEL_HOUR_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Hour change Position */
#define RTC_CR_TIMEVSEL_MIDNIGHT (RTC_CR_TIMEVSEL_MIDNIGHT_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at midnight Position */
#define RTC_CR_TIMEVSEL_NOON (RTC_CR_TIMEVSEL_NOON_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at noon Position */
#define RTC_CR_CALEVSEL_Pos 16 /**< (RTC_CR) Calendar Event Selection Position */
#define RTC_CR_CALEVSEL_Msk (_U_(0x3) << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Calendar Event Selection Mask */
#define RTC_CR_CALEVSEL(value) (RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))
#define RTC_CR_CALEVSEL_WEEK_Val _U_(0x0) /**< (RTC_CR) Week change (every Monday at time 00:00:00) */
#define RTC_CR_CALEVSEL_MONTH_Val _U_(0x1) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
#define RTC_CR_CALEVSEL_YEAR_Val _U_(0x2) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) */
#define RTC_CR_CALEVSEL_WEEK (RTC_CR_CALEVSEL_WEEK_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Week change (every Monday at time 00:00:00) Position */
#define RTC_CR_CALEVSEL_MONTH (RTC_CR_CALEVSEL_MONTH_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) Position */
#define RTC_CR_CALEVSEL_YEAR (RTC_CR_CALEVSEL_YEAR_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) Position */
#define RTC_CR_MASK _U_(0x30303) /**< \deprecated (RTC_CR) Register MASK (Use RTC_CR_Msk instead) */
#define RTC_CR_Msk _U_(0x30303) /**< (RTC_CR) Register Mask */
/* -------- RTC_MR : (RTC Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HRMOD:1; /**< bit: 0 12-/24-hour Mode */
uint32_t PERSIAN:1; /**< bit: 1 PERSIAN Calendar */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t NEGPPM:1; /**< bit: 4 NEGative PPM Correction */
uint32_t :3; /**< bit: 5..7 Reserved */
uint32_t CORRECTION:7; /**< bit: 8..14 Slow Clock Correction */
uint32_t HIGHPPM:1; /**< bit: 15 HIGH PPM Correction */
uint32_t OUT0:3; /**< bit: 16..18 RTCOUT0 OutputSource Selection */
uint32_t :1; /**< bit: 19 Reserved */
uint32_t OUT1:3; /**< bit: 20..22 RTCOUT1 Output Source Selection */
uint32_t :1; /**< bit: 23 Reserved */
uint32_t THIGH:3; /**< bit: 24..26 High Duration of the Output Pulse */
uint32_t :1; /**< bit: 27 Reserved */
uint32_t TPERIOD:2; /**< bit: 28..29 Period of the Output Pulse */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_MR_OFFSET (0x04) /**< (RTC_MR) Mode Register Offset */
#define RTC_MR_HRMOD_Pos 0 /**< (RTC_MR) 12-/24-hour Mode Position */
#define RTC_MR_HRMOD_Msk (_U_(0x1) << RTC_MR_HRMOD_Pos) /**< (RTC_MR) 12-/24-hour Mode Mask */
#define RTC_MR_HRMOD RTC_MR_HRMOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HRMOD_Msk instead */
#define RTC_MR_PERSIAN_Pos 1 /**< (RTC_MR) PERSIAN Calendar Position */
#define RTC_MR_PERSIAN_Msk (_U_(0x1) << RTC_MR_PERSIAN_Pos) /**< (RTC_MR) PERSIAN Calendar Mask */
#define RTC_MR_PERSIAN RTC_MR_PERSIAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_PERSIAN_Msk instead */
#define RTC_MR_NEGPPM_Pos 4 /**< (RTC_MR) NEGative PPM Correction Position */
#define RTC_MR_NEGPPM_Msk (_U_(0x1) << RTC_MR_NEGPPM_Pos) /**< (RTC_MR) NEGative PPM Correction Mask */
#define RTC_MR_NEGPPM RTC_MR_NEGPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_NEGPPM_Msk instead */
#define RTC_MR_CORRECTION_Pos 8 /**< (RTC_MR) Slow Clock Correction Position */
#define RTC_MR_CORRECTION_Msk (_U_(0x7F) << RTC_MR_CORRECTION_Pos) /**< (RTC_MR) Slow Clock Correction Mask */
#define RTC_MR_CORRECTION(value) (RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))
#define RTC_MR_HIGHPPM_Pos 15 /**< (RTC_MR) HIGH PPM Correction Position */
#define RTC_MR_HIGHPPM_Msk (_U_(0x1) << RTC_MR_HIGHPPM_Pos) /**< (RTC_MR) HIGH PPM Correction Mask */
#define RTC_MR_HIGHPPM RTC_MR_HIGHPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HIGHPPM_Msk instead */
#define RTC_MR_OUT0_Pos 16 /**< (RTC_MR) RTCOUT0 OutputSource Selection Position */
#define RTC_MR_OUT0_Msk (_U_(0x7) << RTC_MR_OUT0_Pos) /**< (RTC_MR) RTCOUT0 OutputSource Selection Mask */
#define RTC_MR_OUT0(value) (RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))
#define RTC_MR_OUT0_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */
#define RTC_MR_OUT0_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */
#define RTC_MR_OUT0_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */
#define RTC_MR_OUT0_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */
#define RTC_MR_OUT0_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */
#define RTC_MR_OUT0_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */
#define RTC_MR_OUT0_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */
#define RTC_MR_OUT0_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */
#define RTC_MR_OUT0_NO_WAVE (RTC_MR_OUT0_NO_WAVE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */
#define RTC_MR_OUT0_FREQ1HZ (RTC_MR_OUT0_FREQ1HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 1 Hz square wave Position */
#define RTC_MR_OUT0_FREQ32HZ (RTC_MR_OUT0_FREQ32HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 32 Hz square wave Position */
#define RTC_MR_OUT0_FREQ64HZ (RTC_MR_OUT0_FREQ64HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 64 Hz square wave Position */
#define RTC_MR_OUT0_FREQ512HZ (RTC_MR_OUT0_FREQ512HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 512 Hz square wave Position */
#define RTC_MR_OUT0_ALARM_TOGGLE (RTC_MR_OUT0_ALARM_TOGGLE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */
#define RTC_MR_OUT0_ALARM_FLAG (RTC_MR_OUT0_ALARM_FLAG_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */
#define RTC_MR_OUT0_PROG_PULSE (RTC_MR_OUT0_PROG_PULSE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */
#define RTC_MR_OUT1_Pos 20 /**< (RTC_MR) RTCOUT1 Output Source Selection Position */
#define RTC_MR_OUT1_Msk (_U_(0x7) << RTC_MR_OUT1_Pos) /**< (RTC_MR) RTCOUT1 Output Source Selection Mask */
#define RTC_MR_OUT1(value) (RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))
#define RTC_MR_OUT1_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */
#define RTC_MR_OUT1_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */
#define RTC_MR_OUT1_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */
#define RTC_MR_OUT1_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */
#define RTC_MR_OUT1_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */
#define RTC_MR_OUT1_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */
#define RTC_MR_OUT1_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */
#define RTC_MR_OUT1_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */
#define RTC_MR_OUT1_NO_WAVE (RTC_MR_OUT1_NO_WAVE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */
#define RTC_MR_OUT1_FREQ1HZ (RTC_MR_OUT1_FREQ1HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 1 Hz square wave Position */
#define RTC_MR_OUT1_FREQ32HZ (RTC_MR_OUT1_FREQ32HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 32 Hz square wave Position */
#define RTC_MR_OUT1_FREQ64HZ (RTC_MR_OUT1_FREQ64HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 64 Hz square wave Position */
#define RTC_MR_OUT1_FREQ512HZ (RTC_MR_OUT1_FREQ512HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 512 Hz square wave Position */
#define RTC_MR_OUT1_ALARM_TOGGLE (RTC_MR_OUT1_ALARM_TOGGLE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */
#define RTC_MR_OUT1_ALARM_FLAG (RTC_MR_OUT1_ALARM_FLAG_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */
#define RTC_MR_OUT1_PROG_PULSE (RTC_MR_OUT1_PROG_PULSE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */
#define RTC_MR_THIGH_Pos 24 /**< (RTC_MR) High Duration of the Output Pulse Position */
#define RTC_MR_THIGH_Msk (_U_(0x7) << RTC_MR_THIGH_Pos) /**< (RTC_MR) High Duration of the Output Pulse Mask */
#define RTC_MR_THIGH(value) (RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))
#define RTC_MR_THIGH_H_31MS_Val _U_(0x0) /**< (RTC_MR) 31.2 ms */
#define RTC_MR_THIGH_H_16MS_Val _U_(0x1) /**< (RTC_MR) 15.6 ms */
#define RTC_MR_THIGH_H_4MS_Val _U_(0x2) /**< (RTC_MR) 3.91 ms */
#define RTC_MR_THIGH_H_976US_Val _U_(0x3) /**< (RTC_MR) 976 us */
#define RTC_MR_THIGH_H_488US_Val _U_(0x4) /**< (RTC_MR) 488 us */
#define RTC_MR_THIGH_H_122US_Val _U_(0x5) /**< (RTC_MR) 122 us */
#define RTC_MR_THIGH_H_30US_Val _U_(0x6) /**< (RTC_MR) 30.5 us */
#define RTC_MR_THIGH_H_15US_Val _U_(0x7) /**< (RTC_MR) 15.2 us */
#define RTC_MR_THIGH_H_31MS (RTC_MR_THIGH_H_31MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 31.2 ms Position */
#define RTC_MR_THIGH_H_16MS (RTC_MR_THIGH_H_16MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.6 ms Position */
#define RTC_MR_THIGH_H_4MS (RTC_MR_THIGH_H_4MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 3.91 ms Position */
#define RTC_MR_THIGH_H_976US (RTC_MR_THIGH_H_976US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 976 us Position */
#define RTC_MR_THIGH_H_488US (RTC_MR_THIGH_H_488US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 488 us Position */
#define RTC_MR_THIGH_H_122US (RTC_MR_THIGH_H_122US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 122 us Position */
#define RTC_MR_THIGH_H_30US (RTC_MR_THIGH_H_30US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 30.5 us Position */
#define RTC_MR_THIGH_H_15US (RTC_MR_THIGH_H_15US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.2 us Position */
#define RTC_MR_TPERIOD_Pos 28 /**< (RTC_MR) Period of the Output Pulse Position */
#define RTC_MR_TPERIOD_Msk (_U_(0x3) << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) Period of the Output Pulse Mask */
#define RTC_MR_TPERIOD(value) (RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))
#define RTC_MR_TPERIOD_P_1S_Val _U_(0x0) /**< (RTC_MR) 1 second */
#define RTC_MR_TPERIOD_P_500MS_Val _U_(0x1) /**< (RTC_MR) 500 ms */
#define RTC_MR_TPERIOD_P_250MS_Val _U_(0x2) /**< (RTC_MR) 250 ms */
#define RTC_MR_TPERIOD_P_125MS_Val _U_(0x3) /**< (RTC_MR) 125 ms */
#define RTC_MR_TPERIOD_P_1S (RTC_MR_TPERIOD_P_1S_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 1 second Position */
#define RTC_MR_TPERIOD_P_500MS (RTC_MR_TPERIOD_P_500MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 500 ms Position */
#define RTC_MR_TPERIOD_P_250MS (RTC_MR_TPERIOD_P_250MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 250 ms Position */
#define RTC_MR_TPERIOD_P_125MS (RTC_MR_TPERIOD_P_125MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 125 ms Position */
#define RTC_MR_MASK _U_(0x3777FF13) /**< \deprecated (RTC_MR) Register MASK (Use RTC_MR_Msk instead) */
#define RTC_MR_Msk _U_(0x3777FF13) /**< (RTC_MR) Register Mask */
/* -------- RTC_TIMR : (RTC Offset: 0x08) (R/W 32) Time Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SEC:7; /**< bit: 0..6 Current Second */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t MIN:7; /**< bit: 8..14 Current Minute */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t HOUR:6; /**< bit: 16..21 Current Hour */
uint32_t AMPM:1; /**< bit: 22 Ante Meridiem Post Meridiem Indicator */
uint32_t :9; /**< bit: 23..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_TIMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_TIMR_OFFSET (0x08) /**< (RTC_TIMR) Time Register Offset */
#define RTC_TIMR_SEC_Pos 0 /**< (RTC_TIMR) Current Second Position */
#define RTC_TIMR_SEC_Msk (_U_(0x7F) << RTC_TIMR_SEC_Pos) /**< (RTC_TIMR) Current Second Mask */
#define RTC_TIMR_SEC(value) (RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))
#define RTC_TIMR_MIN_Pos 8 /**< (RTC_TIMR) Current Minute Position */
#define RTC_TIMR_MIN_Msk (_U_(0x7F) << RTC_TIMR_MIN_Pos) /**< (RTC_TIMR) Current Minute Mask */
#define RTC_TIMR_MIN(value) (RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))
#define RTC_TIMR_HOUR_Pos 16 /**< (RTC_TIMR) Current Hour Position */
#define RTC_TIMR_HOUR_Msk (_U_(0x3F) << RTC_TIMR_HOUR_Pos) /**< (RTC_TIMR) Current Hour Mask */
#define RTC_TIMR_HOUR(value) (RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))
#define RTC_TIMR_AMPM_Pos 22 /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Position */
#define RTC_TIMR_AMPM_Msk (_U_(0x1) << RTC_TIMR_AMPM_Pos) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Mask */
#define RTC_TIMR_AMPM RTC_TIMR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMR_AMPM_Msk instead */
#define RTC_TIMR_MASK _U_(0x7F7F7F) /**< \deprecated (RTC_TIMR) Register MASK (Use RTC_TIMR_Msk instead) */
#define RTC_TIMR_Msk _U_(0x7F7F7F) /**< (RTC_TIMR) Register Mask */
/* -------- RTC_CALR : (RTC Offset: 0x0c) (R/W 32) Calendar Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CENT:7; /**< bit: 0..6 Current Century */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t YEAR:8; /**< bit: 8..15 Current Year */
uint32_t MONTH:5; /**< bit: 16..20 Current Month */
uint32_t DAY:3; /**< bit: 21..23 Current Day in Current Week */
uint32_t DATE:6; /**< bit: 24..29 Current Day in Current Month */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_CALR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_CALR_OFFSET (0x0C) /**< (RTC_CALR) Calendar Register Offset */
#define RTC_CALR_CENT_Pos 0 /**< (RTC_CALR) Current Century Position */
#define RTC_CALR_CENT_Msk (_U_(0x7F) << RTC_CALR_CENT_Pos) /**< (RTC_CALR) Current Century Mask */
#define RTC_CALR_CENT(value) (RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))
#define RTC_CALR_YEAR_Pos 8 /**< (RTC_CALR) Current Year Position */
#define RTC_CALR_YEAR_Msk (_U_(0xFF) << RTC_CALR_YEAR_Pos) /**< (RTC_CALR) Current Year Mask */
#define RTC_CALR_YEAR(value) (RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))
#define RTC_CALR_MONTH_Pos 16 /**< (RTC_CALR) Current Month Position */
#define RTC_CALR_MONTH_Msk (_U_(0x1F) << RTC_CALR_MONTH_Pos) /**< (RTC_CALR) Current Month Mask */
#define RTC_CALR_MONTH(value) (RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))
#define RTC_CALR_DAY_Pos 21 /**< (RTC_CALR) Current Day in Current Week Position */
#define RTC_CALR_DAY_Msk (_U_(0x7) << RTC_CALR_DAY_Pos) /**< (RTC_CALR) Current Day in Current Week Mask */
#define RTC_CALR_DAY(value) (RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))
#define RTC_CALR_DATE_Pos 24 /**< (RTC_CALR) Current Day in Current Month Position */
#define RTC_CALR_DATE_Msk (_U_(0x3F) << RTC_CALR_DATE_Pos) /**< (RTC_CALR) Current Day in Current Month Mask */
#define RTC_CALR_DATE(value) (RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))
#define RTC_CALR_MASK _U_(0x3FFFFF7F) /**< \deprecated (RTC_CALR) Register MASK (Use RTC_CALR_Msk instead) */
#define RTC_CALR_Msk _U_(0x3FFFFF7F) /**< (RTC_CALR) Register Mask */
/* -------- RTC_TIMALR : (RTC Offset: 0x10) (R/W 32) Time Alarm Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SEC:7; /**< bit: 0..6 Second Alarm */
uint32_t SECEN:1; /**< bit: 7 Second Alarm Enable */
uint32_t MIN:7; /**< bit: 8..14 Minute Alarm */
uint32_t MINEN:1; /**< bit: 15 Minute Alarm Enable */
uint32_t HOUR:6; /**< bit: 16..21 Hour Alarm */
uint32_t AMPM:1; /**< bit: 22 AM/PM Indicator */
uint32_t HOUREN:1; /**< bit: 23 Hour Alarm Enable */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_TIMALR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_TIMALR_OFFSET (0x10) /**< (RTC_TIMALR) Time Alarm Register Offset */
#define RTC_TIMALR_SEC_Pos 0 /**< (RTC_TIMALR) Second Alarm Position */
#define RTC_TIMALR_SEC_Msk (_U_(0x7F) << RTC_TIMALR_SEC_Pos) /**< (RTC_TIMALR) Second Alarm Mask */
#define RTC_TIMALR_SEC(value) (RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))
#define RTC_TIMALR_SECEN_Pos 7 /**< (RTC_TIMALR) Second Alarm Enable Position */
#define RTC_TIMALR_SECEN_Msk (_U_(0x1) << RTC_TIMALR_SECEN_Pos) /**< (RTC_TIMALR) Second Alarm Enable Mask */
#define RTC_TIMALR_SECEN RTC_TIMALR_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_SECEN_Msk instead */
#define RTC_TIMALR_MIN_Pos 8 /**< (RTC_TIMALR) Minute Alarm Position */
#define RTC_TIMALR_MIN_Msk (_U_(0x7F) << RTC_TIMALR_MIN_Pos) /**< (RTC_TIMALR) Minute Alarm Mask */
#define RTC_TIMALR_MIN(value) (RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))
#define RTC_TIMALR_MINEN_Pos 15 /**< (RTC_TIMALR) Minute Alarm Enable Position */
#define RTC_TIMALR_MINEN_Msk (_U_(0x1) << RTC_TIMALR_MINEN_Pos) /**< (RTC_TIMALR) Minute Alarm Enable Mask */
#define RTC_TIMALR_MINEN RTC_TIMALR_MINEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_MINEN_Msk instead */
#define RTC_TIMALR_HOUR_Pos 16 /**< (RTC_TIMALR) Hour Alarm Position */
#define RTC_TIMALR_HOUR_Msk (_U_(0x3F) << RTC_TIMALR_HOUR_Pos) /**< (RTC_TIMALR) Hour Alarm Mask */
#define RTC_TIMALR_HOUR(value) (RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))
#define RTC_TIMALR_AMPM_Pos 22 /**< (RTC_TIMALR) AM/PM Indicator Position */
#define RTC_TIMALR_AMPM_Msk (_U_(0x1) << RTC_TIMALR_AMPM_Pos) /**< (RTC_TIMALR) AM/PM Indicator Mask */
#define RTC_TIMALR_AMPM RTC_TIMALR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_AMPM_Msk instead */
#define RTC_TIMALR_HOUREN_Pos 23 /**< (RTC_TIMALR) Hour Alarm Enable Position */
#define RTC_TIMALR_HOUREN_Msk (_U_(0x1) << RTC_TIMALR_HOUREN_Pos) /**< (RTC_TIMALR) Hour Alarm Enable Mask */
#define RTC_TIMALR_HOUREN RTC_TIMALR_HOUREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_HOUREN_Msk instead */
#define RTC_TIMALR_MASK _U_(0xFFFFFF) /**< \deprecated (RTC_TIMALR) Register MASK (Use RTC_TIMALR_Msk instead) */
#define RTC_TIMALR_Msk _U_(0xFFFFFF) /**< (RTC_TIMALR) Register Mask */
/* -------- RTC_CALALR : (RTC Offset: 0x14) (R/W 32) Calendar Alarm Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :16; /**< bit: 0..15 Reserved */
uint32_t MONTH:5; /**< bit: 16..20 Month Alarm */
uint32_t :2; /**< bit: 21..22 Reserved */
uint32_t MTHEN:1; /**< bit: 23 Month Alarm Enable */
uint32_t DATE:6; /**< bit: 24..29 Date Alarm */
uint32_t :1; /**< bit: 30 Reserved */
uint32_t DATEEN:1; /**< bit: 31 Date Alarm Enable */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_CALALR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_CALALR_OFFSET (0x14) /**< (RTC_CALALR) Calendar Alarm Register Offset */
#define RTC_CALALR_MONTH_Pos 16 /**< (RTC_CALALR) Month Alarm Position */
#define RTC_CALALR_MONTH_Msk (_U_(0x1F) << RTC_CALALR_MONTH_Pos) /**< (RTC_CALALR) Month Alarm Mask */
#define RTC_CALALR_MONTH(value) (RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))
#define RTC_CALALR_MTHEN_Pos 23 /**< (RTC_CALALR) Month Alarm Enable Position */
#define RTC_CALALR_MTHEN_Msk (_U_(0x1) << RTC_CALALR_MTHEN_Pos) /**< (RTC_CALALR) Month Alarm Enable Mask */
#define RTC_CALALR_MTHEN RTC_CALALR_MTHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_MTHEN_Msk instead */
#define RTC_CALALR_DATE_Pos 24 /**< (RTC_CALALR) Date Alarm Position */
#define RTC_CALALR_DATE_Msk (_U_(0x3F) << RTC_CALALR_DATE_Pos) /**< (RTC_CALALR) Date Alarm Mask */
#define RTC_CALALR_DATE(value) (RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))
#define RTC_CALALR_DATEEN_Pos 31 /**< (RTC_CALALR) Date Alarm Enable Position */
#define RTC_CALALR_DATEEN_Msk (_U_(0x1) << RTC_CALALR_DATEEN_Pos) /**< (RTC_CALALR) Date Alarm Enable Mask */
#define RTC_CALALR_DATEEN RTC_CALALR_DATEEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_DATEEN_Msk instead */
#define RTC_CALALR_MASK _U_(0xBF9F0000) /**< \deprecated (RTC_CALALR) Register MASK (Use RTC_CALALR_Msk instead) */
#define RTC_CALALR_Msk _U_(0xBF9F0000) /**< (RTC_CALALR) Register Mask */
/* -------- RTC_SR : (RTC Offset: 0x18) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ACKUPD:1; /**< bit: 0 Acknowledge for Update */
uint32_t ALARM:1; /**< bit: 1 Alarm Flag */
uint32_t SEC:1; /**< bit: 2 Second Event */
uint32_t TIMEV:1; /**< bit: 3 Time Event */
uint32_t CALEV:1; /**< bit: 4 Calendar Event */
uint32_t TDERR:1; /**< bit: 5 Time and/or Date Free Running Error */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_SR_OFFSET (0x18) /**< (RTC_SR) Status Register Offset */
#define RTC_SR_ACKUPD_Pos 0 /**< (RTC_SR) Acknowledge for Update Position */
#define RTC_SR_ACKUPD_Msk (_U_(0x1) << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Acknowledge for Update Mask */
#define RTC_SR_ACKUPD RTC_SR_ACKUPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ACKUPD_Msk instead */
#define RTC_SR_ACKUPD_FREERUN_Val _U_(0x0) /**< (RTC_SR) Time and calendar registers cannot be updated. */
#define RTC_SR_ACKUPD_UPDATE_Val _U_(0x1) /**< (RTC_SR) Time and calendar registers can be updated. */
#define RTC_SR_ACKUPD_FREERUN (RTC_SR_ACKUPD_FREERUN_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers cannot be updated. Position */
#define RTC_SR_ACKUPD_UPDATE (RTC_SR_ACKUPD_UPDATE_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers can be updated. Position */
#define RTC_SR_ALARM_Pos 1 /**< (RTC_SR) Alarm Flag Position */
#define RTC_SR_ALARM_Msk (_U_(0x1) << RTC_SR_ALARM_Pos) /**< (RTC_SR) Alarm Flag Mask */
#define RTC_SR_ALARM RTC_SR_ALARM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ALARM_Msk instead */
#define RTC_SR_ALARM_NO_ALARMEVENT_Val _U_(0x0) /**< (RTC_SR) No alarm matching condition occurred. */
#define RTC_SR_ALARM_ALARMEVENT_Val _U_(0x1) /**< (RTC_SR) An alarm matching condition has occurred. */
#define RTC_SR_ALARM_NO_ALARMEVENT (RTC_SR_ALARM_NO_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) No alarm matching condition occurred. Position */
#define RTC_SR_ALARM_ALARMEVENT (RTC_SR_ALARM_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) An alarm matching condition has occurred. Position */
#define RTC_SR_SEC_Pos 2 /**< (RTC_SR) Second Event Position */
#define RTC_SR_SEC_Msk (_U_(0x1) << RTC_SR_SEC_Pos) /**< (RTC_SR) Second Event Mask */
#define RTC_SR_SEC RTC_SR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_SEC_Msk instead */
#define RTC_SR_SEC_NO_SECEVENT_Val _U_(0x0) /**< (RTC_SR) No second event has occurred since the last clear. */
#define RTC_SR_SEC_SECEVENT_Val _U_(0x1) /**< (RTC_SR) At least one second event has occurred since the last clear. */
#define RTC_SR_SEC_NO_SECEVENT (RTC_SR_SEC_NO_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) No second event has occurred since the last clear. Position */
#define RTC_SR_SEC_SECEVENT (RTC_SR_SEC_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) At least one second event has occurred since the last clear. Position */
#define RTC_SR_TIMEV_Pos 3 /**< (RTC_SR) Time Event Position */
#define RTC_SR_TIMEV_Msk (_U_(0x1) << RTC_SR_TIMEV_Pos) /**< (RTC_SR) Time Event Mask */
#define RTC_SR_TIMEV RTC_SR_TIMEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TIMEV_Msk instead */
#define RTC_SR_TIMEV_NO_TIMEVENT_Val _U_(0x0) /**< (RTC_SR) No time event has occurred since the last clear. */
#define RTC_SR_TIMEV_TIMEVENT_Val _U_(0x1) /**< (RTC_SR) At least one time event has occurred since the last clear. */
#define RTC_SR_TIMEV_NO_TIMEVENT (RTC_SR_TIMEV_NO_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) No time event has occurred since the last clear. Position */
#define RTC_SR_TIMEV_TIMEVENT (RTC_SR_TIMEV_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) At least one time event has occurred since the last clear. Position */
#define RTC_SR_CALEV_Pos 4 /**< (RTC_SR) Calendar Event Position */
#define RTC_SR_CALEV_Msk (_U_(0x1) << RTC_SR_CALEV_Pos) /**< (RTC_SR) Calendar Event Mask */
#define RTC_SR_CALEV RTC_SR_CALEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_CALEV_Msk instead */
#define RTC_SR_CALEV_NO_CALEVENT_Val _U_(0x0) /**< (RTC_SR) No calendar event has occurred since the last clear. */
#define RTC_SR_CALEV_CALEVENT_Val _U_(0x1) /**< (RTC_SR) At least one calendar event has occurred since the last clear. */
#define RTC_SR_CALEV_NO_CALEVENT (RTC_SR_CALEV_NO_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) No calendar event has occurred since the last clear. Position */
#define RTC_SR_CALEV_CALEVENT (RTC_SR_CALEV_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) At least one calendar event has occurred since the last clear. Position */
#define RTC_SR_TDERR_Pos 5 /**< (RTC_SR) Time and/or Date Free Running Error Position */
#define RTC_SR_TDERR_Msk (_U_(0x1) << RTC_SR_TDERR_Pos) /**< (RTC_SR) Time and/or Date Free Running Error Mask */
#define RTC_SR_TDERR RTC_SR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TDERR_Msk instead */
#define RTC_SR_TDERR_CORRECT_Val _U_(0x0) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */
#define RTC_SR_TDERR_ERR_TIMEDATE_Val _U_(0x1) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
#define RTC_SR_TDERR_CORRECT (RTC_SR_TDERR_CORRECT_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). Position */
#define RTC_SR_TDERR_ERR_TIMEDATE (RTC_SR_TDERR_ERR_TIMEDATE_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. Position */
#define RTC_SR_MASK _U_(0x3F) /**< \deprecated (RTC_SR) Register MASK (Use RTC_SR_Msk instead) */
#define RTC_SR_Msk _U_(0x3F) /**< (RTC_SR) Register Mask */
/* -------- RTC_SCCR : (RTC Offset: 0x1c) (/W 32) Status Clear Command Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ACKCLR:1; /**< bit: 0 Acknowledge Clear */
uint32_t ALRCLR:1; /**< bit: 1 Alarm Clear */
uint32_t SECCLR:1; /**< bit: 2 Second Clear */
uint32_t TIMCLR:1; /**< bit: 3 Time Clear */
uint32_t CALCLR:1; /**< bit: 4 Calendar Clear */
uint32_t TDERRCLR:1; /**< bit: 5 Time and/or Date Free Running Error Clear */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_SCCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_SCCR_OFFSET (0x1C) /**< (RTC_SCCR) Status Clear Command Register Offset */
#define RTC_SCCR_ACKCLR_Pos 0 /**< (RTC_SCCR) Acknowledge Clear Position */
#define RTC_SCCR_ACKCLR_Msk (_U_(0x1) << RTC_SCCR_ACKCLR_Pos) /**< (RTC_SCCR) Acknowledge Clear Mask */
#define RTC_SCCR_ACKCLR RTC_SCCR_ACKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ACKCLR_Msk instead */
#define RTC_SCCR_ALRCLR_Pos 1 /**< (RTC_SCCR) Alarm Clear Position */
#define RTC_SCCR_ALRCLR_Msk (_U_(0x1) << RTC_SCCR_ALRCLR_Pos) /**< (RTC_SCCR) Alarm Clear Mask */
#define RTC_SCCR_ALRCLR RTC_SCCR_ALRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ALRCLR_Msk instead */
#define RTC_SCCR_SECCLR_Pos 2 /**< (RTC_SCCR) Second Clear Position */
#define RTC_SCCR_SECCLR_Msk (_U_(0x1) << RTC_SCCR_SECCLR_Pos) /**< (RTC_SCCR) Second Clear Mask */
#define RTC_SCCR_SECCLR RTC_SCCR_SECCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_SECCLR_Msk instead */
#define RTC_SCCR_TIMCLR_Pos 3 /**< (RTC_SCCR) Time Clear Position */
#define RTC_SCCR_TIMCLR_Msk (_U_(0x1) << RTC_SCCR_TIMCLR_Pos) /**< (RTC_SCCR) Time Clear Mask */
#define RTC_SCCR_TIMCLR RTC_SCCR_TIMCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TIMCLR_Msk instead */
#define RTC_SCCR_CALCLR_Pos 4 /**< (RTC_SCCR) Calendar Clear Position */
#define RTC_SCCR_CALCLR_Msk (_U_(0x1) << RTC_SCCR_CALCLR_Pos) /**< (RTC_SCCR) Calendar Clear Mask */
#define RTC_SCCR_CALCLR RTC_SCCR_CALCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_CALCLR_Msk instead */
#define RTC_SCCR_TDERRCLR_Pos 5 /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Position */
#define RTC_SCCR_TDERRCLR_Msk (_U_(0x1) << RTC_SCCR_TDERRCLR_Pos) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Mask */
#define RTC_SCCR_TDERRCLR RTC_SCCR_TDERRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TDERRCLR_Msk instead */
#define RTC_SCCR_MASK _U_(0x3F) /**< \deprecated (RTC_SCCR) Register MASK (Use RTC_SCCR_Msk instead) */
#define RTC_SCCR_Msk _U_(0x3F) /**< (RTC_SCCR) Register Mask */
/* -------- RTC_IER : (RTC Offset: 0x20) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ACKEN:1; /**< bit: 0 Acknowledge Update Interrupt Enable */
uint32_t ALREN:1; /**< bit: 1 Alarm Interrupt Enable */
uint32_t SECEN:1; /**< bit: 2 Second Event Interrupt Enable */
uint32_t TIMEN:1; /**< bit: 3 Time Event Interrupt Enable */
uint32_t CALEN:1; /**< bit: 4 Calendar Event Interrupt Enable */
uint32_t TDERREN:1; /**< bit: 5 Time and/or Date Error Interrupt Enable */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_IER_OFFSET (0x20) /**< (RTC_IER) Interrupt Enable Register Offset */
#define RTC_IER_ACKEN_Pos 0 /**< (RTC_IER) Acknowledge Update Interrupt Enable Position */
#define RTC_IER_ACKEN_Msk (_U_(0x1) << RTC_IER_ACKEN_Pos) /**< (RTC_IER) Acknowledge Update Interrupt Enable Mask */
#define RTC_IER_ACKEN RTC_IER_ACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ACKEN_Msk instead */
#define RTC_IER_ALREN_Pos 1 /**< (RTC_IER) Alarm Interrupt Enable Position */
#define RTC_IER_ALREN_Msk (_U_(0x1) << RTC_IER_ALREN_Pos) /**< (RTC_IER) Alarm Interrupt Enable Mask */
#define RTC_IER_ALREN RTC_IER_ALREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ALREN_Msk instead */
#define RTC_IER_SECEN_Pos 2 /**< (RTC_IER) Second Event Interrupt Enable Position */
#define RTC_IER_SECEN_Msk (_U_(0x1) << RTC_IER_SECEN_Pos) /**< (RTC_IER) Second Event Interrupt Enable Mask */
#define RTC_IER_SECEN RTC_IER_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_SECEN_Msk instead */
#define RTC_IER_TIMEN_Pos 3 /**< (RTC_IER) Time Event Interrupt Enable Position */
#define RTC_IER_TIMEN_Msk (_U_(0x1) << RTC_IER_TIMEN_Pos) /**< (RTC_IER) Time Event Interrupt Enable Mask */
#define RTC_IER_TIMEN RTC_IER_TIMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TIMEN_Msk instead */
#define RTC_IER_CALEN_Pos 4 /**< (RTC_IER) Calendar Event Interrupt Enable Position */
#define RTC_IER_CALEN_Msk (_U_(0x1) << RTC_IER_CALEN_Pos) /**< (RTC_IER) Calendar Event Interrupt Enable Mask */
#define RTC_IER_CALEN RTC_IER_CALEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_CALEN_Msk instead */
#define RTC_IER_TDERREN_Pos 5 /**< (RTC_IER) Time and/or Date Error Interrupt Enable Position */
#define RTC_IER_TDERREN_Msk (_U_(0x1) << RTC_IER_TDERREN_Pos) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Mask */
#define RTC_IER_TDERREN RTC_IER_TDERREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TDERREN_Msk instead */
#define RTC_IER_MASK _U_(0x3F) /**< \deprecated (RTC_IER) Register MASK (Use RTC_IER_Msk instead) */
#define RTC_IER_Msk _U_(0x3F) /**< (RTC_IER) Register Mask */
/* -------- RTC_IDR : (RTC Offset: 0x24) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ACKDIS:1; /**< bit: 0 Acknowledge Update Interrupt Disable */
uint32_t ALRDIS:1; /**< bit: 1 Alarm Interrupt Disable */
uint32_t SECDIS:1; /**< bit: 2 Second Event Interrupt Disable */
uint32_t TIMDIS:1; /**< bit: 3 Time Event Interrupt Disable */
uint32_t CALDIS:1; /**< bit: 4 Calendar Event Interrupt Disable */
uint32_t TDERRDIS:1; /**< bit: 5 Time and/or Date Error Interrupt Disable */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_IDR_OFFSET (0x24) /**< (RTC_IDR) Interrupt Disable Register Offset */
#define RTC_IDR_ACKDIS_Pos 0 /**< (RTC_IDR) Acknowledge Update Interrupt Disable Position */
#define RTC_IDR_ACKDIS_Msk (_U_(0x1) << RTC_IDR_ACKDIS_Pos) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Mask */
#define RTC_IDR_ACKDIS RTC_IDR_ACKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ACKDIS_Msk instead */
#define RTC_IDR_ALRDIS_Pos 1 /**< (RTC_IDR) Alarm Interrupt Disable Position */
#define RTC_IDR_ALRDIS_Msk (_U_(0x1) << RTC_IDR_ALRDIS_Pos) /**< (RTC_IDR) Alarm Interrupt Disable Mask */
#define RTC_IDR_ALRDIS RTC_IDR_ALRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ALRDIS_Msk instead */
#define RTC_IDR_SECDIS_Pos 2 /**< (RTC_IDR) Second Event Interrupt Disable Position */
#define RTC_IDR_SECDIS_Msk (_U_(0x1) << RTC_IDR_SECDIS_Pos) /**< (RTC_IDR) Second Event Interrupt Disable Mask */
#define RTC_IDR_SECDIS RTC_IDR_SECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_SECDIS_Msk instead */
#define RTC_IDR_TIMDIS_Pos 3 /**< (RTC_IDR) Time Event Interrupt Disable Position */
#define RTC_IDR_TIMDIS_Msk (_U_(0x1) << RTC_IDR_TIMDIS_Pos) /**< (RTC_IDR) Time Event Interrupt Disable Mask */
#define RTC_IDR_TIMDIS RTC_IDR_TIMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TIMDIS_Msk instead */
#define RTC_IDR_CALDIS_Pos 4 /**< (RTC_IDR) Calendar Event Interrupt Disable Position */
#define RTC_IDR_CALDIS_Msk (_U_(0x1) << RTC_IDR_CALDIS_Pos) /**< (RTC_IDR) Calendar Event Interrupt Disable Mask */
#define RTC_IDR_CALDIS RTC_IDR_CALDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_CALDIS_Msk instead */
#define RTC_IDR_TDERRDIS_Pos 5 /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Position */
#define RTC_IDR_TDERRDIS_Msk (_U_(0x1) << RTC_IDR_TDERRDIS_Pos) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Mask */
#define RTC_IDR_TDERRDIS RTC_IDR_TDERRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TDERRDIS_Msk instead */
#define RTC_IDR_MASK _U_(0x3F) /**< \deprecated (RTC_IDR) Register MASK (Use RTC_IDR_Msk instead) */
#define RTC_IDR_Msk _U_(0x3F) /**< (RTC_IDR) Register Mask */
/* -------- RTC_IMR : (RTC Offset: 0x28) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ACK:1; /**< bit: 0 Acknowledge Update Interrupt Mask */
uint32_t ALR:1; /**< bit: 1 Alarm Interrupt Mask */
uint32_t SEC:1; /**< bit: 2 Second Event Interrupt Mask */
uint32_t TIM:1; /**< bit: 3 Time Event Interrupt Mask */
uint32_t CAL:1; /**< bit: 4 Calendar Event Interrupt Mask */
uint32_t TDERR:1; /**< bit: 5 Time and/or Date Error Mask */
uint32_t :26; /**< bit: 6..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_IMR_OFFSET (0x28) /**< (RTC_IMR) Interrupt Mask Register Offset */
#define RTC_IMR_ACK_Pos 0 /**< (RTC_IMR) Acknowledge Update Interrupt Mask Position */
#define RTC_IMR_ACK_Msk (_U_(0x1) << RTC_IMR_ACK_Pos) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Mask */
#define RTC_IMR_ACK RTC_IMR_ACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ACK_Msk instead */
#define RTC_IMR_ALR_Pos 1 /**< (RTC_IMR) Alarm Interrupt Mask Position */
#define RTC_IMR_ALR_Msk (_U_(0x1) << RTC_IMR_ALR_Pos) /**< (RTC_IMR) Alarm Interrupt Mask Mask */
#define RTC_IMR_ALR RTC_IMR_ALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ALR_Msk instead */
#define RTC_IMR_SEC_Pos 2 /**< (RTC_IMR) Second Event Interrupt Mask Position */
#define RTC_IMR_SEC_Msk (_U_(0x1) << RTC_IMR_SEC_Pos) /**< (RTC_IMR) Second Event Interrupt Mask Mask */
#define RTC_IMR_SEC RTC_IMR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_SEC_Msk instead */
#define RTC_IMR_TIM_Pos 3 /**< (RTC_IMR) Time Event Interrupt Mask Position */
#define RTC_IMR_TIM_Msk (_U_(0x1) << RTC_IMR_TIM_Pos) /**< (RTC_IMR) Time Event Interrupt Mask Mask */
#define RTC_IMR_TIM RTC_IMR_TIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TIM_Msk instead */
#define RTC_IMR_CAL_Pos 4 /**< (RTC_IMR) Calendar Event Interrupt Mask Position */
#define RTC_IMR_CAL_Msk (_U_(0x1) << RTC_IMR_CAL_Pos) /**< (RTC_IMR) Calendar Event Interrupt Mask Mask */
#define RTC_IMR_CAL RTC_IMR_CAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_CAL_Msk instead */
#define RTC_IMR_TDERR_Pos 5 /**< (RTC_IMR) Time and/or Date Error Mask Position */
#define RTC_IMR_TDERR_Msk (_U_(0x1) << RTC_IMR_TDERR_Pos) /**< (RTC_IMR) Time and/or Date Error Mask Mask */
#define RTC_IMR_TDERR RTC_IMR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TDERR_Msk instead */
#define RTC_IMR_MASK _U_(0x3F) /**< \deprecated (RTC_IMR) Register MASK (Use RTC_IMR_Msk instead) */
#define RTC_IMR_Msk _U_(0x3F) /**< (RTC_IMR) Register Mask */
/* -------- RTC_VER : (RTC Offset: 0x2c) (R/ 32) Valid Entry Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVTIM:1; /**< bit: 0 Non-valid Time */
uint32_t NVCAL:1; /**< bit: 1 Non-valid Calendar */
uint32_t NVTIMALR:1; /**< bit: 2 Non-valid Time Alarm */
uint32_t NVCALALR:1; /**< bit: 3 Non-valid Calendar Alarm */
uint32_t :28; /**< bit: 4..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_VER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_VER_OFFSET (0x2C) /**< (RTC_VER) Valid Entry Register Offset */
#define RTC_VER_NVTIM_Pos 0 /**< (RTC_VER) Non-valid Time Position */
#define RTC_VER_NVTIM_Msk (_U_(0x1) << RTC_VER_NVTIM_Pos) /**< (RTC_VER) Non-valid Time Mask */
#define RTC_VER_NVTIM RTC_VER_NVTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIM_Msk instead */
#define RTC_VER_NVCAL_Pos 1 /**< (RTC_VER) Non-valid Calendar Position */
#define RTC_VER_NVCAL_Msk (_U_(0x1) << RTC_VER_NVCAL_Pos) /**< (RTC_VER) Non-valid Calendar Mask */
#define RTC_VER_NVCAL RTC_VER_NVCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCAL_Msk instead */
#define RTC_VER_NVTIMALR_Pos 2 /**< (RTC_VER) Non-valid Time Alarm Position */
#define RTC_VER_NVTIMALR_Msk (_U_(0x1) << RTC_VER_NVTIMALR_Pos) /**< (RTC_VER) Non-valid Time Alarm Mask */
#define RTC_VER_NVTIMALR RTC_VER_NVTIMALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIMALR_Msk instead */
#define RTC_VER_NVCALALR_Pos 3 /**< (RTC_VER) Non-valid Calendar Alarm Position */
#define RTC_VER_NVCALALR_Msk (_U_(0x1) << RTC_VER_NVCALALR_Pos) /**< (RTC_VER) Non-valid Calendar Alarm Mask */
#define RTC_VER_NVCALALR RTC_VER_NVCALALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCALALR_Msk instead */
#define RTC_VER_MASK _U_(0x0F) /**< \deprecated (RTC_VER) Register MASK (Use RTC_VER_Msk instead) */
#define RTC_VER_Msk _U_(0x0F) /**< (RTC_VER) Register Mask */
/* -------- RTC_WPMR : (RTC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTC_WPMR_OFFSET (0xE4) /**< (RTC_WPMR) Write Protection Mode Register Offset */
#define RTC_WPMR_WPEN_Pos 0 /**< (RTC_WPMR) Write Protection Enable Position */
#define RTC_WPMR_WPEN_Msk (_U_(0x1) << RTC_WPMR_WPEN_Pos) /**< (RTC_WPMR) Write Protection Enable Mask */
#define RTC_WPMR_WPEN RTC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_WPMR_WPEN_Msk instead */
#define RTC_WPMR_WPKEY_Pos 8 /**< (RTC_WPMR) Write Protection Key Position */
#define RTC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << RTC_WPMR_WPKEY_Pos) /**< (RTC_WPMR) Write Protection Key Mask */
#define RTC_WPMR_WPKEY(value) (RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))
#define RTC_WPMR_WPKEY_PASSWD_Val _U_(0x525443) /**< (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define RTC_WPMR_WPKEY_PASSWD (RTC_WPMR_WPKEY_PASSWD_Val << RTC_WPMR_WPKEY_Pos) /**< (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define RTC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (RTC_WPMR) Register MASK (Use RTC_WPMR_Msk instead) */
#define RTC_WPMR_Msk _U_(0xFFFFFF01) /**< (RTC_WPMR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief RTC hardware registers */
typedef struct {
__IO uint32_t RTC_CR; /**< (RTC Offset: 0x00) Control Register */
__IO uint32_t RTC_MR; /**< (RTC Offset: 0x04) Mode Register */
__IO uint32_t RTC_TIMR; /**< (RTC Offset: 0x08) Time Register */
__IO uint32_t RTC_CALR; /**< (RTC Offset: 0x0C) Calendar Register */
__IO uint32_t RTC_TIMALR; /**< (RTC Offset: 0x10) Time Alarm Register */
__IO uint32_t RTC_CALALR; /**< (RTC Offset: 0x14) Calendar Alarm Register */
__I uint32_t RTC_SR; /**< (RTC Offset: 0x18) Status Register */
__O uint32_t RTC_SCCR; /**< (RTC Offset: 0x1C) Status Clear Command Register */
__O uint32_t RTC_IER; /**< (RTC Offset: 0x20) Interrupt Enable Register */
__O uint32_t RTC_IDR; /**< (RTC Offset: 0x24) Interrupt Disable Register */
__I uint32_t RTC_IMR; /**< (RTC Offset: 0x28) Interrupt Mask Register */
__I uint32_t RTC_VER; /**< (RTC Offset: 0x2C) Valid Entry Register */
RoReg8 Reserved1[0xB4];
__IO uint32_t RTC_WPMR; /**< (RTC Offset: 0xE4) Write Protection Mode Register */
} Rtc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief RTC hardware registers */
typedef struct {
__IO RTC_CR_Type RTC_CR; /**< Offset: 0x00 (R/W 32) Control Register */
__IO RTC_MR_Type RTC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__IO RTC_TIMR_Type RTC_TIMR; /**< Offset: 0x08 (R/W 32) Time Register */
__IO RTC_CALR_Type RTC_CALR; /**< Offset: 0x0C (R/W 32) Calendar Register */
__IO RTC_TIMALR_Type RTC_TIMALR; /**< Offset: 0x10 (R/W 32) Time Alarm Register */
__IO RTC_CALALR_Type RTC_CALALR; /**< Offset: 0x14 (R/W 32) Calendar Alarm Register */
__I RTC_SR_Type RTC_SR; /**< Offset: 0x18 (R/ 32) Status Register */
__O RTC_SCCR_Type RTC_SCCR; /**< Offset: 0x1C ( /W 32) Status Clear Command Register */
__O RTC_IER_Type RTC_IER; /**< Offset: 0x20 ( /W 32) Interrupt Enable Register */
__O RTC_IDR_Type RTC_IDR; /**< Offset: 0x24 ( /W 32) Interrupt Disable Register */
__I RTC_IMR_Type RTC_IMR; /**< Offset: 0x28 (R/ 32) Interrupt Mask Register */
__I RTC_VER_Type RTC_VER; /**< Offset: 0x2C (R/ 32) Valid Entry Register */
__I uint32_t Reserved1[45];
__IO RTC_WPMR_Type RTC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
} Rtc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Real-time Clock */
#endif /* _SAME70_RTC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for RTT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RTT_COMPONENT_H_
#define _SAME70_RTT_COMPONENT_H_
#define _SAME70_RTT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Real-time Timer
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RTT */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define RTT_6081 /**< (RTT) Module ID */
#define REV_RTT M /**< (RTT) Module revision */
/* -------- RTT_MR : (RTT Offset: 0x00) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RTPRES:16; /**< bit: 0..15 Real-time Timer Prescaler Value */
uint32_t ALMIEN:1; /**< bit: 16 Alarm Interrupt Enable */
uint32_t RTTINCIEN:1; /**< bit: 17 Real-time Timer Increment Interrupt Enable */
uint32_t RTTRST:1; /**< bit: 18 Real-time Timer Restart */
uint32_t :1; /**< bit: 19 Reserved */
uint32_t RTTDIS:1; /**< bit: 20 Real-time Timer Disable */
uint32_t :3; /**< bit: 21..23 Reserved */
uint32_t RTC1HZ:1; /**< bit: 24 Real-Time Clock 1Hz Clock Selection */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTT_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTT_MR_OFFSET (0x00) /**< (RTT_MR) Mode Register Offset */
#define RTT_MR_RTPRES_Pos 0 /**< (RTT_MR) Real-time Timer Prescaler Value Position */
#define RTT_MR_RTPRES_Msk (_U_(0xFFFF) << RTT_MR_RTPRES_Pos) /**< (RTT_MR) Real-time Timer Prescaler Value Mask */
#define RTT_MR_RTPRES(value) (RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))
#define RTT_MR_ALMIEN_Pos 16 /**< (RTT_MR) Alarm Interrupt Enable Position */
#define RTT_MR_ALMIEN_Msk (_U_(0x1) << RTT_MR_ALMIEN_Pos) /**< (RTT_MR) Alarm Interrupt Enable Mask */
#define RTT_MR_ALMIEN RTT_MR_ALMIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_ALMIEN_Msk instead */
#define RTT_MR_RTTINCIEN_Pos 17 /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Position */
#define RTT_MR_RTTINCIEN_Msk (_U_(0x1) << RTT_MR_RTTINCIEN_Pos) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Mask */
#define RTT_MR_RTTINCIEN RTT_MR_RTTINCIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTINCIEN_Msk instead */
#define RTT_MR_RTTRST_Pos 18 /**< (RTT_MR) Real-time Timer Restart Position */
#define RTT_MR_RTTRST_Msk (_U_(0x1) << RTT_MR_RTTRST_Pos) /**< (RTT_MR) Real-time Timer Restart Mask */
#define RTT_MR_RTTRST RTT_MR_RTTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTRST_Msk instead */
#define RTT_MR_RTTDIS_Pos 20 /**< (RTT_MR) Real-time Timer Disable Position */
#define RTT_MR_RTTDIS_Msk (_U_(0x1) << RTT_MR_RTTDIS_Pos) /**< (RTT_MR) Real-time Timer Disable Mask */
#define RTT_MR_RTTDIS RTT_MR_RTTDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTDIS_Msk instead */
#define RTT_MR_RTC1HZ_Pos 24 /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Position */
#define RTT_MR_RTC1HZ_Msk (_U_(0x1) << RTT_MR_RTC1HZ_Pos) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Mask */
#define RTT_MR_RTC1HZ RTT_MR_RTC1HZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTC1HZ_Msk instead */
#define RTT_MR_MASK _U_(0x117FFFF) /**< \deprecated (RTT_MR) Register MASK (Use RTT_MR_Msk instead) */
#define RTT_MR_Msk _U_(0x117FFFF) /**< (RTT_MR) Register Mask */
/* -------- RTT_AR : (RTT Offset: 0x04) (R/W 32) Alarm Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ALMV:32; /**< bit: 0..31 Alarm Value */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTT_AR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTT_AR_OFFSET (0x04) /**< (RTT_AR) Alarm Register Offset */
#define RTT_AR_ALMV_Pos 0 /**< (RTT_AR) Alarm Value Position */
#define RTT_AR_ALMV_Msk (_U_(0xFFFFFFFF) << RTT_AR_ALMV_Pos) /**< (RTT_AR) Alarm Value Mask */
#define RTT_AR_ALMV(value) (RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))
#define RTT_AR_MASK _U_(0xFFFFFFFF) /**< \deprecated (RTT_AR) Register MASK (Use RTT_AR_Msk instead) */
#define RTT_AR_Msk _U_(0xFFFFFFFF) /**< (RTT_AR) Register Mask */
/* -------- RTT_VR : (RTT Offset: 0x08) (R/ 32) Value Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRTV:32; /**< bit: 0..31 Current Real-time Value */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTT_VR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTT_VR_OFFSET (0x08) /**< (RTT_VR) Value Register Offset */
#define RTT_VR_CRTV_Pos 0 /**< (RTT_VR) Current Real-time Value Position */
#define RTT_VR_CRTV_Msk (_U_(0xFFFFFFFF) << RTT_VR_CRTV_Pos) /**< (RTT_VR) Current Real-time Value Mask */
#define RTT_VR_CRTV(value) (RTT_VR_CRTV_Msk & ((value) << RTT_VR_CRTV_Pos))
#define RTT_VR_MASK _U_(0xFFFFFFFF) /**< \deprecated (RTT_VR) Register MASK (Use RTT_VR_Msk instead) */
#define RTT_VR_Msk _U_(0xFFFFFFFF) /**< (RTT_VR) Register Mask */
/* -------- RTT_SR : (RTT Offset: 0x0c) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ALMS:1; /**< bit: 0 Real-time Alarm Status (cleared on read) */
uint32_t RTTINC:1; /**< bit: 1 Prescaler Roll-over Status (cleared on read) */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} RTT_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RTT_SR_OFFSET (0x0C) /**< (RTT_SR) Status Register Offset */
#define RTT_SR_ALMS_Pos 0 /**< (RTT_SR) Real-time Alarm Status (cleared on read) Position */
#define RTT_SR_ALMS_Msk (_U_(0x1) << RTT_SR_ALMS_Pos) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Mask */
#define RTT_SR_ALMS RTT_SR_ALMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_SR_ALMS_Msk instead */
#define RTT_SR_RTTINC_Pos 1 /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Position */
#define RTT_SR_RTTINC_Msk (_U_(0x1) << RTT_SR_RTTINC_Pos) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Mask */
#define RTT_SR_RTTINC RTT_SR_RTTINC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_SR_RTTINC_Msk instead */
#define RTT_SR_MASK _U_(0x03) /**< \deprecated (RTT_SR) Register MASK (Use RTT_SR_Msk instead) */
#define RTT_SR_Msk _U_(0x03) /**< (RTT_SR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief RTT hardware registers */
typedef struct {
__IO uint32_t RTT_MR; /**< (RTT Offset: 0x00) Mode Register */
__IO uint32_t RTT_AR; /**< (RTT Offset: 0x04) Alarm Register */
__I uint32_t RTT_VR; /**< (RTT Offset: 0x08) Value Register */
__I uint32_t RTT_SR; /**< (RTT Offset: 0x0C) Status Register */
} Rtt;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief RTT hardware registers */
typedef struct {
__IO RTT_MR_Type RTT_MR; /**< Offset: 0x00 (R/W 32) Mode Register */
__IO RTT_AR_Type RTT_AR; /**< Offset: 0x04 (R/W 32) Alarm Register */
__I RTT_VR_Type RTT_VR; /**< Offset: 0x08 (R/ 32) Value Register */
__I RTT_SR_Type RTT_SR; /**< Offset: 0x0C (R/ 32) Status Register */
} Rtt;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Real-time Timer */
#endif /* _SAME70_RTT_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for SDRAMC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SDRAMC_COMPONENT_H_
#define _SAME70_SDRAMC_COMPONENT_H_
#define _SAME70_SDRAMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 SDRAM Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SDRAMC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define SDRAMC_6100 /**< (SDRAMC) Module ID */
#define REV_SDRAMC U /**< (SDRAMC) Module revision */
/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) (R/W 32) SDRAMC Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MODE:3; /**< bit: 0..2 SDRAMC Command Mode */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_MR_OFFSET (0x00) /**< (SDRAMC_MR) SDRAMC Mode Register Offset */
#define SDRAMC_MR_MODE_Pos 0 /**< (SDRAMC_MR) SDRAMC Command Mode Position */
#define SDRAMC_MR_MODE_Msk (_U_(0x7) << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) SDRAMC Command Mode Mask */
#define SDRAMC_MR_MODE(value) (SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))
#define SDRAMC_MR_MODE_NORMAL_Val _U_(0x0) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
#define SDRAMC_MR_MODE_NOP_Val _U_(0x1) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val _U_(0x2) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
#define SDRAMC_MR_MODE_LOAD_MODEREG_Val _U_(0x3) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
#define SDRAMC_MR_MODE_AUTO_REFRESH_Val _U_(0x4) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val _U_(0x5) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
#define SDRAMC_MR_MODE_DEEP_POWERDOWN_Val _U_(0x6) /**< (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
#define SDRAMC_MR_MODE_NORMAL (SDRAMC_MR_MODE_NORMAL_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. Position */
#define SDRAMC_MR_MODE_NOP (SDRAMC_MR_MODE_NOP_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */
#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */
#define SDRAMC_MR_MODE_LOAD_MODEREG (SDRAMC_MR_MODE_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */
#define SDRAMC_MR_MODE_AUTO_REFRESH (SDRAMC_MR_MODE_AUTO_REFRESH_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. Position */
#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. Position */
#define SDRAMC_MR_MODE_DEEP_POWERDOWN (SDRAMC_MR_MODE_DEEP_POWERDOWN_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. Position */
#define SDRAMC_MR_MASK _U_(0x07) /**< \deprecated (SDRAMC_MR) Register MASK (Use SDRAMC_MR_Msk instead) */
#define SDRAMC_MR_Msk _U_(0x07) /**< (SDRAMC_MR) Register Mask */
/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) (R/W 32) SDRAMC Refresh Timer Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:12; /**< bit: 0..11 SDRAMC Refresh Timer Count */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_TR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_TR_OFFSET (0x04) /**< (SDRAMC_TR) SDRAMC Refresh Timer Register Offset */
#define SDRAMC_TR_COUNT_Pos 0 /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Position */
#define SDRAMC_TR_COUNT_Msk (_U_(0xFFF) << SDRAMC_TR_COUNT_Pos) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Mask */
#define SDRAMC_TR_COUNT(value) (SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))
#define SDRAMC_TR_MASK _U_(0xFFF) /**< \deprecated (SDRAMC_TR) Register MASK (Use SDRAMC_TR_Msk instead) */
#define SDRAMC_TR_Msk _U_(0xFFF) /**< (SDRAMC_TR) Register Mask */
/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) (R/W 32) SDRAMC Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NC:2; /**< bit: 0..1 Number of Column Bits */
uint32_t NR:2; /**< bit: 2..3 Number of Row Bits */
uint32_t NB:1; /**< bit: 4 Number of Banks */
uint32_t CAS:2; /**< bit: 5..6 CAS Latency */
uint32_t DBW:1; /**< bit: 7 Data Bus Width */
uint32_t TWR:4; /**< bit: 8..11 Write Recovery Delay */
uint32_t TRC_TRFC:4; /**< bit: 12..15 Row Cycle Delay and Row Refresh Cycle */
uint32_t TRP:4; /**< bit: 16..19 Row Precharge Delay */
uint32_t TRCD:4; /**< bit: 20..23 Row to Column Delay */
uint32_t TRAS:4; /**< bit: 24..27 Active to Precharge Delay */
uint32_t TXSR:4; /**< bit: 28..31 Exit Self Refresh to Active Delay */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_CR_OFFSET (0x08) /**< (SDRAMC_CR) SDRAMC Configuration Register Offset */
#define SDRAMC_CR_NC_Pos 0 /**< (SDRAMC_CR) Number of Column Bits Position */
#define SDRAMC_CR_NC_Msk (_U_(0x3) << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) Number of Column Bits Mask */
#define SDRAMC_CR_NC(value) (SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))
#define SDRAMC_CR_NC_COL8_Val _U_(0x0) /**< (SDRAMC_CR) 8 column bits */
#define SDRAMC_CR_NC_COL9_Val _U_(0x1) /**< (SDRAMC_CR) 9 column bits */
#define SDRAMC_CR_NC_COL10_Val _U_(0x2) /**< (SDRAMC_CR) 10 column bits */
#define SDRAMC_CR_NC_COL11_Val _U_(0x3) /**< (SDRAMC_CR) 11 column bits */
#define SDRAMC_CR_NC_COL8 (SDRAMC_CR_NC_COL8_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 8 column bits Position */
#define SDRAMC_CR_NC_COL9 (SDRAMC_CR_NC_COL9_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 9 column bits Position */
#define SDRAMC_CR_NC_COL10 (SDRAMC_CR_NC_COL10_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 10 column bits Position */
#define SDRAMC_CR_NC_COL11 (SDRAMC_CR_NC_COL11_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 11 column bits Position */
#define SDRAMC_CR_NR_Pos 2 /**< (SDRAMC_CR) Number of Row Bits Position */
#define SDRAMC_CR_NR_Msk (_U_(0x3) << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) Number of Row Bits Mask */
#define SDRAMC_CR_NR(value) (SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))
#define SDRAMC_CR_NR_ROW11_Val _U_(0x0) /**< (SDRAMC_CR) 11 row bits */
#define SDRAMC_CR_NR_ROW12_Val _U_(0x1) /**< (SDRAMC_CR) 12 row bits */
#define SDRAMC_CR_NR_ROW13_Val _U_(0x2) /**< (SDRAMC_CR) 13 row bits */
#define SDRAMC_CR_NR_ROW11 (SDRAMC_CR_NR_ROW11_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 11 row bits Position */
#define SDRAMC_CR_NR_ROW12 (SDRAMC_CR_NR_ROW12_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 12 row bits Position */
#define SDRAMC_CR_NR_ROW13 (SDRAMC_CR_NR_ROW13_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 13 row bits Position */
#define SDRAMC_CR_NB_Pos 4 /**< (SDRAMC_CR) Number of Banks Position */
#define SDRAMC_CR_NB_Msk (_U_(0x1) << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) Number of Banks Mask */
#define SDRAMC_CR_NB SDRAMC_CR_NB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CR_NB_Msk instead */
#define SDRAMC_CR_NB_BANK2_Val _U_(0x0) /**< (SDRAMC_CR) 2 banks */
#define SDRAMC_CR_NB_BANK4_Val _U_(0x1) /**< (SDRAMC_CR) 4 banks */
#define SDRAMC_CR_NB_BANK2 (SDRAMC_CR_NB_BANK2_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 2 banks Position */
#define SDRAMC_CR_NB_BANK4 (SDRAMC_CR_NB_BANK4_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 4 banks Position */
#define SDRAMC_CR_CAS_Pos 5 /**< (SDRAMC_CR) CAS Latency Position */
#define SDRAMC_CR_CAS_Msk (_U_(0x3) << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) CAS Latency Mask */
#define SDRAMC_CR_CAS(value) (SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))
#define SDRAMC_CR_CAS_LATENCY1_Val _U_(0x1) /**< (SDRAMC_CR) 1 cycle CAS latency */
#define SDRAMC_CR_CAS_LATENCY2_Val _U_(0x2) /**< (SDRAMC_CR) 2 cycle CAS latency */
#define SDRAMC_CR_CAS_LATENCY3_Val _U_(0x3) /**< (SDRAMC_CR) 3 cycle CAS latency */
#define SDRAMC_CR_CAS_LATENCY1 (SDRAMC_CR_CAS_LATENCY1_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 1 cycle CAS latency Position */
#define SDRAMC_CR_CAS_LATENCY2 (SDRAMC_CR_CAS_LATENCY2_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 2 cycle CAS latency Position */
#define SDRAMC_CR_CAS_LATENCY3 (SDRAMC_CR_CAS_LATENCY3_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 3 cycle CAS latency Position */
#define SDRAMC_CR_DBW_Pos 7 /**< (SDRAMC_CR) Data Bus Width Position */
#define SDRAMC_CR_DBW_Msk (_U_(0x1) << SDRAMC_CR_DBW_Pos) /**< (SDRAMC_CR) Data Bus Width Mask */
#define SDRAMC_CR_DBW SDRAMC_CR_DBW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CR_DBW_Msk instead */
#define SDRAMC_CR_TWR_Pos 8 /**< (SDRAMC_CR) Write Recovery Delay Position */
#define SDRAMC_CR_TWR_Msk (_U_(0xF) << SDRAMC_CR_TWR_Pos) /**< (SDRAMC_CR) Write Recovery Delay Mask */
#define SDRAMC_CR_TWR(value) (SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))
#define SDRAMC_CR_TRC_TRFC_Pos 12 /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Position */
#define SDRAMC_CR_TRC_TRFC_Msk (_U_(0xF) << SDRAMC_CR_TRC_TRFC_Pos) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Mask */
#define SDRAMC_CR_TRC_TRFC(value) (SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))
#define SDRAMC_CR_TRP_Pos 16 /**< (SDRAMC_CR) Row Precharge Delay Position */
#define SDRAMC_CR_TRP_Msk (_U_(0xF) << SDRAMC_CR_TRP_Pos) /**< (SDRAMC_CR) Row Precharge Delay Mask */
#define SDRAMC_CR_TRP(value) (SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))
#define SDRAMC_CR_TRCD_Pos 20 /**< (SDRAMC_CR) Row to Column Delay Position */
#define SDRAMC_CR_TRCD_Msk (_U_(0xF) << SDRAMC_CR_TRCD_Pos) /**< (SDRAMC_CR) Row to Column Delay Mask */
#define SDRAMC_CR_TRCD(value) (SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))
#define SDRAMC_CR_TRAS_Pos 24 /**< (SDRAMC_CR) Active to Precharge Delay Position */
#define SDRAMC_CR_TRAS_Msk (_U_(0xF) << SDRAMC_CR_TRAS_Pos) /**< (SDRAMC_CR) Active to Precharge Delay Mask */
#define SDRAMC_CR_TRAS(value) (SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))
#define SDRAMC_CR_TXSR_Pos 28 /**< (SDRAMC_CR) Exit Self Refresh to Active Delay Position */
#define SDRAMC_CR_TXSR_Msk (_U_(0xF) << SDRAMC_CR_TXSR_Pos) /**< (SDRAMC_CR) Exit Self Refresh to Active Delay Mask */
#define SDRAMC_CR_TXSR(value) (SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))
#define SDRAMC_CR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_CR) Register MASK (Use SDRAMC_CR_Msk instead) */
#define SDRAMC_CR_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_CR) Register Mask */
/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) (R/W 32) SDRAMC Low Power Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LPCB:2; /**< bit: 0..1 Low-power Configuration Bits */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t PASR:3; /**< bit: 4..6 Partial Array Self-refresh (only for low-power SDRAM) */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t TCSR:2; /**< bit: 8..9 Temperature Compensated Self-Refresh (only for low-power SDRAM) */
uint32_t DS:2; /**< bit: 10..11 Drive Strength (only for low-power SDRAM) */
uint32_t TIMEOUT:2; /**< bit: 12..13 Time to Define When Low-power Mode Is Enabled */
uint32_t :18; /**< bit: 14..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_LPR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_LPR_OFFSET (0x10) /**< (SDRAMC_LPR) SDRAMC Low Power Register Offset */
#define SDRAMC_LPR_LPCB_Pos 0 /**< (SDRAMC_LPR) Low-power Configuration Bits Position */
#define SDRAMC_LPR_LPCB_Msk (_U_(0x3) << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low-power Configuration Bits Mask */
#define SDRAMC_LPR_LPCB(value) (SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))
#define SDRAMC_LPR_LPCB_DISABLED_Val _U_(0x0) /**< (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
#define SDRAMC_LPR_LPCB_SELF_REFRESH_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
#define SDRAMC_LPR_LPCB_POWER_DOWN_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val _U_(0x3) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
#define SDRAMC_LPR_LPCB_DISABLED (SDRAMC_LPR_LPCB_DISABLED_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. Position */
#define SDRAMC_LPR_LPCB_SELF_REFRESH (SDRAMC_LPR_LPCB_SELF_REFRESH_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. Position */
#define SDRAMC_LPR_LPCB_POWER_DOWN (SDRAMC_LPR_LPCB_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. Position */
#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. Position */
#define SDRAMC_LPR_PASR_Pos 4 /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Position */
#define SDRAMC_LPR_PASR_Msk (_U_(0x7) << SDRAMC_LPR_PASR_Pos) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Mask */
#define SDRAMC_LPR_PASR(value) (SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))
#define SDRAMC_LPR_TCSR_Pos 8 /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Position */
#define SDRAMC_LPR_TCSR_Msk (_U_(0x3) << SDRAMC_LPR_TCSR_Pos) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Mask */
#define SDRAMC_LPR_TCSR(value) (SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))
#define SDRAMC_LPR_DS_Pos 10 /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Position */
#define SDRAMC_LPR_DS_Msk (_U_(0x3) << SDRAMC_LPR_DS_Pos) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Mask */
#define SDRAMC_LPR_DS(value) (SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))
#define SDRAMC_LPR_TIMEOUT_Pos 12 /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Position */
#define SDRAMC_LPR_TIMEOUT_Msk (_U_(0x3) << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Mask */
#define SDRAMC_LPR_TIMEOUT(value) (SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val _U_(0x0) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. Position */
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. Position */
#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. Position */
#define SDRAMC_LPR_MASK _U_(0x3F73) /**< \deprecated (SDRAMC_LPR) Register MASK (Use SDRAMC_LPR_Msk instead) */
#define SDRAMC_LPR_Msk _U_(0x3F73) /**< (SDRAMC_LPR) Register Mask */
/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) (/W 32) SDRAMC Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RES:1; /**< bit: 0 Refresh Error Status */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_IER_OFFSET (0x14) /**< (SDRAMC_IER) SDRAMC Interrupt Enable Register Offset */
#define SDRAMC_IER_RES_Pos 0 /**< (SDRAMC_IER) Refresh Error Status Position */
#define SDRAMC_IER_RES_Msk (_U_(0x1) << SDRAMC_IER_RES_Pos) /**< (SDRAMC_IER) Refresh Error Status Mask */
#define SDRAMC_IER_RES SDRAMC_IER_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IER_RES_Msk instead */
#define SDRAMC_IER_MASK _U_(0x01) /**< \deprecated (SDRAMC_IER) Register MASK (Use SDRAMC_IER_Msk instead) */
#define SDRAMC_IER_Msk _U_(0x01) /**< (SDRAMC_IER) Register Mask */
/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) (/W 32) SDRAMC Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RES:1; /**< bit: 0 Refresh Error Status */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_IDR_OFFSET (0x18) /**< (SDRAMC_IDR) SDRAMC Interrupt Disable Register Offset */
#define SDRAMC_IDR_RES_Pos 0 /**< (SDRAMC_IDR) Refresh Error Status Position */
#define SDRAMC_IDR_RES_Msk (_U_(0x1) << SDRAMC_IDR_RES_Pos) /**< (SDRAMC_IDR) Refresh Error Status Mask */
#define SDRAMC_IDR_RES SDRAMC_IDR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IDR_RES_Msk instead */
#define SDRAMC_IDR_MASK _U_(0x01) /**< \deprecated (SDRAMC_IDR) Register MASK (Use SDRAMC_IDR_Msk instead) */
#define SDRAMC_IDR_Msk _U_(0x01) /**< (SDRAMC_IDR) Register Mask */
/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) (R/ 32) SDRAMC Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RES:1; /**< bit: 0 Refresh Error Status */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_IMR_OFFSET (0x1C) /**< (SDRAMC_IMR) SDRAMC Interrupt Mask Register Offset */
#define SDRAMC_IMR_RES_Pos 0 /**< (SDRAMC_IMR) Refresh Error Status Position */
#define SDRAMC_IMR_RES_Msk (_U_(0x1) << SDRAMC_IMR_RES_Pos) /**< (SDRAMC_IMR) Refresh Error Status Mask */
#define SDRAMC_IMR_RES SDRAMC_IMR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IMR_RES_Msk instead */
#define SDRAMC_IMR_MASK _U_(0x01) /**< \deprecated (SDRAMC_IMR) Register MASK (Use SDRAMC_IMR_Msk instead) */
#define SDRAMC_IMR_Msk _U_(0x01) /**< (SDRAMC_IMR) Register Mask */
/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) (R/ 32) SDRAMC Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RES:1; /**< bit: 0 Refresh Error Status (cleared on read) */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_ISR_OFFSET (0x20) /**< (SDRAMC_ISR) SDRAMC Interrupt Status Register Offset */
#define SDRAMC_ISR_RES_Pos 0 /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Position */
#define SDRAMC_ISR_RES_Msk (_U_(0x1) << SDRAMC_ISR_RES_Pos) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Mask */
#define SDRAMC_ISR_RES SDRAMC_ISR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_ISR_RES_Msk instead */
#define SDRAMC_ISR_MASK _U_(0x01) /**< \deprecated (SDRAMC_ISR) Register MASK (Use SDRAMC_ISR_Msk instead) */
#define SDRAMC_ISR_Msk _U_(0x01) /**< (SDRAMC_ISR) Register Mask */
/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) (R/W 32) SDRAMC Memory Device Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MD:2; /**< bit: 0..1 Memory Device Type */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_MDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_MDR_OFFSET (0x24) /**< (SDRAMC_MDR) SDRAMC Memory Device Register Offset */
#define SDRAMC_MDR_MD_Pos 0 /**< (SDRAMC_MDR) Memory Device Type Position */
#define SDRAMC_MDR_MD_Msk (_U_(0x3) << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Memory Device Type Mask */
#define SDRAMC_MDR_MD(value) (SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))
#define SDRAMC_MDR_MD_SDRAM_Val _U_(0x0) /**< (SDRAMC_MDR) SDRAM */
#define SDRAMC_MDR_MD_LPSDRAM_Val _U_(0x1) /**< (SDRAMC_MDR) Low-power SDRAM */
#define SDRAMC_MDR_MD_SDRAM (SDRAMC_MDR_MD_SDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) SDRAM Position */
#define SDRAMC_MDR_MD_LPSDRAM (SDRAMC_MDR_MD_LPSDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Low-power SDRAM Position */
#define SDRAMC_MDR_MASK _U_(0x03) /**< \deprecated (SDRAMC_MDR) Register MASK (Use SDRAMC_MDR_Msk instead) */
#define SDRAMC_MDR_Msk _U_(0x03) /**< (SDRAMC_MDR) Register Mask */
/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) (R/W 32) SDRAMC Configuration Register 1 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TMRD:4; /**< bit: 0..3 Load Mode Register Command to Active or Refresh Command */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t UNAL:1; /**< bit: 8 Support Unaligned Access */
uint32_t :23; /**< bit: 9..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_CFR1_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_CFR1_OFFSET (0x28) /**< (SDRAMC_CFR1) SDRAMC Configuration Register 1 Offset */
#define SDRAMC_CFR1_TMRD_Pos 0 /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Position */
#define SDRAMC_CFR1_TMRD_Msk (_U_(0xF) << SDRAMC_CFR1_TMRD_Pos) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Mask */
#define SDRAMC_CFR1_TMRD(value) (SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))
#define SDRAMC_CFR1_UNAL_Pos 8 /**< (SDRAMC_CFR1) Support Unaligned Access Position */
#define SDRAMC_CFR1_UNAL_Msk (_U_(0x1) << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Support Unaligned Access Mask */
#define SDRAMC_CFR1_UNAL SDRAMC_CFR1_UNAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CFR1_UNAL_Msk instead */
#define SDRAMC_CFR1_UNAL_UNSUPPORTED_Val _U_(0x0) /**< (SDRAMC_CFR1) Unaligned access is not supported. */
#define SDRAMC_CFR1_UNAL_SUPPORTED_Val _U_(0x1) /**< (SDRAMC_CFR1) Unaligned access is supported. */
#define SDRAMC_CFR1_UNAL_UNSUPPORTED (SDRAMC_CFR1_UNAL_UNSUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is not supported. Position */
#define SDRAMC_CFR1_UNAL_SUPPORTED (SDRAMC_CFR1_UNAL_SUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is supported. Position */
#define SDRAMC_CFR1_MASK _U_(0x10F) /**< \deprecated (SDRAMC_CFR1) Register MASK (Use SDRAMC_CFR1_Msk instead) */
#define SDRAMC_CFR1_Msk _U_(0x10F) /**< (SDRAMC_CFR1) Register Mask */
/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2c) (R/W 32) SDRAMC OCMS Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SDR_SE:1; /**< bit: 0 SDRAM Memory Controller Scrambling Enable */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_OCMS_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_OCMS_OFFSET (0x2C) /**< (SDRAMC_OCMS) SDRAMC OCMS Register Offset */
#define SDRAMC_OCMS_SDR_SE_Pos 0 /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Position */
#define SDRAMC_OCMS_SDR_SE_Msk (_U_(0x1) << SDRAMC_OCMS_SDR_SE_Pos) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Mask */
#define SDRAMC_OCMS_SDR_SE SDRAMC_OCMS_SDR_SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_OCMS_SDR_SE_Msk instead */
#define SDRAMC_OCMS_MASK _U_(0x01) /**< \deprecated (SDRAMC_OCMS) Register MASK (Use SDRAMC_OCMS_Msk instead) */
#define SDRAMC_OCMS_Msk _U_(0x01) /**< (SDRAMC_OCMS) Register Mask */
/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) (/W 32) SDRAMC OCMS KEY1 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEY1:32; /**< bit: 0..31 Off-chip Memory Scrambling (OCMS) Key Part 1 */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_OCMS_KEY1_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_OCMS_KEY1_OFFSET (0x30) /**< (SDRAMC_OCMS_KEY1) SDRAMC OCMS KEY1 Register Offset */
#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Position */
#define SDRAMC_OCMS_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Mask */
#define SDRAMC_OCMS_KEY1_KEY1(value) (SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))
#define SDRAMC_OCMS_KEY1_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_OCMS_KEY1) Register MASK (Use SDRAMC_OCMS_KEY1_Msk instead) */
#define SDRAMC_OCMS_KEY1_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY1) Register Mask */
/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) (/W 32) SDRAMC OCMS KEY2 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEY2:32; /**< bit: 0..31 Off-chip Memory Scrambling (OCMS) Key Part 2 */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SDRAMC_OCMS_KEY2_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDRAMC_OCMS_KEY2_OFFSET (0x34) /**< (SDRAMC_OCMS_KEY2) SDRAMC OCMS KEY2 Register Offset */
#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Position */
#define SDRAMC_OCMS_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Mask */
#define SDRAMC_OCMS_KEY2_KEY2(value) (SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))
#define SDRAMC_OCMS_KEY2_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_OCMS_KEY2) Register MASK (Use SDRAMC_OCMS_KEY2_Msk instead) */
#define SDRAMC_OCMS_KEY2_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY2) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief SDRAMC hardware registers */
typedef struct {
__IO uint32_t SDRAMC_MR; /**< (SDRAMC Offset: 0x00) SDRAMC Mode Register */
__IO uint32_t SDRAMC_TR; /**< (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register */
__IO uint32_t SDRAMC_CR; /**< (SDRAMC Offset: 0x08) SDRAMC Configuration Register */
RoReg8 Reserved1[0x4];
__IO uint32_t SDRAMC_LPR; /**< (SDRAMC Offset: 0x10) SDRAMC Low Power Register */
__O uint32_t SDRAMC_IER; /**< (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register */
__O uint32_t SDRAMC_IDR; /**< (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register */
__I uint32_t SDRAMC_IMR; /**< (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register */
__I uint32_t SDRAMC_ISR; /**< (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register */
__IO uint32_t SDRAMC_MDR; /**< (SDRAMC Offset: 0x24) SDRAMC Memory Device Register */
__IO uint32_t SDRAMC_CFR1; /**< (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 */
__IO uint32_t SDRAMC_OCMS; /**< (SDRAMC Offset: 0x2C) SDRAMC OCMS Register */
__O uint32_t SDRAMC_OCMS_KEY1; /**< (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register */
__O uint32_t SDRAMC_OCMS_KEY2; /**< (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register */
} Sdramc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief SDRAMC hardware registers */
typedef struct {
__IO SDRAMC_MR_Type SDRAMC_MR; /**< Offset: 0x00 (R/W 32) SDRAMC Mode Register */
__IO SDRAMC_TR_Type SDRAMC_TR; /**< Offset: 0x04 (R/W 32) SDRAMC Refresh Timer Register */
__IO SDRAMC_CR_Type SDRAMC_CR; /**< Offset: 0x08 (R/W 32) SDRAMC Configuration Register */
__I uint32_t Reserved1[1];
__IO SDRAMC_LPR_Type SDRAMC_LPR; /**< Offset: 0x10 (R/W 32) SDRAMC Low Power Register */
__O SDRAMC_IER_Type SDRAMC_IER; /**< Offset: 0x14 ( /W 32) SDRAMC Interrupt Enable Register */
__O SDRAMC_IDR_Type SDRAMC_IDR; /**< Offset: 0x18 ( /W 32) SDRAMC Interrupt Disable Register */
__I SDRAMC_IMR_Type SDRAMC_IMR; /**< Offset: 0x1C (R/ 32) SDRAMC Interrupt Mask Register */
__I SDRAMC_ISR_Type SDRAMC_ISR; /**< Offset: 0x20 (R/ 32) SDRAMC Interrupt Status Register */
__IO SDRAMC_MDR_Type SDRAMC_MDR; /**< Offset: 0x24 (R/W 32) SDRAMC Memory Device Register */
__IO SDRAMC_CFR1_Type SDRAMC_CFR1; /**< Offset: 0x28 (R/W 32) SDRAMC Configuration Register 1 */
__IO SDRAMC_OCMS_Type SDRAMC_OCMS; /**< Offset: 0x2C (R/W 32) SDRAMC OCMS Register */
__O SDRAMC_OCMS_KEY1_Type SDRAMC_OCMS_KEY1; /**< Offset: 0x30 ( /W 32) SDRAMC OCMS KEY1 Register */
__O SDRAMC_OCMS_KEY2_Type SDRAMC_OCMS_KEY2; /**< Offset: 0x34 ( /W 32) SDRAMC OCMS KEY2 Register */
} Sdramc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of SDRAM Controller */
#endif /* _SAME70_SDRAMC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for SMC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SMC_COMPONENT_H_
#define _SAME70_SMC_COMPONENT_H_
#define _SAME70_SMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Static Memory Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SMC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define SMC_6498 /**< (SMC) Module ID */
#define REV_SMC H /**< (SMC) Module revision */
/* -------- SMC_SETUP : (SMC Offset: 0x00) (R/W 32) SMC Setup Register (CS_number = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NWE_SETUP:6; /**< bit: 0..5 NWE Setup Length */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t NCS_WR_SETUP:6; /**< bit: 8..13 NCS Setup Length in WRITE Access */
uint32_t :2; /**< bit: 14..15 Reserved */
uint32_t NRD_SETUP:6; /**< bit: 16..21 NRD Setup Length */
uint32_t :2; /**< bit: 22..23 Reserved */
uint32_t NCS_RD_SETUP:6; /**< bit: 24..29 NCS Setup Length in READ Access */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_SETUP_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_SETUP_OFFSET (0x00) /**< (SMC_SETUP) SMC Setup Register (CS_number = 0) Offset */
#define SMC_SETUP_NWE_SETUP_Pos 0 /**< (SMC_SETUP) NWE Setup Length Position */
#define SMC_SETUP_NWE_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NWE_SETUP_Pos) /**< (SMC_SETUP) NWE Setup Length Mask */
#define SMC_SETUP_NWE_SETUP(value) (SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))
#define SMC_SETUP_NCS_WR_SETUP_Pos 8 /**< (SMC_SETUP) NCS Setup Length in WRITE Access Position */
#define SMC_SETUP_NCS_WR_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_WR_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Mask */
#define SMC_SETUP_NCS_WR_SETUP(value) (SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))
#define SMC_SETUP_NRD_SETUP_Pos 16 /**< (SMC_SETUP) NRD Setup Length Position */
#define SMC_SETUP_NRD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NRD_SETUP_Pos) /**< (SMC_SETUP) NRD Setup Length Mask */
#define SMC_SETUP_NRD_SETUP(value) (SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))
#define SMC_SETUP_NCS_RD_SETUP_Pos 24 /**< (SMC_SETUP) NCS Setup Length in READ Access Position */
#define SMC_SETUP_NCS_RD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_RD_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in READ Access Mask */
#define SMC_SETUP_NCS_RD_SETUP(value) (SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))
#define SMC_SETUP_MASK _U_(0x3F3F3F3F) /**< \deprecated (SMC_SETUP) Register MASK (Use SMC_SETUP_Msk instead) */
#define SMC_SETUP_Msk _U_(0x3F3F3F3F) /**< (SMC_SETUP) Register Mask */
/* -------- SMC_PULSE : (SMC Offset: 0x04) (R/W 32) SMC Pulse Register (CS_number = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NWE_PULSE:7; /**< bit: 0..6 NWE Pulse Length */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t NCS_WR_PULSE:7; /**< bit: 8..14 NCS Pulse Length in WRITE Access */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t NRD_PULSE:7; /**< bit: 16..22 NRD Pulse Length */
uint32_t :1; /**< bit: 23 Reserved */
uint32_t NCS_RD_PULSE:7; /**< bit: 24..30 NCS Pulse Length in READ Access */
uint32_t :1; /**< bit: 31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_PULSE_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_PULSE_OFFSET (0x04) /**< (SMC_PULSE) SMC Pulse Register (CS_number = 0) Offset */
#define SMC_PULSE_NWE_PULSE_Pos 0 /**< (SMC_PULSE) NWE Pulse Length Position */
#define SMC_PULSE_NWE_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NWE_PULSE_Pos) /**< (SMC_PULSE) NWE Pulse Length Mask */
#define SMC_PULSE_NWE_PULSE(value) (SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))
#define SMC_PULSE_NCS_WR_PULSE_Pos 8 /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Position */
#define SMC_PULSE_NCS_WR_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_WR_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Mask */
#define SMC_PULSE_NCS_WR_PULSE(value) (SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))
#define SMC_PULSE_NRD_PULSE_Pos 16 /**< (SMC_PULSE) NRD Pulse Length Position */
#define SMC_PULSE_NRD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NRD_PULSE_Pos) /**< (SMC_PULSE) NRD Pulse Length Mask */
#define SMC_PULSE_NRD_PULSE(value) (SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))
#define SMC_PULSE_NCS_RD_PULSE_Pos 24 /**< (SMC_PULSE) NCS Pulse Length in READ Access Position */
#define SMC_PULSE_NCS_RD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_RD_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in READ Access Mask */
#define SMC_PULSE_NCS_RD_PULSE(value) (SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))
#define SMC_PULSE_MASK _U_(0x7F7F7F7F) /**< \deprecated (SMC_PULSE) Register MASK (Use SMC_PULSE_Msk instead) */
#define SMC_PULSE_Msk _U_(0x7F7F7F7F) /**< (SMC_PULSE) Register Mask */
/* -------- SMC_CYCLE : (SMC Offset: 0x08) (R/W 32) SMC Cycle Register (CS_number = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NWE_CYCLE:9; /**< bit: 0..8 Total Write Cycle Length */
uint32_t :7; /**< bit: 9..15 Reserved */
uint32_t NRD_CYCLE:9; /**< bit: 16..24 Total Read Cycle Length */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_CYCLE_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_CYCLE_OFFSET (0x08) /**< (SMC_CYCLE) SMC Cycle Register (CS_number = 0) Offset */
#define SMC_CYCLE_NWE_CYCLE_Pos 0 /**< (SMC_CYCLE) Total Write Cycle Length Position */
#define SMC_CYCLE_NWE_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NWE_CYCLE_Pos) /**< (SMC_CYCLE) Total Write Cycle Length Mask */
#define SMC_CYCLE_NWE_CYCLE(value) (SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))
#define SMC_CYCLE_NRD_CYCLE_Pos 16 /**< (SMC_CYCLE) Total Read Cycle Length Position */
#define SMC_CYCLE_NRD_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NRD_CYCLE_Pos) /**< (SMC_CYCLE) Total Read Cycle Length Mask */
#define SMC_CYCLE_NRD_CYCLE(value) (SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))
#define SMC_CYCLE_MASK _U_(0x1FF01FF) /**< \deprecated (SMC_CYCLE) Register MASK (Use SMC_CYCLE_Msk instead) */
#define SMC_CYCLE_Msk _U_(0x1FF01FF) /**< (SMC_CYCLE) Register Mask */
/* -------- SMC_MODE : (SMC Offset: 0x0c) (R/W 32) SMC MODE Register (CS_number = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t READ_MODE:1; /**< bit: 0 Read Mode */
uint32_t WRITE_MODE:1; /**< bit: 1 Write Mode */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t EXNW_MODE:2; /**< bit: 4..5 NWAIT Mode */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t BAT:1; /**< bit: 8 Byte Access Type */
uint32_t :3; /**< bit: 9..11 Reserved */
uint32_t DBW:1; /**< bit: 12 Data Bus Width */
uint32_t :3; /**< bit: 13..15 Reserved */
uint32_t TDF_CYCLES:4; /**< bit: 16..19 Data Float Time */
uint32_t TDF_MODE:1; /**< bit: 20 TDF Optimization */
uint32_t :3; /**< bit: 21..23 Reserved */
uint32_t PMEN:1; /**< bit: 24 Page Mode Enabled */
uint32_t :3; /**< bit: 25..27 Reserved */
uint32_t PS:2; /**< bit: 28..29 Page Size */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_MODE_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_MODE_OFFSET (0x0C) /**< (SMC_MODE) SMC MODE Register (CS_number = 0) Offset */
#define SMC_MODE_READ_MODE_Pos 0 /**< (SMC_MODE) Read Mode Position */
#define SMC_MODE_READ_MODE_Msk (_U_(0x1) << SMC_MODE_READ_MODE_Pos) /**< (SMC_MODE) Read Mode Mask */
#define SMC_MODE_READ_MODE SMC_MODE_READ_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_READ_MODE_Msk instead */
#define SMC_MODE_WRITE_MODE_Pos 1 /**< (SMC_MODE) Write Mode Position */
#define SMC_MODE_WRITE_MODE_Msk (_U_(0x1) << SMC_MODE_WRITE_MODE_Pos) /**< (SMC_MODE) Write Mode Mask */
#define SMC_MODE_WRITE_MODE SMC_MODE_WRITE_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_WRITE_MODE_Msk instead */
#define SMC_MODE_EXNW_MODE_Pos 4 /**< (SMC_MODE) NWAIT Mode Position */
#define SMC_MODE_EXNW_MODE_Msk (_U_(0x3) << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) NWAIT Mode Mask */
#define SMC_MODE_EXNW_MODE(value) (SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))
#define SMC_MODE_EXNW_MODE_DISABLED_Val _U_(0x0) /**< (SMC_MODE) Disabled */
#define SMC_MODE_EXNW_MODE_FROZEN_Val _U_(0x2) /**< (SMC_MODE) Frozen Mode */
#define SMC_MODE_EXNW_MODE_READY_Val _U_(0x3) /**< (SMC_MODE) Ready Mode */
#define SMC_MODE_EXNW_MODE_DISABLED (SMC_MODE_EXNW_MODE_DISABLED_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Disabled Position */
#define SMC_MODE_EXNW_MODE_FROZEN (SMC_MODE_EXNW_MODE_FROZEN_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Frozen Mode Position */
#define SMC_MODE_EXNW_MODE_READY (SMC_MODE_EXNW_MODE_READY_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Ready Mode Position */
#define SMC_MODE_BAT_Pos 8 /**< (SMC_MODE) Byte Access Type Position */
#define SMC_MODE_BAT_Msk (_U_(0x1) << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte Access Type Mask */
#define SMC_MODE_BAT SMC_MODE_BAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_BAT_Msk instead */
#define SMC_MODE_BAT_BYTE_SELECT_Val _U_(0x0) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */
#define SMC_MODE_BAT_BYTE_WRITE_Val _U_(0x1) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */
#define SMC_MODE_BAT_BYTE_SELECT (SMC_MODE_BAT_BYTE_SELECT_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. Position */
#define SMC_MODE_BAT_BYTE_WRITE (SMC_MODE_BAT_BYTE_WRITE_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. Position */
#define SMC_MODE_DBW_Pos 12 /**< (SMC_MODE) Data Bus Width Position */
#define SMC_MODE_DBW_Msk (_U_(0x1) << SMC_MODE_DBW_Pos) /**< (SMC_MODE) Data Bus Width Mask */
#define SMC_MODE_DBW SMC_MODE_DBW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_DBW_Msk instead */
#define SMC_MODE_DBW_8_BIT_Val _U_(0x0) /**< (SMC_MODE) 8-bit Data Bus */
#define SMC_MODE_DBW_16_BIT_Val _U_(0x1) /**< (SMC_MODE) 16-bit Data Bus */
#define SMC_MODE_DBW_8_BIT (SMC_MODE_DBW_8_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 8-bit Data Bus Position */
#define SMC_MODE_DBW_16_BIT (SMC_MODE_DBW_16_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 16-bit Data Bus Position */
#define SMC_MODE_TDF_CYCLES_Pos 16 /**< (SMC_MODE) Data Float Time Position */
#define SMC_MODE_TDF_CYCLES_Msk (_U_(0xF) << SMC_MODE_TDF_CYCLES_Pos) /**< (SMC_MODE) Data Float Time Mask */
#define SMC_MODE_TDF_CYCLES(value) (SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))
#define SMC_MODE_TDF_MODE_Pos 20 /**< (SMC_MODE) TDF Optimization Position */
#define SMC_MODE_TDF_MODE_Msk (_U_(0x1) << SMC_MODE_TDF_MODE_Pos) /**< (SMC_MODE) TDF Optimization Mask */
#define SMC_MODE_TDF_MODE SMC_MODE_TDF_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_TDF_MODE_Msk instead */
#define SMC_MODE_PMEN_Pos 24 /**< (SMC_MODE) Page Mode Enabled Position */
#define SMC_MODE_PMEN_Msk (_U_(0x1) << SMC_MODE_PMEN_Pos) /**< (SMC_MODE) Page Mode Enabled Mask */
#define SMC_MODE_PMEN SMC_MODE_PMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_PMEN_Msk instead */
#define SMC_MODE_PS_Pos 28 /**< (SMC_MODE) Page Size Position */
#define SMC_MODE_PS_Msk (_U_(0x3) << SMC_MODE_PS_Pos) /**< (SMC_MODE) Page Size Mask */
#define SMC_MODE_PS(value) (SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))
#define SMC_MODE_PS_4_BYTE_Val _U_(0x0) /**< (SMC_MODE) 4-byte page */
#define SMC_MODE_PS_8_BYTE_Val _U_(0x1) /**< (SMC_MODE) 8-byte page */
#define SMC_MODE_PS_16_BYTE_Val _U_(0x2) /**< (SMC_MODE) 16-byte page */
#define SMC_MODE_PS_32_BYTE_Val _U_(0x3) /**< (SMC_MODE) 32-byte page */
#define SMC_MODE_PS_4_BYTE (SMC_MODE_PS_4_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 4-byte page Position */
#define SMC_MODE_PS_8_BYTE (SMC_MODE_PS_8_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 8-byte page Position */
#define SMC_MODE_PS_16_BYTE (SMC_MODE_PS_16_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 16-byte page Position */
#define SMC_MODE_PS_32_BYTE (SMC_MODE_PS_32_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 32-byte page Position */
#define SMC_MODE_MASK _U_(0x311F1133) /**< \deprecated (SMC_MODE) Register MASK (Use SMC_MODE_Msk instead) */
#define SMC_MODE_Msk _U_(0x311F1133) /**< (SMC_MODE) Register Mask */
/* -------- SMC_OCMS : (SMC Offset: 0x80) (R/W 32) SMC OCMS MODE Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMSE:1; /**< bit: 0 Static Memory Controller Scrambling Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t CS0SE:1; /**< bit: 8 Chip Select 0 Scrambling Enable */
uint32_t CS1SE:1; /**< bit: 9 Chip Select 1 Scrambling Enable */
uint32_t CS2SE:1; /**< bit: 10 Chip Select 2 Scrambling Enable */
uint32_t CS3SE:1; /**< bit: 11 Chip Select 3 Scrambling Enable */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_OCMS_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_OCMS_OFFSET (0x80) /**< (SMC_OCMS) SMC OCMS MODE Register Offset */
#define SMC_OCMS_SMSE_Pos 0 /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Position */
#define SMC_OCMS_SMSE_Msk (_U_(0x1) << SMC_OCMS_SMSE_Pos) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Mask */
#define SMC_OCMS_SMSE SMC_OCMS_SMSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_SMSE_Msk instead */
#define SMC_OCMS_CS0SE_Pos 8 /**< (SMC_OCMS) Chip Select 0 Scrambling Enable Position */
#define SMC_OCMS_CS0SE_Msk (_U_(0x1) << SMC_OCMS_CS0SE_Pos) /**< (SMC_OCMS) Chip Select 0 Scrambling Enable Mask */
#define SMC_OCMS_CS0SE SMC_OCMS_CS0SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS0SE_Msk instead */
#define SMC_OCMS_CS1SE_Pos 9 /**< (SMC_OCMS) Chip Select 1 Scrambling Enable Position */
#define SMC_OCMS_CS1SE_Msk (_U_(0x1) << SMC_OCMS_CS1SE_Pos) /**< (SMC_OCMS) Chip Select 1 Scrambling Enable Mask */
#define SMC_OCMS_CS1SE SMC_OCMS_CS1SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS1SE_Msk instead */
#define SMC_OCMS_CS2SE_Pos 10 /**< (SMC_OCMS) Chip Select 2 Scrambling Enable Position */
#define SMC_OCMS_CS2SE_Msk (_U_(0x1) << SMC_OCMS_CS2SE_Pos) /**< (SMC_OCMS) Chip Select 2 Scrambling Enable Mask */
#define SMC_OCMS_CS2SE SMC_OCMS_CS2SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS2SE_Msk instead */
#define SMC_OCMS_CS3SE_Pos 11 /**< (SMC_OCMS) Chip Select 3 Scrambling Enable Position */
#define SMC_OCMS_CS3SE_Msk (_U_(0x1) << SMC_OCMS_CS3SE_Pos) /**< (SMC_OCMS) Chip Select 3 Scrambling Enable Mask */
#define SMC_OCMS_CS3SE SMC_OCMS_CS3SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS3SE_Msk instead */
#define SMC_OCMS_MASK _U_(0xF01) /**< \deprecated (SMC_OCMS) Register MASK (Use SMC_OCMS_Msk instead) */
#define SMC_OCMS_Msk _U_(0xF01) /**< (SMC_OCMS) Register Mask */
/* -------- SMC_KEY1 : (SMC Offset: 0x84) (/W 32) SMC OCMS KEY1 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEY1:32; /**< bit: 0..31 Off Chip Memory Scrambling (OCMS) Key Part 1 */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_KEY1_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_KEY1_OFFSET (0x84) /**< (SMC_KEY1) SMC OCMS KEY1 Register Offset */
#define SMC_KEY1_KEY1_Pos 0 /**< (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 Position */
#define SMC_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SMC_KEY1_KEY1_Pos) /**< (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 Mask */
#define SMC_KEY1_KEY1(value) (SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))
#define SMC_KEY1_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY1) Register MASK (Use SMC_KEY1_Msk instead) */
#define SMC_KEY1_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY1) Register Mask */
/* -------- SMC_KEY2 : (SMC Offset: 0x88) (/W 32) SMC OCMS KEY2 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEY2:32; /**< bit: 0..31 Off Chip Memory Scrambling (OCMS) Key Part 2 */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_KEY2_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_KEY2_OFFSET (0x88) /**< (SMC_KEY2) SMC OCMS KEY2 Register Offset */
#define SMC_KEY2_KEY2_Pos 0 /**< (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 Position */
#define SMC_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SMC_KEY2_KEY2_Pos) /**< (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 Mask */
#define SMC_KEY2_KEY2(value) (SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))
#define SMC_KEY2_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY2) Register MASK (Use SMC_KEY2_Msk instead) */
#define SMC_KEY2_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY2) Register Mask */
/* -------- SMC_WPMR : (SMC Offset: 0xe4) (R/W 32) SMC Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protect Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_WPMR_OFFSET (0xE4) /**< (SMC_WPMR) SMC Write Protection Mode Register Offset */
#define SMC_WPMR_WPEN_Pos 0 /**< (SMC_WPMR) Write Protect Enable Position */
#define SMC_WPMR_WPEN_Msk (_U_(0x1) << SMC_WPMR_WPEN_Pos) /**< (SMC_WPMR) Write Protect Enable Mask */
#define SMC_WPMR_WPEN SMC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPMR_WPEN_Msk instead */
#define SMC_WPMR_WPKEY_Pos 8 /**< (SMC_WPMR) Write Protection Key Position */
#define SMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Write Protection Key Mask */
#define SMC_WPMR_WPKEY(value) (SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))
#define SMC_WPMR_WPKEY_PASSWD_Val _U_(0x534D43) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
#define SMC_WPMR_WPKEY_PASSWD (SMC_WPMR_WPKEY_PASSWD_Val << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */
#define SMC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SMC_WPMR) Register MASK (Use SMC_WPMR_Msk instead) */
#define SMC_WPMR_Msk _U_(0xFFFFFF01) /**< (SMC_WPMR) Register Mask */
/* -------- SMC_WPSR : (SMC Offset: 0xe8) (R/ 32) SMC Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SMC_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SMC_WPSR_OFFSET (0xE8) /**< (SMC_WPSR) SMC Write Protection Status Register Offset */
#define SMC_WPSR_WPVS_Pos 0 /**< (SMC_WPSR) Write Protection Violation Status Position */
#define SMC_WPSR_WPVS_Msk (_U_(0x1) << SMC_WPSR_WPVS_Pos) /**< (SMC_WPSR) Write Protection Violation Status Mask */
#define SMC_WPSR_WPVS SMC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPSR_WPVS_Msk instead */
#define SMC_WPSR_WPVSRC_Pos 8 /**< (SMC_WPSR) Write Protection Violation Source Position */
#define SMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SMC_WPSR_WPVSRC_Pos) /**< (SMC_WPSR) Write Protection Violation Source Mask */
#define SMC_WPSR_WPVSRC(value) (SMC_WPSR_WPVSRC_Msk & ((value) << SMC_WPSR_WPVSRC_Pos))
#define SMC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SMC_WPSR) Register MASK (Use SMC_WPSR_Msk instead) */
#define SMC_WPSR_Msk _U_(0xFFFF01) /**< (SMC_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief SMC_CS_NUMBER hardware registers */
typedef struct {
__IO uint32_t SMC_SETUP; /**< (SMC_CS_NUMBER Offset: 0x00) SMC Setup Register (CS_number = 0) */
__IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */
__IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */
__IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC MODE Register (CS_number = 0) */
} SmcCsNumber;
#define SMCCSNUMBER_NUMBER 4
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
RoReg8 Reserved1[0x40];
__IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC OCMS MODE Register */
__O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC OCMS KEY1 Register */
__O uint32_t SMC_KEY2; /**< (SMC Offset: 0x88) SMC OCMS KEY2 Register */
RoReg8 Reserved2[0x58];
__IO uint32_t SMC_WPMR; /**< (SMC Offset: 0xE4) SMC Write Protection Mode Register */
__I uint32_t SMC_WPSR; /**< (SMC Offset: 0xE8) SMC Write Protection Status Register */
} Smc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief SMC_CS_NUMBER hardware registers */
typedef struct {
__IO SMC_SETUP_Type SMC_SETUP; /**< Offset: 0x00 (R/W 32) SMC Setup Register (CS_number = 0) */
__IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */
__IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */
__IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC MODE Register (CS_number = 0) */
} SmcCsNumber;
/** \brief SMC hardware registers */
typedef struct {
SmcCsNumber SMC_CS_NUMBER[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */
__I uint32_t Reserved1[16];
__IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC OCMS MODE Register */
__O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC OCMS KEY1 Register */
__O SMC_KEY2_Type SMC_KEY2; /**< Offset: 0x88 ( /W 32) SMC OCMS KEY2 Register */
__I uint32_t Reserved2[22];
__IO SMC_WPMR_Type SMC_WPMR; /**< Offset: 0xE4 (R/W 32) SMC Write Protection Mode Register */
__I SMC_WPSR_Type SMC_WPSR; /**< Offset: 0xE8 (R/ 32) SMC Write Protection Status Register */
} Smc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Static Memory Controller */
#endif /* _SAME70_SMC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for SPI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SPI_COMPONENT_H_
#define _SAME70_SPI_COMPONENT_H_
#define _SAME70_SPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Serial Peripheral Interface
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SPI */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define SPI_6088 /**< (SPI) Module ID */
#define REV_SPI ZM /**< (SPI) Module revision */
/* -------- SPI_CR : (SPI Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SPIEN:1; /**< bit: 0 SPI Enable */
uint32_t SPIDIS:1; /**< bit: 1 SPI Disable */
uint32_t :5; /**< bit: 2..6 Reserved */
uint32_t SWRST:1; /**< bit: 7 SPI Software Reset */
uint32_t :4; /**< bit: 8..11 Reserved */
uint32_t REQCLR:1; /**< bit: 12 Request to Clear the Comparison Trigger */
uint32_t :11; /**< bit: 13..23 Reserved */
uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_CR_OFFSET (0x00) /**< (SPI_CR) Control Register Offset */
#define SPI_CR_SPIEN_Pos 0 /**< (SPI_CR) SPI Enable Position */
#define SPI_CR_SPIEN_Msk (_U_(0x1) << SPI_CR_SPIEN_Pos) /**< (SPI_CR) SPI Enable Mask */
#define SPI_CR_SPIEN SPI_CR_SPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIEN_Msk instead */
#define SPI_CR_SPIDIS_Pos 1 /**< (SPI_CR) SPI Disable Position */
#define SPI_CR_SPIDIS_Msk (_U_(0x1) << SPI_CR_SPIDIS_Pos) /**< (SPI_CR) SPI Disable Mask */
#define SPI_CR_SPIDIS SPI_CR_SPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIDIS_Msk instead */
#define SPI_CR_SWRST_Pos 7 /**< (SPI_CR) SPI Software Reset Position */
#define SPI_CR_SWRST_Msk (_U_(0x1) << SPI_CR_SWRST_Pos) /**< (SPI_CR) SPI Software Reset Mask */
#define SPI_CR_SWRST SPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SWRST_Msk instead */
#define SPI_CR_REQCLR_Pos 12 /**< (SPI_CR) Request to Clear the Comparison Trigger Position */
#define SPI_CR_REQCLR_Msk (_U_(0x1) << SPI_CR_REQCLR_Pos) /**< (SPI_CR) Request to Clear the Comparison Trigger Mask */
#define SPI_CR_REQCLR SPI_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_REQCLR_Msk instead */
#define SPI_CR_LASTXFER_Pos 24 /**< (SPI_CR) Last Transfer Position */
#define SPI_CR_LASTXFER_Msk (_U_(0x1) << SPI_CR_LASTXFER_Pos) /**< (SPI_CR) Last Transfer Mask */
#define SPI_CR_LASTXFER SPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_LASTXFER_Msk instead */
#define SPI_CR_MASK _U_(0x1001083) /**< \deprecated (SPI_CR) Register MASK (Use SPI_CR_Msk instead) */
#define SPI_CR_Msk _U_(0x1001083) /**< (SPI_CR) Register Mask */
/* -------- SPI_MR : (SPI Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MSTR:1; /**< bit: 0 Master/Slave Mode */
uint32_t PS:1; /**< bit: 1 Peripheral Select */
uint32_t PCSDEC:1; /**< bit: 2 Chip Select Decode */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t MODFDIS:1; /**< bit: 4 Mode Fault Detection */
uint32_t WDRBT:1; /**< bit: 5 Wait Data Read Before Transfer */
uint32_t :1; /**< bit: 6 Reserved */
uint32_t LLB:1; /**< bit: 7 Local Loopback Enable */
uint32_t :8; /**< bit: 8..15 Reserved */
uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */
uint32_t :4; /**< bit: 20..23 Reserved */
uint32_t DLYBCS:8; /**< bit: 24..31 Delay Between Chip Selects */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_MR_OFFSET (0x04) /**< (SPI_MR) Mode Register Offset */
#define SPI_MR_MSTR_Pos 0 /**< (SPI_MR) Master/Slave Mode Position */
#define SPI_MR_MSTR_Msk (_U_(0x1) << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master/Slave Mode Mask */
#define SPI_MR_MSTR SPI_MR_MSTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MSTR_Msk instead */
#define SPI_MR_PS_Pos 1 /**< (SPI_MR) Peripheral Select Position */
#define SPI_MR_PS_Msk (_U_(0x1) << SPI_MR_PS_Pos) /**< (SPI_MR) Peripheral Select Mask */
#define SPI_MR_PS SPI_MR_PS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PS_Msk instead */
#define SPI_MR_PCSDEC_Pos 2 /**< (SPI_MR) Chip Select Decode Position */
#define SPI_MR_PCSDEC_Msk (_U_(0x1) << SPI_MR_PCSDEC_Pos) /**< (SPI_MR) Chip Select Decode Mask */
#define SPI_MR_PCSDEC SPI_MR_PCSDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PCSDEC_Msk instead */
#define SPI_MR_MODFDIS_Pos 4 /**< (SPI_MR) Mode Fault Detection Position */
#define SPI_MR_MODFDIS_Msk (_U_(0x1) << SPI_MR_MODFDIS_Pos) /**< (SPI_MR) Mode Fault Detection Mask */
#define SPI_MR_MODFDIS SPI_MR_MODFDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MODFDIS_Msk instead */
#define SPI_MR_WDRBT_Pos 5 /**< (SPI_MR) Wait Data Read Before Transfer Position */
#define SPI_MR_WDRBT_Msk (_U_(0x1) << SPI_MR_WDRBT_Pos) /**< (SPI_MR) Wait Data Read Before Transfer Mask */
#define SPI_MR_WDRBT SPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_WDRBT_Msk instead */
#define SPI_MR_LLB_Pos 7 /**< (SPI_MR) Local Loopback Enable Position */
#define SPI_MR_LLB_Msk (_U_(0x1) << SPI_MR_LLB_Pos) /**< (SPI_MR) Local Loopback Enable Mask */
#define SPI_MR_LLB SPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_LLB_Msk instead */
#define SPI_MR_PCS_Pos 16 /**< (SPI_MR) Peripheral Chip Select Position */
#define SPI_MR_PCS_Msk (_U_(0xF) << SPI_MR_PCS_Pos) /**< (SPI_MR) Peripheral Chip Select Mask */
#define SPI_MR_PCS(value) (SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))
#define SPI_MR_DLYBCS_Pos 24 /**< (SPI_MR) Delay Between Chip Selects Position */
#define SPI_MR_DLYBCS_Msk (_U_(0xFF) << SPI_MR_DLYBCS_Pos) /**< (SPI_MR) Delay Between Chip Selects Mask */
#define SPI_MR_DLYBCS(value) (SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))
#define SPI_MR_MASK _U_(0xFF0F00B7) /**< \deprecated (SPI_MR) Register MASK (Use SPI_MR_Msk instead) */
#define SPI_MR_Msk _U_(0xFF0F00B7) /**< (SPI_MR) Register Mask */
/* -------- SPI_RDR : (SPI Offset: 0x08) (R/ 32) Receive Data Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RD:16; /**< bit: 0..15 Receive Data */
uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */
uint32_t :12; /**< bit: 20..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_RDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_RDR_OFFSET (0x08) /**< (SPI_RDR) Receive Data Register Offset */
#define SPI_RDR_RD_Pos 0 /**< (SPI_RDR) Receive Data Position */
#define SPI_RDR_RD_Msk (_U_(0xFFFF) << SPI_RDR_RD_Pos) /**< (SPI_RDR) Receive Data Mask */
#define SPI_RDR_RD(value) (SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos))
#define SPI_RDR_PCS_Pos 16 /**< (SPI_RDR) Peripheral Chip Select Position */
#define SPI_RDR_PCS_Msk (_U_(0xF) << SPI_RDR_PCS_Pos) /**< (SPI_RDR) Peripheral Chip Select Mask */
#define SPI_RDR_PCS(value) (SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos))
#define SPI_RDR_MASK _U_(0xFFFFF) /**< \deprecated (SPI_RDR) Register MASK (Use SPI_RDR_Msk instead) */
#define SPI_RDR_Msk _U_(0xFFFFF) /**< (SPI_RDR) Register Mask */
/* -------- SPI_TDR : (SPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TD:16; /**< bit: 0..15 Transmit Data */
uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */
uint32_t :4; /**< bit: 20..23 Reserved */
uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */
uint32_t :7; /**< bit: 25..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_TDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_TDR_OFFSET (0x0C) /**< (SPI_TDR) Transmit Data Register Offset */
#define SPI_TDR_TD_Pos 0 /**< (SPI_TDR) Transmit Data Position */
#define SPI_TDR_TD_Msk (_U_(0xFFFF) << SPI_TDR_TD_Pos) /**< (SPI_TDR) Transmit Data Mask */
#define SPI_TDR_TD(value) (SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))
#define SPI_TDR_PCS_Pos 16 /**< (SPI_TDR) Peripheral Chip Select Position */
#define SPI_TDR_PCS_Msk (_U_(0xF) << SPI_TDR_PCS_Pos) /**< (SPI_TDR) Peripheral Chip Select Mask */
#define SPI_TDR_PCS(value) (SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))
#define SPI_TDR_LASTXFER_Pos 24 /**< (SPI_TDR) Last Transfer Position */
#define SPI_TDR_LASTXFER_Msk (_U_(0x1) << SPI_TDR_LASTXFER_Pos) /**< (SPI_TDR) Last Transfer Mask */
#define SPI_TDR_LASTXFER SPI_TDR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_TDR_LASTXFER_Msk instead */
#define SPI_TDR_MASK _U_(0x10FFFFF) /**< \deprecated (SPI_TDR) Register MASK (Use SPI_TDR_Msk instead) */
#define SPI_TDR_Msk _U_(0x10FFFFF) /**< (SPI_TDR) Register Mask */
/* -------- SPI_SR : (SPI Offset: 0x10) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */
uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */
uint32_t MODF:1; /**< bit: 2 Mode Fault Error (cleared on read) */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t NSSR:1; /**< bit: 8 NSS Rising (cleared on read) */
uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty (cleared by writing SPI_TDR) */
uint32_t UNDES:1; /**< bit: 10 Underrun Error Status (Slave mode only) (cleared on read) */
uint32_t :5; /**< bit: 11..15 Reserved */
uint32_t SPIENS:1; /**< bit: 16 SPI Enable Status */
uint32_t :15; /**< bit: 17..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_SR_OFFSET (0x10) /**< (SPI_SR) Status Register Offset */
#define SPI_SR_RDRF_Pos 0 /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */
#define SPI_SR_RDRF_Msk (_U_(0x1) << SPI_SR_RDRF_Pos) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */
#define SPI_SR_RDRF SPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_RDRF_Msk instead */
#define SPI_SR_TDRE_Pos 1 /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */
#define SPI_SR_TDRE_Msk (_U_(0x1) << SPI_SR_TDRE_Pos) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */
#define SPI_SR_TDRE SPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TDRE_Msk instead */
#define SPI_SR_MODF_Pos 2 /**< (SPI_SR) Mode Fault Error (cleared on read) Position */
#define SPI_SR_MODF_Msk (_U_(0x1) << SPI_SR_MODF_Pos) /**< (SPI_SR) Mode Fault Error (cleared on read) Mask */
#define SPI_SR_MODF SPI_SR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_MODF_Msk instead */
#define SPI_SR_OVRES_Pos 3 /**< (SPI_SR) Overrun Error Status (cleared on read) Position */
#define SPI_SR_OVRES_Msk (_U_(0x1) << SPI_SR_OVRES_Pos) /**< (SPI_SR) Overrun Error Status (cleared on read) Mask */
#define SPI_SR_OVRES SPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_OVRES_Msk instead */
#define SPI_SR_NSSR_Pos 8 /**< (SPI_SR) NSS Rising (cleared on read) Position */
#define SPI_SR_NSSR_Msk (_U_(0x1) << SPI_SR_NSSR_Pos) /**< (SPI_SR) NSS Rising (cleared on read) Mask */
#define SPI_SR_NSSR SPI_SR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_NSSR_Msk instead */
#define SPI_SR_TXEMPTY_Pos 9 /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */
#define SPI_SR_TXEMPTY_Msk (_U_(0x1) << SPI_SR_TXEMPTY_Pos) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */
#define SPI_SR_TXEMPTY SPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TXEMPTY_Msk instead */
#define SPI_SR_UNDES_Pos 10 /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Position */
#define SPI_SR_UNDES_Msk (_U_(0x1) << SPI_SR_UNDES_Pos) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Mask */
#define SPI_SR_UNDES SPI_SR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_UNDES_Msk instead */
#define SPI_SR_SPIENS_Pos 16 /**< (SPI_SR) SPI Enable Status Position */
#define SPI_SR_SPIENS_Msk (_U_(0x1) << SPI_SR_SPIENS_Pos) /**< (SPI_SR) SPI Enable Status Mask */
#define SPI_SR_SPIENS SPI_SR_SPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_SPIENS_Msk instead */
#define SPI_SR_MASK _U_(0x1070F) /**< \deprecated (SPI_SR) Register MASK (Use SPI_SR_Msk instead) */
#define SPI_SR_Msk _U_(0x1070F) /**< (SPI_SR) Register Mask */
/* -------- SPI_IER : (SPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */
uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Enable */
uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Enable */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Enable */
uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Enable */
uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Enable */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_IER_OFFSET (0x14) /**< (SPI_IER) Interrupt Enable Register Offset */
#define SPI_IER_RDRF_Pos 0 /**< (SPI_IER) Receive Data Register Full Interrupt Enable Position */
#define SPI_IER_RDRF_Msk (_U_(0x1) << SPI_IER_RDRF_Pos) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Mask */
#define SPI_IER_RDRF SPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_RDRF_Msk instead */
#define SPI_IER_TDRE_Pos 1 /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Position */
#define SPI_IER_TDRE_Msk (_U_(0x1) << SPI_IER_TDRE_Pos) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Mask */
#define SPI_IER_TDRE SPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TDRE_Msk instead */
#define SPI_IER_MODF_Pos 2 /**< (SPI_IER) Mode Fault Error Interrupt Enable Position */
#define SPI_IER_MODF_Msk (_U_(0x1) << SPI_IER_MODF_Pos) /**< (SPI_IER) Mode Fault Error Interrupt Enable Mask */
#define SPI_IER_MODF SPI_IER_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_MODF_Msk instead */
#define SPI_IER_OVRES_Pos 3 /**< (SPI_IER) Overrun Error Interrupt Enable Position */
#define SPI_IER_OVRES_Msk (_U_(0x1) << SPI_IER_OVRES_Pos) /**< (SPI_IER) Overrun Error Interrupt Enable Mask */
#define SPI_IER_OVRES SPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_OVRES_Msk instead */
#define SPI_IER_NSSR_Pos 8 /**< (SPI_IER) NSS Rising Interrupt Enable Position */
#define SPI_IER_NSSR_Msk (_U_(0x1) << SPI_IER_NSSR_Pos) /**< (SPI_IER) NSS Rising Interrupt Enable Mask */
#define SPI_IER_NSSR SPI_IER_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_NSSR_Msk instead */
#define SPI_IER_TXEMPTY_Pos 9 /**< (SPI_IER) Transmission Registers Empty Enable Position */
#define SPI_IER_TXEMPTY_Msk (_U_(0x1) << SPI_IER_TXEMPTY_Pos) /**< (SPI_IER) Transmission Registers Empty Enable Mask */
#define SPI_IER_TXEMPTY SPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TXEMPTY_Msk instead */
#define SPI_IER_UNDES_Pos 10 /**< (SPI_IER) Underrun Error Interrupt Enable Position */
#define SPI_IER_UNDES_Msk (_U_(0x1) << SPI_IER_UNDES_Pos) /**< (SPI_IER) Underrun Error Interrupt Enable Mask */
#define SPI_IER_UNDES SPI_IER_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_UNDES_Msk instead */
#define SPI_IER_MASK _U_(0x70F) /**< \deprecated (SPI_IER) Register MASK (Use SPI_IER_Msk instead) */
#define SPI_IER_Msk _U_(0x70F) /**< (SPI_IER) Register Mask */
/* -------- SPI_IDR : (SPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */
uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Disable */
uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Disable */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Disable */
uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Disable */
uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Disable */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_IDR_OFFSET (0x18) /**< (SPI_IDR) Interrupt Disable Register Offset */
#define SPI_IDR_RDRF_Pos 0 /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Position */
#define SPI_IDR_RDRF_Msk (_U_(0x1) << SPI_IDR_RDRF_Pos) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Mask */
#define SPI_IDR_RDRF SPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_RDRF_Msk instead */
#define SPI_IDR_TDRE_Pos 1 /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Position */
#define SPI_IDR_TDRE_Msk (_U_(0x1) << SPI_IDR_TDRE_Pos) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Mask */
#define SPI_IDR_TDRE SPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TDRE_Msk instead */
#define SPI_IDR_MODF_Pos 2 /**< (SPI_IDR) Mode Fault Error Interrupt Disable Position */
#define SPI_IDR_MODF_Msk (_U_(0x1) << SPI_IDR_MODF_Pos) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Mask */
#define SPI_IDR_MODF SPI_IDR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_MODF_Msk instead */
#define SPI_IDR_OVRES_Pos 3 /**< (SPI_IDR) Overrun Error Interrupt Disable Position */
#define SPI_IDR_OVRES_Msk (_U_(0x1) << SPI_IDR_OVRES_Pos) /**< (SPI_IDR) Overrun Error Interrupt Disable Mask */
#define SPI_IDR_OVRES SPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_OVRES_Msk instead */
#define SPI_IDR_NSSR_Pos 8 /**< (SPI_IDR) NSS Rising Interrupt Disable Position */
#define SPI_IDR_NSSR_Msk (_U_(0x1) << SPI_IDR_NSSR_Pos) /**< (SPI_IDR) NSS Rising Interrupt Disable Mask */
#define SPI_IDR_NSSR SPI_IDR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_NSSR_Msk instead */
#define SPI_IDR_TXEMPTY_Pos 9 /**< (SPI_IDR) Transmission Registers Empty Disable Position */
#define SPI_IDR_TXEMPTY_Msk (_U_(0x1) << SPI_IDR_TXEMPTY_Pos) /**< (SPI_IDR) Transmission Registers Empty Disable Mask */
#define SPI_IDR_TXEMPTY SPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TXEMPTY_Msk instead */
#define SPI_IDR_UNDES_Pos 10 /**< (SPI_IDR) Underrun Error Interrupt Disable Position */
#define SPI_IDR_UNDES_Msk (_U_(0x1) << SPI_IDR_UNDES_Pos) /**< (SPI_IDR) Underrun Error Interrupt Disable Mask */
#define SPI_IDR_UNDES SPI_IDR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_UNDES_Msk instead */
#define SPI_IDR_MASK _U_(0x70F) /**< \deprecated (SPI_IDR) Register MASK (Use SPI_IDR_Msk instead) */
#define SPI_IDR_Msk _U_(0x70F) /**< (SPI_IDR) Register Mask */
/* -------- SPI_IMR : (SPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */
uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Mask */
uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Mask */
uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Mask */
uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Mask */
uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Mask */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_IMR_OFFSET (0x1C) /**< (SPI_IMR) Interrupt Mask Register Offset */
#define SPI_IMR_RDRF_Pos 0 /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Position */
#define SPI_IMR_RDRF_Msk (_U_(0x1) << SPI_IMR_RDRF_Pos) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Mask */
#define SPI_IMR_RDRF SPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_RDRF_Msk instead */
#define SPI_IMR_TDRE_Pos 1 /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Position */
#define SPI_IMR_TDRE_Msk (_U_(0x1) << SPI_IMR_TDRE_Pos) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Mask */
#define SPI_IMR_TDRE SPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TDRE_Msk instead */
#define SPI_IMR_MODF_Pos 2 /**< (SPI_IMR) Mode Fault Error Interrupt Mask Position */
#define SPI_IMR_MODF_Msk (_U_(0x1) << SPI_IMR_MODF_Pos) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Mask */
#define SPI_IMR_MODF SPI_IMR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_MODF_Msk instead */
#define SPI_IMR_OVRES_Pos 3 /**< (SPI_IMR) Overrun Error Interrupt Mask Position */
#define SPI_IMR_OVRES_Msk (_U_(0x1) << SPI_IMR_OVRES_Pos) /**< (SPI_IMR) Overrun Error Interrupt Mask Mask */
#define SPI_IMR_OVRES SPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_OVRES_Msk instead */
#define SPI_IMR_NSSR_Pos 8 /**< (SPI_IMR) NSS Rising Interrupt Mask Position */
#define SPI_IMR_NSSR_Msk (_U_(0x1) << SPI_IMR_NSSR_Pos) /**< (SPI_IMR) NSS Rising Interrupt Mask Mask */
#define SPI_IMR_NSSR SPI_IMR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_NSSR_Msk instead */
#define SPI_IMR_TXEMPTY_Pos 9 /**< (SPI_IMR) Transmission Registers Empty Mask Position */
#define SPI_IMR_TXEMPTY_Msk (_U_(0x1) << SPI_IMR_TXEMPTY_Pos) /**< (SPI_IMR) Transmission Registers Empty Mask Mask */
#define SPI_IMR_TXEMPTY SPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TXEMPTY_Msk instead */
#define SPI_IMR_UNDES_Pos 10 /**< (SPI_IMR) Underrun Error Interrupt Mask Position */
#define SPI_IMR_UNDES_Msk (_U_(0x1) << SPI_IMR_UNDES_Pos) /**< (SPI_IMR) Underrun Error Interrupt Mask Mask */
#define SPI_IMR_UNDES SPI_IMR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_UNDES_Msk instead */
#define SPI_IMR_MASK _U_(0x70F) /**< \deprecated (SPI_IMR) Register MASK (Use SPI_IMR_Msk instead) */
#define SPI_IMR_Msk _U_(0x70F) /**< (SPI_IMR) Register Mask */
/* -------- SPI_CSR : (SPI Offset: 0x30) (R/W 32) Chip Select Register 0 -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CPOL:1; /**< bit: 0 Clock Polarity */
uint32_t NCPHA:1; /**< bit: 1 Clock Phase */
uint32_t CSNAAT:1; /**< bit: 2 Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
uint32_t CSAAT:1; /**< bit: 3 Chip Select Active After Transfer */
uint32_t BITS:4; /**< bit: 4..7 Bits Per Transfer */
uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Bit Rate */
uint32_t DLYBS:8; /**< bit: 16..23 Delay Before SPCK */
uint32_t DLYBCT:8; /**< bit: 24..31 Delay Between Consecutive Transfers */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_CSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_CSR_OFFSET (0x30) /**< (SPI_CSR) Chip Select Register 0 Offset */
#define SPI_CSR_CPOL_Pos 0 /**< (SPI_CSR) Clock Polarity Position */
#define SPI_CSR_CPOL_Msk (_U_(0x1) << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock Polarity Mask */
#define SPI_CSR_CPOL SPI_CSR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CPOL_Msk instead */
#define SPI_CSR_NCPHA_Pos 1 /**< (SPI_CSR) Clock Phase Position */
#define SPI_CSR_NCPHA_Msk (_U_(0x1) << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Clock Phase Mask */
#define SPI_CSR_NCPHA SPI_CSR_NCPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_NCPHA_Msk instead */
#define SPI_CSR_CSNAAT_Pos 2 /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Position */
#define SPI_CSR_CSNAAT_Msk (_U_(0x1) << SPI_CSR_CSNAAT_Pos) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Mask */
#define SPI_CSR_CSNAAT SPI_CSR_CSNAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSNAAT_Msk instead */
#define SPI_CSR_CSAAT_Pos 3 /**< (SPI_CSR) Chip Select Active After Transfer Position */
#define SPI_CSR_CSAAT_Msk (_U_(0x1) << SPI_CSR_CSAAT_Pos) /**< (SPI_CSR) Chip Select Active After Transfer Mask */
#define SPI_CSR_CSAAT SPI_CSR_CSAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSAAT_Msk instead */
#define SPI_CSR_BITS_Pos 4 /**< (SPI_CSR) Bits Per Transfer Position */
#define SPI_CSR_BITS_Msk (_U_(0xF) << SPI_CSR_BITS_Pos) /**< (SPI_CSR) Bits Per Transfer Mask */
#define SPI_CSR_BITS(value) (SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))
#define SPI_CSR_BITS_8_BIT_Val _U_(0x0) /**< (SPI_CSR) 8 bits for transfer */
#define SPI_CSR_BITS_9_BIT_Val _U_(0x1) /**< (SPI_CSR) 9 bits for transfer */
#define SPI_CSR_BITS_10_BIT_Val _U_(0x2) /**< (SPI_CSR) 10 bits for transfer */
#define SPI_CSR_BITS_11_BIT_Val _U_(0x3) /**< (SPI_CSR) 11 bits for transfer */
#define SPI_CSR_BITS_12_BIT_Val _U_(0x4) /**< (SPI_CSR) 12 bits for transfer */
#define SPI_CSR_BITS_13_BIT_Val _U_(0x5) /**< (SPI_CSR) 13 bits for transfer */
#define SPI_CSR_BITS_14_BIT_Val _U_(0x6) /**< (SPI_CSR) 14 bits for transfer */
#define SPI_CSR_BITS_15_BIT_Val _U_(0x7) /**< (SPI_CSR) 15 bits for transfer */
#define SPI_CSR_BITS_16_BIT_Val _U_(0x8) /**< (SPI_CSR) 16 bits for transfer */
#define SPI_CSR_BITS_8_BIT (SPI_CSR_BITS_8_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 8 bits for transfer Position */
#define SPI_CSR_BITS_9_BIT (SPI_CSR_BITS_9_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 9 bits for transfer Position */
#define SPI_CSR_BITS_10_BIT (SPI_CSR_BITS_10_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 10 bits for transfer Position */
#define SPI_CSR_BITS_11_BIT (SPI_CSR_BITS_11_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 11 bits for transfer Position */
#define SPI_CSR_BITS_12_BIT (SPI_CSR_BITS_12_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 12 bits for transfer Position */
#define SPI_CSR_BITS_13_BIT (SPI_CSR_BITS_13_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 13 bits for transfer Position */
#define SPI_CSR_BITS_14_BIT (SPI_CSR_BITS_14_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 14 bits for transfer Position */
#define SPI_CSR_BITS_15_BIT (SPI_CSR_BITS_15_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 15 bits for transfer Position */
#define SPI_CSR_BITS_16_BIT (SPI_CSR_BITS_16_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 16 bits for transfer Position */
#define SPI_CSR_SCBR_Pos 8 /**< (SPI_CSR) Serial Clock Bit Rate Position */
#define SPI_CSR_SCBR_Msk (_U_(0xFF) << SPI_CSR_SCBR_Pos) /**< (SPI_CSR) Serial Clock Bit Rate Mask */
#define SPI_CSR_SCBR(value) (SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))
#define SPI_CSR_DLYBS_Pos 16 /**< (SPI_CSR) Delay Before SPCK Position */
#define SPI_CSR_DLYBS_Msk (_U_(0xFF) << SPI_CSR_DLYBS_Pos) /**< (SPI_CSR) Delay Before SPCK Mask */
#define SPI_CSR_DLYBS(value) (SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))
#define SPI_CSR_DLYBCT_Pos 24 /**< (SPI_CSR) Delay Between Consecutive Transfers Position */
#define SPI_CSR_DLYBCT_Msk (_U_(0xFF) << SPI_CSR_DLYBCT_Pos) /**< (SPI_CSR) Delay Between Consecutive Transfers Mask */
#define SPI_CSR_DLYBCT(value) (SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))
#define SPI_CSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SPI_CSR) Register MASK (Use SPI_CSR_Msk instead) */
#define SPI_CSR_Msk _U_(0xFFFFFFFF) /**< (SPI_CSR) Register Mask */
/* -------- SPI_WPMR : (SPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_WPMR_OFFSET (0xE4) /**< (SPI_WPMR) Write Protection Mode Register Offset */
#define SPI_WPMR_WPEN_Pos 0 /**< (SPI_WPMR) Write Protection Enable Position */
#define SPI_WPMR_WPEN_Msk (_U_(0x1) << SPI_WPMR_WPEN_Pos) /**< (SPI_WPMR) Write Protection Enable Mask */
#define SPI_WPMR_WPEN SPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPMR_WPEN_Msk instead */
#define SPI_WPMR_WPKEY_Pos 8 /**< (SPI_WPMR) Write Protection Key Position */
#define SPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Write Protection Key Mask */
#define SPI_WPMR_WPKEY(value) (SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))
#define SPI_WPMR_WPKEY_PASSWD_Val _U_(0x535049) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define SPI_WPMR_WPKEY_PASSWD (SPI_WPMR_WPKEY_PASSWD_Val << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define SPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SPI_WPMR) Register MASK (Use SPI_WPMR_Msk instead) */
#define SPI_WPMR_Msk _U_(0xFFFFFF01) /**< (SPI_WPMR) Register Mask */
/* -------- SPI_WPSR : (SPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SPI_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SPI_WPSR_OFFSET (0xE8) /**< (SPI_WPSR) Write Protection Status Register Offset */
#define SPI_WPSR_WPVS_Pos 0 /**< (SPI_WPSR) Write Protection Violation Status Position */
#define SPI_WPSR_WPVS_Msk (_U_(0x1) << SPI_WPSR_WPVS_Pos) /**< (SPI_WPSR) Write Protection Violation Status Mask */
#define SPI_WPSR_WPVS SPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPSR_WPVS_Msk instead */
#define SPI_WPSR_WPVSRC_Pos 8 /**< (SPI_WPSR) Write Protection Violation Source Position */
#define SPI_WPSR_WPVSRC_Msk (_U_(0xFF) << SPI_WPSR_WPVSRC_Pos) /**< (SPI_WPSR) Write Protection Violation Source Mask */
#define SPI_WPSR_WPVSRC(value) (SPI_WPSR_WPVSRC_Msk & ((value) << SPI_WPSR_WPVSRC_Pos))
#define SPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (SPI_WPSR) Register MASK (Use SPI_WPSR_Msk instead) */
#define SPI_WPSR_Msk _U_(0xFF01) /**< (SPI_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief SPI hardware registers */
typedef struct {
__O uint32_t SPI_CR; /**< (SPI Offset: 0x00) Control Register */
__IO uint32_t SPI_MR; /**< (SPI Offset: 0x04) Mode Register */
__I uint32_t SPI_RDR; /**< (SPI Offset: 0x08) Receive Data Register */
__O uint32_t SPI_TDR; /**< (SPI Offset: 0x0C) Transmit Data Register */
__I uint32_t SPI_SR; /**< (SPI Offset: 0x10) Status Register */
__O uint32_t SPI_IER; /**< (SPI Offset: 0x14) Interrupt Enable Register */
__O uint32_t SPI_IDR; /**< (SPI Offset: 0x18) Interrupt Disable Register */
__I uint32_t SPI_IMR; /**< (SPI Offset: 0x1C) Interrupt Mask Register */
RoReg8 Reserved1[0x10];
__IO uint32_t SPI_CSR[4]; /**< (SPI Offset: 0x30) Chip Select Register 0 */
RoReg8 Reserved2[0xA4];
__IO uint32_t SPI_WPMR; /**< (SPI Offset: 0xE4) Write Protection Mode Register */
__I uint32_t SPI_WPSR; /**< (SPI Offset: 0xE8) Write Protection Status Register */
} Spi;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief SPI hardware registers */
typedef struct {
__O SPI_CR_Type SPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO SPI_MR_Type SPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I SPI_RDR_Type SPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */
__O SPI_TDR_Type SPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */
__I SPI_SR_Type SPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */
__O SPI_IER_Type SPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */
__O SPI_IDR_Type SPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */
__I SPI_IMR_Type SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */
__I uint32_t Reserved1[4];
__IO SPI_CSR_Type SPI_CSR[4]; /**< Offset: 0x30 (R/W 32) Chip Select Register 0 */
__I uint32_t Reserved2[41];
__IO SPI_WPMR_Type SPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I SPI_WPSR_Type SPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Spi;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Serial Peripheral Interface */
#endif /* _SAME70_SPI_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for SSC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SSC_COMPONENT_H_
#define _SAME70_SSC_COMPONENT_H_
#define _SAME70_SSC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Synchronous Serial Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SSC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define SSC_6078 /**< (SSC) Module ID */
#define REV_SSC Q /**< (SSC) Module revision */
/* -------- SSC_CR : (SSC Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXEN:1; /**< bit: 0 Receive Enable */
uint32_t RXDIS:1; /**< bit: 1 Receive Disable */
uint32_t :6; /**< bit: 2..7 Reserved */
uint32_t TXEN:1; /**< bit: 8 Transmit Enable */
uint32_t TXDIS:1; /**< bit: 9 Transmit Disable */
uint32_t :5; /**< bit: 10..14 Reserved */
uint32_t SWRST:1; /**< bit: 15 Software Reset */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_CR_OFFSET (0x00) /**< (SSC_CR) Control Register Offset */
#define SSC_CR_RXEN_Pos 0 /**< (SSC_CR) Receive Enable Position */
#define SSC_CR_RXEN_Msk (_U_(0x1) << SSC_CR_RXEN_Pos) /**< (SSC_CR) Receive Enable Mask */
#define SSC_CR_RXEN SSC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXEN_Msk instead */
#define SSC_CR_RXDIS_Pos 1 /**< (SSC_CR) Receive Disable Position */
#define SSC_CR_RXDIS_Msk (_U_(0x1) << SSC_CR_RXDIS_Pos) /**< (SSC_CR) Receive Disable Mask */
#define SSC_CR_RXDIS SSC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXDIS_Msk instead */
#define SSC_CR_TXEN_Pos 8 /**< (SSC_CR) Transmit Enable Position */
#define SSC_CR_TXEN_Msk (_U_(0x1) << SSC_CR_TXEN_Pos) /**< (SSC_CR) Transmit Enable Mask */
#define SSC_CR_TXEN SSC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXEN_Msk instead */
#define SSC_CR_TXDIS_Pos 9 /**< (SSC_CR) Transmit Disable Position */
#define SSC_CR_TXDIS_Msk (_U_(0x1) << SSC_CR_TXDIS_Pos) /**< (SSC_CR) Transmit Disable Mask */
#define SSC_CR_TXDIS SSC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXDIS_Msk instead */
#define SSC_CR_SWRST_Pos 15 /**< (SSC_CR) Software Reset Position */
#define SSC_CR_SWRST_Msk (_U_(0x1) << SSC_CR_SWRST_Pos) /**< (SSC_CR) Software Reset Mask */
#define SSC_CR_SWRST SSC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_SWRST_Msk instead */
#define SSC_CR_MASK _U_(0x8303) /**< \deprecated (SSC_CR) Register MASK (Use SSC_CR_Msk instead) */
#define SSC_CR_Msk _U_(0x8303) /**< (SSC_CR) Register Mask */
/* -------- SSC_CMR : (SSC Offset: 0x04) (R/W 32) Clock Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIV:12; /**< bit: 0..11 Clock Divider */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_CMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_CMR_OFFSET (0x04) /**< (SSC_CMR) Clock Mode Register Offset */
#define SSC_CMR_DIV_Pos 0 /**< (SSC_CMR) Clock Divider Position */
#define SSC_CMR_DIV_Msk (_U_(0xFFF) << SSC_CMR_DIV_Pos) /**< (SSC_CMR) Clock Divider Mask */
#define SSC_CMR_DIV(value) (SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))
#define SSC_CMR_MASK _U_(0xFFF) /**< \deprecated (SSC_CMR) Register MASK (Use SSC_CMR_Msk instead) */
#define SSC_CMR_Msk _U_(0xFFF) /**< (SSC_CMR) Register Mask */
/* -------- SSC_RCMR : (SSC Offset: 0x10) (R/W 32) Receive Clock Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CKS:2; /**< bit: 0..1 Receive Clock Selection */
uint32_t CKO:3; /**< bit: 2..4 Receive Clock Output Mode Selection */
uint32_t CKI:1; /**< bit: 5 Receive Clock Inversion */
uint32_t CKG:2; /**< bit: 6..7 Receive Clock Gating Selection */
uint32_t START:4; /**< bit: 8..11 Receive Start Selection */
uint32_t STOP:1; /**< bit: 12 Receive Stop Selection */
uint32_t :3; /**< bit: 13..15 Reserved */
uint32_t STTDLY:8; /**< bit: 16..23 Receive Start Delay */
uint32_t PERIOD:8; /**< bit: 24..31 Receive Period Divider Selection */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RCMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RCMR_OFFSET (0x10) /**< (SSC_RCMR) Receive Clock Mode Register Offset */
#define SSC_RCMR_CKS_Pos 0 /**< (SSC_RCMR) Receive Clock Selection Position */
#define SSC_RCMR_CKS_Msk (_U_(0x3) << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Receive Clock Selection Mask */
#define SSC_RCMR_CKS(value) (SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))
#define SSC_RCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_RCMR) Divided Clock */
#define SSC_RCMR_CKS_TK_Val _U_(0x1) /**< (SSC_RCMR) TK Clock signal */
#define SSC_RCMR_CKS_RK_Val _U_(0x2) /**< (SSC_RCMR) RK pin */
#define SSC_RCMR_CKS_MCK (SSC_RCMR_CKS_MCK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Divided Clock Position */
#define SSC_RCMR_CKS_TK (SSC_RCMR_CKS_TK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) TK Clock signal Position */
#define SSC_RCMR_CKS_RK (SSC_RCMR_CKS_RK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) RK pin Position */
#define SSC_RCMR_CKO_Pos 2 /**< (SSC_RCMR) Receive Clock Output Mode Selection Position */
#define SSC_RCMR_CKO_Msk (_U_(0x7) << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock Output Mode Selection Mask */
#define SSC_RCMR_CKO(value) (SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))
#define SSC_RCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_RCMR) None, RK pin is an input */
#define SSC_RCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output */
#define SSC_RCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */
#define SSC_RCMR_CKO_NONE (SSC_RCMR_CKO_NONE_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) None, RK pin is an input Position */
#define SSC_RCMR_CKO_CONTINUOUS (SSC_RCMR_CKO_CONTINUOUS_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output Position */
#define SSC_RCMR_CKO_TRANSFER (SSC_RCMR_CKO_TRANSFER_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output Position */
#define SSC_RCMR_CKI_Pos 5 /**< (SSC_RCMR) Receive Clock Inversion Position */
#define SSC_RCMR_CKI_Msk (_U_(0x1) << SSC_RCMR_CKI_Pos) /**< (SSC_RCMR) Receive Clock Inversion Mask */
#define SSC_RCMR_CKI SSC_RCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_CKI_Msk instead */
#define SSC_RCMR_CKG_Pos 6 /**< (SSC_RCMR) Receive Clock Gating Selection Position */
#define SSC_RCMR_CKG_Msk (_U_(0x3) << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock Gating Selection Mask */
#define SSC_RCMR_CKG(value) (SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))
#define SSC_RCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) None */
#define SSC_RCMR_CKG_EN_RF_LOW_Val _U_(0x1) /**< (SSC_RCMR) Receive Clock enabled only if RF Low */
#define SSC_RCMR_CKG_EN_RF_HIGH_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock enabled only if RF High */
#define SSC_RCMR_CKG_CONTINUOUS (SSC_RCMR_CKG_CONTINUOUS_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) None Position */
#define SSC_RCMR_CKG_EN_RF_LOW (SSC_RCMR_CKG_EN_RF_LOW_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF Low Position */
#define SSC_RCMR_CKG_EN_RF_HIGH (SSC_RCMR_CKG_EN_RF_HIGH_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF High Position */
#define SSC_RCMR_START_Pos 8 /**< (SSC_RCMR) Receive Start Selection Position */
#define SSC_RCMR_START_Msk (_U_(0xF) << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Receive Start Selection Mask */
#define SSC_RCMR_START(value) (SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))
#define SSC_RCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
#define SSC_RCMR_START_TRANSMIT_Val _U_(0x1) /**< (SSC_RCMR) Transmit start */
#define SSC_RCMR_START_RF_LOW_Val _U_(0x2) /**< (SSC_RCMR) Detection of a low level on RF signal */
#define SSC_RCMR_START_RF_HIGH_Val _U_(0x3) /**< (SSC_RCMR) Detection of a high level on RF signal */
#define SSC_RCMR_START_RF_FALLING_Val _U_(0x4) /**< (SSC_RCMR) Detection of a falling edge on RF signal */
#define SSC_RCMR_START_RF_RISING_Val _U_(0x5) /**< (SSC_RCMR) Detection of a rising edge on RF signal */
#define SSC_RCMR_START_RF_LEVEL_Val _U_(0x6) /**< (SSC_RCMR) Detection of any level change on RF signal */
#define SSC_RCMR_START_RF_EDGE_Val _U_(0x7) /**< (SSC_RCMR) Detection of any edge on RF signal */
#define SSC_RCMR_START_CMP_0_Val _U_(0x8) /**< (SSC_RCMR) Compare 0 */
#define SSC_RCMR_START_CONTINUOUS (SSC_RCMR_START_CONTINUOUS_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Position */
#define SSC_RCMR_START_TRANSMIT (SSC_RCMR_START_TRANSMIT_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Transmit start Position */
#define SSC_RCMR_START_RF_LOW (SSC_RCMR_START_RF_LOW_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a low level on RF signal Position */
#define SSC_RCMR_START_RF_HIGH (SSC_RCMR_START_RF_HIGH_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a high level on RF signal Position */
#define SSC_RCMR_START_RF_FALLING (SSC_RCMR_START_RF_FALLING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a falling edge on RF signal Position */
#define SSC_RCMR_START_RF_RISING (SSC_RCMR_START_RF_RISING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a rising edge on RF signal Position */
#define SSC_RCMR_START_RF_LEVEL (SSC_RCMR_START_RF_LEVEL_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any level change on RF signal Position */
#define SSC_RCMR_START_RF_EDGE (SSC_RCMR_START_RF_EDGE_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any edge on RF signal Position */
#define SSC_RCMR_START_CMP_0 (SSC_RCMR_START_CMP_0_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Compare 0 Position */
#define SSC_RCMR_STOP_Pos 12 /**< (SSC_RCMR) Receive Stop Selection Position */
#define SSC_RCMR_STOP_Msk (_U_(0x1) << SSC_RCMR_STOP_Pos) /**< (SSC_RCMR) Receive Stop Selection Mask */
#define SSC_RCMR_STOP SSC_RCMR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_STOP_Msk instead */
#define SSC_RCMR_STTDLY_Pos 16 /**< (SSC_RCMR) Receive Start Delay Position */
#define SSC_RCMR_STTDLY_Msk (_U_(0xFF) << SSC_RCMR_STTDLY_Pos) /**< (SSC_RCMR) Receive Start Delay Mask */
#define SSC_RCMR_STTDLY(value) (SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))
#define SSC_RCMR_PERIOD_Pos 24 /**< (SSC_RCMR) Receive Period Divider Selection Position */
#define SSC_RCMR_PERIOD_Msk (_U_(0xFF) << SSC_RCMR_PERIOD_Pos) /**< (SSC_RCMR) Receive Period Divider Selection Mask */
#define SSC_RCMR_PERIOD(value) (SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))
#define SSC_RCMR_MASK _U_(0xFFFF1FFF) /**< \deprecated (SSC_RCMR) Register MASK (Use SSC_RCMR_Msk instead) */
#define SSC_RCMR_Msk _U_(0xFFFF1FFF) /**< (SSC_RCMR) Register Mask */
/* -------- SSC_RFMR : (SSC Offset: 0x14) (R/W 32) Receive Frame Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATLEN:5; /**< bit: 0..4 Data Length */
uint32_t LOOP:1; /**< bit: 5 Loop Mode */
uint32_t :1; /**< bit: 6 Reserved */
uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */
uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t FSLEN:4; /**< bit: 16..19 Receive Frame Sync Length */
uint32_t FSOS:3; /**< bit: 20..22 Receive Frame Sync Output Selection */
uint32_t :1; /**< bit: 23 Reserved */
uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */
uint32_t :3; /**< bit: 25..27 Reserved */
uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RFMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RFMR_OFFSET (0x14) /**< (SSC_RFMR) Receive Frame Mode Register Offset */
#define SSC_RFMR_DATLEN_Pos 0 /**< (SSC_RFMR) Data Length Position */
#define SSC_RFMR_DATLEN_Msk (_U_(0x1F) << SSC_RFMR_DATLEN_Pos) /**< (SSC_RFMR) Data Length Mask */
#define SSC_RFMR_DATLEN(value) (SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))
#define SSC_RFMR_LOOP_Pos 5 /**< (SSC_RFMR) Loop Mode Position */
#define SSC_RFMR_LOOP_Msk (_U_(0x1) << SSC_RFMR_LOOP_Pos) /**< (SSC_RFMR) Loop Mode Mask */
#define SSC_RFMR_LOOP SSC_RFMR_LOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_LOOP_Msk instead */
#define SSC_RFMR_MSBF_Pos 7 /**< (SSC_RFMR) Most Significant Bit First Position */
#define SSC_RFMR_MSBF_Msk (_U_(0x1) << SSC_RFMR_MSBF_Pos) /**< (SSC_RFMR) Most Significant Bit First Mask */
#define SSC_RFMR_MSBF SSC_RFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_MSBF_Msk instead */
#define SSC_RFMR_DATNB_Pos 8 /**< (SSC_RFMR) Data Number per Frame Position */
#define SSC_RFMR_DATNB_Msk (_U_(0xF) << SSC_RFMR_DATNB_Pos) /**< (SSC_RFMR) Data Number per Frame Mask */
#define SSC_RFMR_DATNB(value) (SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))
#define SSC_RFMR_FSLEN_Pos 16 /**< (SSC_RFMR) Receive Frame Sync Length Position */
#define SSC_RFMR_FSLEN_Msk (_U_(0xF) << SSC_RFMR_FSLEN_Pos) /**< (SSC_RFMR) Receive Frame Sync Length Mask */
#define SSC_RFMR_FSLEN(value) (SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))
#define SSC_RFMR_FSOS_Pos 20 /**< (SSC_RFMR) Receive Frame Sync Output Selection Position */
#define SSC_RFMR_FSOS_Msk (_U_(0x7) << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Receive Frame Sync Output Selection Mask */
#define SSC_RFMR_FSOS(value) (SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))
#define SSC_RFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_RFMR) None, RF pin is an input */
#define SSC_RFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Pulse, RF pin is an output */
#define SSC_RFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_RFMR) Positive Pulse, RF pin is an output */
#define SSC_RFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output */
#define SSC_RFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output */
#define SSC_RFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */
#define SSC_RFMR_FSOS_NONE (SSC_RFMR_FSOS_NONE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) None, RF pin is an input Position */
#define SSC_RFMR_FSOS_NEGATIVE (SSC_RFMR_FSOS_NEGATIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Negative Pulse, RF pin is an output Position */
#define SSC_RFMR_FSOS_POSITIVE (SSC_RFMR_FSOS_POSITIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Positive Pulse, RF pin is an output Position */
#define SSC_RFMR_FSOS_LOW (SSC_RFMR_FSOS_LOW_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output Position */
#define SSC_RFMR_FSOS_HIGH (SSC_RFMR_FSOS_HIGH_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output Position */
#define SSC_RFMR_FSOS_TOGGLING (SSC_RFMR_FSOS_TOGGLING_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output Position */
#define SSC_RFMR_FSEDGE_Pos 24 /**< (SSC_RFMR) Frame Sync Edge Detection Position */
#define SSC_RFMR_FSEDGE_Msk (_U_(0x1) << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Frame Sync Edge Detection Mask */
#define SSC_RFMR_FSEDGE SSC_RFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_FSEDGE_Msk instead */
#define SSC_RFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_RFMR) Positive Edge Detection */
#define SSC_RFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Edge Detection */
#define SSC_RFMR_FSEDGE_POSITIVE (SSC_RFMR_FSEDGE_POSITIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Positive Edge Detection Position */
#define SSC_RFMR_FSEDGE_NEGATIVE (SSC_RFMR_FSEDGE_NEGATIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Negative Edge Detection Position */
#define SSC_RFMR_FSLEN_EXT_Pos 28 /**< (SSC_RFMR) FSLEN Field Extension Position */
#define SSC_RFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_RFMR_FSLEN_EXT_Pos) /**< (SSC_RFMR) FSLEN Field Extension Mask */
#define SSC_RFMR_FSLEN_EXT(value) (SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))
#define SSC_RFMR_MASK _U_(0xF17F0FBF) /**< \deprecated (SSC_RFMR) Register MASK (Use SSC_RFMR_Msk instead) */
#define SSC_RFMR_Msk _U_(0xF17F0FBF) /**< (SSC_RFMR) Register Mask */
/* -------- SSC_TCMR : (SSC Offset: 0x18) (R/W 32) Transmit Clock Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CKS:2; /**< bit: 0..1 Transmit Clock Selection */
uint32_t CKO:3; /**< bit: 2..4 Transmit Clock Output Mode Selection */
uint32_t CKI:1; /**< bit: 5 Transmit Clock Inversion */
uint32_t CKG:2; /**< bit: 6..7 Transmit Clock Gating Selection */
uint32_t START:4; /**< bit: 8..11 Transmit Start Selection */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t STTDLY:8; /**< bit: 16..23 Transmit Start Delay */
uint32_t PERIOD:8; /**< bit: 24..31 Transmit Period Divider Selection */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_TCMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_TCMR_OFFSET (0x18) /**< (SSC_TCMR) Transmit Clock Mode Register Offset */
#define SSC_TCMR_CKS_Pos 0 /**< (SSC_TCMR) Transmit Clock Selection Position */
#define SSC_TCMR_CKS_Msk (_U_(0x3) << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Transmit Clock Selection Mask */
#define SSC_TCMR_CKS(value) (SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))
#define SSC_TCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_TCMR) Divided Clock */
#define SSC_TCMR_CKS_RK_Val _U_(0x1) /**< (SSC_TCMR) RK Clock signal */
#define SSC_TCMR_CKS_TK_Val _U_(0x2) /**< (SSC_TCMR) TK pin */
#define SSC_TCMR_CKS_MCK (SSC_TCMR_CKS_MCK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Divided Clock Position */
#define SSC_TCMR_CKS_RK (SSC_TCMR_CKS_RK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) RK Clock signal Position */
#define SSC_TCMR_CKS_TK (SSC_TCMR_CKS_TK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) TK pin Position */
#define SSC_TCMR_CKO_Pos 2 /**< (SSC_TCMR) Transmit Clock Output Mode Selection Position */
#define SSC_TCMR_CKO_Msk (_U_(0x7) << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Mask */
#define SSC_TCMR_CKO(value) (SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))
#define SSC_TCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_TCMR) None, TK pin is an input */
#define SSC_TCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */
#define SSC_TCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */
#define SSC_TCMR_CKO_NONE (SSC_TCMR_CKO_NONE_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) None, TK pin is an input Position */
#define SSC_TCMR_CKO_CONTINUOUS (SSC_TCMR_CKO_CONTINUOUS_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output Position */
#define SSC_TCMR_CKO_TRANSFER (SSC_TCMR_CKO_TRANSFER_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output Position */
#define SSC_TCMR_CKI_Pos 5 /**< (SSC_TCMR) Transmit Clock Inversion Position */
#define SSC_TCMR_CKI_Msk (_U_(0x1) << SSC_TCMR_CKI_Pos) /**< (SSC_TCMR) Transmit Clock Inversion Mask */
#define SSC_TCMR_CKI SSC_TCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TCMR_CKI_Msk instead */
#define SSC_TCMR_CKG_Pos 6 /**< (SSC_TCMR) Transmit Clock Gating Selection Position */
#define SSC_TCMR_CKG_Msk (_U_(0x3) << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock Gating Selection Mask */
#define SSC_TCMR_CKG(value) (SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))
#define SSC_TCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) None */
#define SSC_TCMR_CKG_EN_TF_LOW_Val _U_(0x1) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low */
#define SSC_TCMR_CKG_EN_TF_HIGH_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock enabled only if TF High */
#define SSC_TCMR_CKG_CONTINUOUS (SSC_TCMR_CKG_CONTINUOUS_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) None Position */
#define SSC_TCMR_CKG_EN_TF_LOW (SSC_TCMR_CKG_EN_TF_LOW_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low Position */
#define SSC_TCMR_CKG_EN_TF_HIGH (SSC_TCMR_CKG_EN_TF_HIGH_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF High Position */
#define SSC_TCMR_START_Pos 8 /**< (SSC_TCMR) Transmit Start Selection Position */
#define SSC_TCMR_START_Msk (_U_(0xF) << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Transmit Start Selection Mask */
#define SSC_TCMR_START(value) (SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))
#define SSC_TCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */
#define SSC_TCMR_START_RECEIVE_Val _U_(0x1) /**< (SSC_TCMR) Receive start */
#define SSC_TCMR_START_TF_LOW_Val _U_(0x2) /**< (SSC_TCMR) Detection of a low level on TF signal */
#define SSC_TCMR_START_TF_HIGH_Val _U_(0x3) /**< (SSC_TCMR) Detection of a high level on TF signal */
#define SSC_TCMR_START_TF_FALLING_Val _U_(0x4) /**< (SSC_TCMR) Detection of a falling edge on TF signal */
#define SSC_TCMR_START_TF_RISING_Val _U_(0x5) /**< (SSC_TCMR) Detection of a rising edge on TF signal */
#define SSC_TCMR_START_TF_LEVEL_Val _U_(0x6) /**< (SSC_TCMR) Detection of any level change on TF signal */
#define SSC_TCMR_START_TF_EDGE_Val _U_(0x7) /**< (SSC_TCMR) Detection of any edge on TF signal */
#define SSC_TCMR_START_CONTINUOUS (SSC_TCMR_START_CONTINUOUS_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data Position */
#define SSC_TCMR_START_RECEIVE (SSC_TCMR_START_RECEIVE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Receive start Position */
#define SSC_TCMR_START_TF_LOW (SSC_TCMR_START_TF_LOW_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a low level on TF signal Position */
#define SSC_TCMR_START_TF_HIGH (SSC_TCMR_START_TF_HIGH_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a high level on TF signal Position */
#define SSC_TCMR_START_TF_FALLING (SSC_TCMR_START_TF_FALLING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a falling edge on TF signal Position */
#define SSC_TCMR_START_TF_RISING (SSC_TCMR_START_TF_RISING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a rising edge on TF signal Position */
#define SSC_TCMR_START_TF_LEVEL (SSC_TCMR_START_TF_LEVEL_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any level change on TF signal Position */
#define SSC_TCMR_START_TF_EDGE (SSC_TCMR_START_TF_EDGE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any edge on TF signal Position */
#define SSC_TCMR_STTDLY_Pos 16 /**< (SSC_TCMR) Transmit Start Delay Position */
#define SSC_TCMR_STTDLY_Msk (_U_(0xFF) << SSC_TCMR_STTDLY_Pos) /**< (SSC_TCMR) Transmit Start Delay Mask */
#define SSC_TCMR_STTDLY(value) (SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))
#define SSC_TCMR_PERIOD_Pos 24 /**< (SSC_TCMR) Transmit Period Divider Selection Position */
#define SSC_TCMR_PERIOD_Msk (_U_(0xFF) << SSC_TCMR_PERIOD_Pos) /**< (SSC_TCMR) Transmit Period Divider Selection Mask */
#define SSC_TCMR_PERIOD(value) (SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))
#define SSC_TCMR_MASK _U_(0xFFFF0FFF) /**< \deprecated (SSC_TCMR) Register MASK (Use SSC_TCMR_Msk instead) */
#define SSC_TCMR_Msk _U_(0xFFFF0FFF) /**< (SSC_TCMR) Register Mask */
/* -------- SSC_TFMR : (SSC Offset: 0x1c) (R/W 32) Transmit Frame Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATLEN:5; /**< bit: 0..4 Data Length */
uint32_t DATDEF:1; /**< bit: 5 Data Default Value */
uint32_t :1; /**< bit: 6 Reserved */
uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */
uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t FSLEN:4; /**< bit: 16..19 Transmit Frame Sync Length */
uint32_t FSOS:3; /**< bit: 20..22 Transmit Frame Sync Output Selection */
uint32_t FSDEN:1; /**< bit: 23 Frame Sync Data Enable */
uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */
uint32_t :3; /**< bit: 25..27 Reserved */
uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_TFMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_TFMR_OFFSET (0x1C) /**< (SSC_TFMR) Transmit Frame Mode Register Offset */
#define SSC_TFMR_DATLEN_Pos 0 /**< (SSC_TFMR) Data Length Position */
#define SSC_TFMR_DATLEN_Msk (_U_(0x1F) << SSC_TFMR_DATLEN_Pos) /**< (SSC_TFMR) Data Length Mask */
#define SSC_TFMR_DATLEN(value) (SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))
#define SSC_TFMR_DATDEF_Pos 5 /**< (SSC_TFMR) Data Default Value Position */
#define SSC_TFMR_DATDEF_Msk (_U_(0x1) << SSC_TFMR_DATDEF_Pos) /**< (SSC_TFMR) Data Default Value Mask */
#define SSC_TFMR_DATDEF SSC_TFMR_DATDEF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_DATDEF_Msk instead */
#define SSC_TFMR_MSBF_Pos 7 /**< (SSC_TFMR) Most Significant Bit First Position */
#define SSC_TFMR_MSBF_Msk (_U_(0x1) << SSC_TFMR_MSBF_Pos) /**< (SSC_TFMR) Most Significant Bit First Mask */
#define SSC_TFMR_MSBF SSC_TFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_MSBF_Msk instead */
#define SSC_TFMR_DATNB_Pos 8 /**< (SSC_TFMR) Data Number per Frame Position */
#define SSC_TFMR_DATNB_Msk (_U_(0xF) << SSC_TFMR_DATNB_Pos) /**< (SSC_TFMR) Data Number per Frame Mask */
#define SSC_TFMR_DATNB(value) (SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))
#define SSC_TFMR_FSLEN_Pos 16 /**< (SSC_TFMR) Transmit Frame Sync Length Position */
#define SSC_TFMR_FSLEN_Msk (_U_(0xF) << SSC_TFMR_FSLEN_Pos) /**< (SSC_TFMR) Transmit Frame Sync Length Mask */
#define SSC_TFMR_FSLEN(value) (SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))
#define SSC_TFMR_FSOS_Pos 20 /**< (SSC_TFMR) Transmit Frame Sync Output Selection Position */
#define SSC_TFMR_FSOS_Msk (_U_(0x7) << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Mask */
#define SSC_TFMR_FSOS(value) (SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))
#define SSC_TFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_TFMR) None, TF pin is an input */
#define SSC_TFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Pulse, TF pin is an output */
#define SSC_TFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_TFMR) Positive Pulse, TF pin is an output */
#define SSC_TFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_TFMR) Driven Low during data transfer */
#define SSC_TFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_TFMR) Driven High during data transfer */
#define SSC_TFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_TFMR) Toggling at each start of data transfer */
#define SSC_TFMR_FSOS_NONE (SSC_TFMR_FSOS_NONE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) None, TF pin is an input Position */
#define SSC_TFMR_FSOS_NEGATIVE (SSC_TFMR_FSOS_NEGATIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Negative Pulse, TF pin is an output Position */
#define SSC_TFMR_FSOS_POSITIVE (SSC_TFMR_FSOS_POSITIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Positive Pulse, TF pin is an output Position */
#define SSC_TFMR_FSOS_LOW (SSC_TFMR_FSOS_LOW_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven Low during data transfer Position */
#define SSC_TFMR_FSOS_HIGH (SSC_TFMR_FSOS_HIGH_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven High during data transfer Position */
#define SSC_TFMR_FSOS_TOGGLING (SSC_TFMR_FSOS_TOGGLING_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Toggling at each start of data transfer Position */
#define SSC_TFMR_FSDEN_Pos 23 /**< (SSC_TFMR) Frame Sync Data Enable Position */
#define SSC_TFMR_FSDEN_Msk (_U_(0x1) << SSC_TFMR_FSDEN_Pos) /**< (SSC_TFMR) Frame Sync Data Enable Mask */
#define SSC_TFMR_FSDEN SSC_TFMR_FSDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSDEN_Msk instead */
#define SSC_TFMR_FSEDGE_Pos 24 /**< (SSC_TFMR) Frame Sync Edge Detection Position */
#define SSC_TFMR_FSEDGE_Msk (_U_(0x1) << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Frame Sync Edge Detection Mask */
#define SSC_TFMR_FSEDGE SSC_TFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSEDGE_Msk instead */
#define SSC_TFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_TFMR) Positive Edge Detection */
#define SSC_TFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Edge Detection */
#define SSC_TFMR_FSEDGE_POSITIVE (SSC_TFMR_FSEDGE_POSITIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Positive Edge Detection Position */
#define SSC_TFMR_FSEDGE_NEGATIVE (SSC_TFMR_FSEDGE_NEGATIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Negative Edge Detection Position */
#define SSC_TFMR_FSLEN_EXT_Pos 28 /**< (SSC_TFMR) FSLEN Field Extension Position */
#define SSC_TFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_TFMR_FSLEN_EXT_Pos) /**< (SSC_TFMR) FSLEN Field Extension Mask */
#define SSC_TFMR_FSLEN_EXT(value) (SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))
#define SSC_TFMR_MASK _U_(0xF1FF0FBF) /**< \deprecated (SSC_TFMR) Register MASK (Use SSC_TFMR_Msk instead) */
#define SSC_TFMR_Msk _U_(0xF1FF0FBF) /**< (SSC_TFMR) Register Mask */
/* -------- SSC_RHR : (SSC Offset: 0x20) (R/ 32) Receive Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDAT:32; /**< bit: 0..31 Receive Data */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RHR_OFFSET (0x20) /**< (SSC_RHR) Receive Holding Register Offset */
#define SSC_RHR_RDAT_Pos 0 /**< (SSC_RHR) Receive Data Position */
#define SSC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << SSC_RHR_RDAT_Pos) /**< (SSC_RHR) Receive Data Mask */
#define SSC_RHR_RDAT(value) (SSC_RHR_RDAT_Msk & ((value) << SSC_RHR_RDAT_Pos))
#define SSC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_RHR) Register MASK (Use SSC_RHR_Msk instead) */
#define SSC_RHR_Msk _U_(0xFFFFFFFF) /**< (SSC_RHR) Register Mask */
/* -------- SSC_THR : (SSC Offset: 0x24) (/W 32) Transmit Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TDAT:32; /**< bit: 0..31 Transmit Data */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_THR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_THR_OFFSET (0x24) /**< (SSC_THR) Transmit Holding Register Offset */
#define SSC_THR_TDAT_Pos 0 /**< (SSC_THR) Transmit Data Position */
#define SSC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << SSC_THR_TDAT_Pos) /**< (SSC_THR) Transmit Data Mask */
#define SSC_THR_TDAT(value) (SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))
#define SSC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_THR) Register MASK (Use SSC_THR_Msk instead) */
#define SSC_THR_Msk _U_(0xFFFFFFFF) /**< (SSC_THR) Register Mask */
/* -------- SSC_RSHR : (SSC Offset: 0x30) (R/ 32) Receive Sync. Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RSDAT:16; /**< bit: 0..15 Receive Synchronization Data */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RSHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RSHR_OFFSET (0x30) /**< (SSC_RSHR) Receive Sync. Holding Register Offset */
#define SSC_RSHR_RSDAT_Pos 0 /**< (SSC_RSHR) Receive Synchronization Data Position */
#define SSC_RSHR_RSDAT_Msk (_U_(0xFFFF) << SSC_RSHR_RSDAT_Pos) /**< (SSC_RSHR) Receive Synchronization Data Mask */
#define SSC_RSHR_RSDAT(value) (SSC_RSHR_RSDAT_Msk & ((value) << SSC_RSHR_RSDAT_Pos))
#define SSC_RSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_RSHR) Register MASK (Use SSC_RSHR_Msk instead) */
#define SSC_RSHR_Msk _U_(0xFFFF) /**< (SSC_RSHR) Register Mask */
/* -------- SSC_TSHR : (SSC Offset: 0x34) (R/W 32) Transmit Sync. Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TSDAT:16; /**< bit: 0..15 Transmit Synchronization Data */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_TSHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_TSHR_OFFSET (0x34) /**< (SSC_TSHR) Transmit Sync. Holding Register Offset */
#define SSC_TSHR_TSDAT_Pos 0 /**< (SSC_TSHR) Transmit Synchronization Data Position */
#define SSC_TSHR_TSDAT_Msk (_U_(0xFFFF) << SSC_TSHR_TSDAT_Pos) /**< (SSC_TSHR) Transmit Synchronization Data Mask */
#define SSC_TSHR_TSDAT(value) (SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))
#define SSC_TSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_TSHR) Register MASK (Use SSC_TSHR_Msk instead) */
#define SSC_TSHR_Msk _U_(0xFFFF) /**< (SSC_TSHR) Register Mask */
/* -------- SSC_RC0R : (SSC Offset: 0x38) (R/W 32) Receive Compare 0 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CP0:16; /**< bit: 0..15 Receive Compare Data 0 */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RC0R_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RC0R_OFFSET (0x38) /**< (SSC_RC0R) Receive Compare 0 Register Offset */
#define SSC_RC0R_CP0_Pos 0 /**< (SSC_RC0R) Receive Compare Data 0 Position */
#define SSC_RC0R_CP0_Msk (_U_(0xFFFF) << SSC_RC0R_CP0_Pos) /**< (SSC_RC0R) Receive Compare Data 0 Mask */
#define SSC_RC0R_CP0(value) (SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))
#define SSC_RC0R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC0R) Register MASK (Use SSC_RC0R_Msk instead) */
#define SSC_RC0R_Msk _U_(0xFFFF) /**< (SSC_RC0R) Register Mask */
/* -------- SSC_RC1R : (SSC Offset: 0x3c) (R/W 32) Receive Compare 1 Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CP1:16; /**< bit: 0..15 Receive Compare Data 1 */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_RC1R_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_RC1R_OFFSET (0x3C) /**< (SSC_RC1R) Receive Compare 1 Register Offset */
#define SSC_RC1R_CP1_Pos 0 /**< (SSC_RC1R) Receive Compare Data 1 Position */
#define SSC_RC1R_CP1_Msk (_U_(0xFFFF) << SSC_RC1R_CP1_Pos) /**< (SSC_RC1R) Receive Compare Data 1 Mask */
#define SSC_RC1R_CP1(value) (SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))
#define SSC_RC1R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC1R) Register MASK (Use SSC_RC1R_Msk instead) */
#define SSC_RC1R_Msk _U_(0xFFFF) /**< (SSC_RC1R) Register Mask */
/* -------- SSC_SR : (SSC Offset: 0x40) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY:1; /**< bit: 0 Transmit Ready */
uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t RXRDY:1; /**< bit: 4 Receive Ready */
uint32_t OVRUN:1; /**< bit: 5 Receive Overrun */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t CP0:1; /**< bit: 8 Compare 0 */
uint32_t CP1:1; /**< bit: 9 Compare 1 */
uint32_t TXSYN:1; /**< bit: 10 Transmit Sync */
uint32_t RXSYN:1; /**< bit: 11 Receive Sync */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t TXEN:1; /**< bit: 16 Transmit Enable */
uint32_t RXEN:1; /**< bit: 17 Receive Enable */
uint32_t :14; /**< bit: 18..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :8; /**< bit: 0..7 Reserved */
uint32_t CP:2; /**< bit: 8..9 Compare x */
uint32_t :22; /**< bit: 10..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SSC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_SR_OFFSET (0x40) /**< (SSC_SR) Status Register Offset */
#define SSC_SR_TXRDY_Pos 0 /**< (SSC_SR) Transmit Ready Position */
#define SSC_SR_TXRDY_Msk (_U_(0x1) << SSC_SR_TXRDY_Pos) /**< (SSC_SR) Transmit Ready Mask */
#define SSC_SR_TXRDY SSC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXRDY_Msk instead */
#define SSC_SR_TXEMPTY_Pos 1 /**< (SSC_SR) Transmit Empty Position */
#define SSC_SR_TXEMPTY_Msk (_U_(0x1) << SSC_SR_TXEMPTY_Pos) /**< (SSC_SR) Transmit Empty Mask */
#define SSC_SR_TXEMPTY SSC_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEMPTY_Msk instead */
#define SSC_SR_RXRDY_Pos 4 /**< (SSC_SR) Receive Ready Position */
#define SSC_SR_RXRDY_Msk (_U_(0x1) << SSC_SR_RXRDY_Pos) /**< (SSC_SR) Receive Ready Mask */
#define SSC_SR_RXRDY SSC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXRDY_Msk instead */
#define SSC_SR_OVRUN_Pos 5 /**< (SSC_SR) Receive Overrun Position */
#define SSC_SR_OVRUN_Msk (_U_(0x1) << SSC_SR_OVRUN_Pos) /**< (SSC_SR) Receive Overrun Mask */
#define SSC_SR_OVRUN SSC_SR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_OVRUN_Msk instead */
#define SSC_SR_CP0_Pos 8 /**< (SSC_SR) Compare 0 Position */
#define SSC_SR_CP0_Msk (_U_(0x1) << SSC_SR_CP0_Pos) /**< (SSC_SR) Compare 0 Mask */
#define SSC_SR_CP0 SSC_SR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP0_Msk instead */
#define SSC_SR_CP1_Pos 9 /**< (SSC_SR) Compare 1 Position */
#define SSC_SR_CP1_Msk (_U_(0x1) << SSC_SR_CP1_Pos) /**< (SSC_SR) Compare 1 Mask */
#define SSC_SR_CP1 SSC_SR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP1_Msk instead */
#define SSC_SR_TXSYN_Pos 10 /**< (SSC_SR) Transmit Sync Position */
#define SSC_SR_TXSYN_Msk (_U_(0x1) << SSC_SR_TXSYN_Pos) /**< (SSC_SR) Transmit Sync Mask */
#define SSC_SR_TXSYN SSC_SR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXSYN_Msk instead */
#define SSC_SR_RXSYN_Pos 11 /**< (SSC_SR) Receive Sync Position */
#define SSC_SR_RXSYN_Msk (_U_(0x1) << SSC_SR_RXSYN_Pos) /**< (SSC_SR) Receive Sync Mask */
#define SSC_SR_RXSYN SSC_SR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXSYN_Msk instead */
#define SSC_SR_TXEN_Pos 16 /**< (SSC_SR) Transmit Enable Position */
#define SSC_SR_TXEN_Msk (_U_(0x1) << SSC_SR_TXEN_Pos) /**< (SSC_SR) Transmit Enable Mask */
#define SSC_SR_TXEN SSC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEN_Msk instead */
#define SSC_SR_RXEN_Pos 17 /**< (SSC_SR) Receive Enable Position */
#define SSC_SR_RXEN_Msk (_U_(0x1) << SSC_SR_RXEN_Pos) /**< (SSC_SR) Receive Enable Mask */
#define SSC_SR_RXEN SSC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXEN_Msk instead */
#define SSC_SR_MASK _U_(0x30F33) /**< \deprecated (SSC_SR) Register MASK (Use SSC_SR_Msk instead) */
#define SSC_SR_Msk _U_(0x30F33) /**< (SSC_SR) Register Mask */
#define SSC_SR_CP_Pos 8 /**< (SSC_SR Position) Compare x */
#define SSC_SR_CP_Msk (_U_(0x3) << SSC_SR_CP_Pos) /**< (SSC_SR Mask) CP */
#define SSC_SR_CP(value) (SSC_SR_CP_Msk & ((value) << SSC_SR_CP_Pos))
/* -------- SSC_IER : (SSC Offset: 0x44) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Enable */
uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Enable */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Enable */
uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Enable */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Enable */
uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Enable */
uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */
uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :8; /**< bit: 0..7 Reserved */
uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Enable */
uint32_t :22; /**< bit: 10..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SSC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_IER_OFFSET (0x44) /**< (SSC_IER) Interrupt Enable Register Offset */
#define SSC_IER_TXRDY_Pos 0 /**< (SSC_IER) Transmit Ready Interrupt Enable Position */
#define SSC_IER_TXRDY_Msk (_U_(0x1) << SSC_IER_TXRDY_Pos) /**< (SSC_IER) Transmit Ready Interrupt Enable Mask */
#define SSC_IER_TXRDY SSC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXRDY_Msk instead */
#define SSC_IER_TXEMPTY_Pos 1 /**< (SSC_IER) Transmit Empty Interrupt Enable Position */
#define SSC_IER_TXEMPTY_Msk (_U_(0x1) << SSC_IER_TXEMPTY_Pos) /**< (SSC_IER) Transmit Empty Interrupt Enable Mask */
#define SSC_IER_TXEMPTY SSC_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXEMPTY_Msk instead */
#define SSC_IER_RXRDY_Pos 4 /**< (SSC_IER) Receive Ready Interrupt Enable Position */
#define SSC_IER_RXRDY_Msk (_U_(0x1) << SSC_IER_RXRDY_Pos) /**< (SSC_IER) Receive Ready Interrupt Enable Mask */
#define SSC_IER_RXRDY SSC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXRDY_Msk instead */
#define SSC_IER_OVRUN_Pos 5 /**< (SSC_IER) Receive Overrun Interrupt Enable Position */
#define SSC_IER_OVRUN_Msk (_U_(0x1) << SSC_IER_OVRUN_Pos) /**< (SSC_IER) Receive Overrun Interrupt Enable Mask */
#define SSC_IER_OVRUN SSC_IER_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_OVRUN_Msk instead */
#define SSC_IER_CP0_Pos 8 /**< (SSC_IER) Compare 0 Interrupt Enable Position */
#define SSC_IER_CP0_Msk (_U_(0x1) << SSC_IER_CP0_Pos) /**< (SSC_IER) Compare 0 Interrupt Enable Mask */
#define SSC_IER_CP0 SSC_IER_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP0_Msk instead */
#define SSC_IER_CP1_Pos 9 /**< (SSC_IER) Compare 1 Interrupt Enable Position */
#define SSC_IER_CP1_Msk (_U_(0x1) << SSC_IER_CP1_Pos) /**< (SSC_IER) Compare 1 Interrupt Enable Mask */
#define SSC_IER_CP1 SSC_IER_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP1_Msk instead */
#define SSC_IER_TXSYN_Pos 10 /**< (SSC_IER) Tx Sync Interrupt Enable Position */
#define SSC_IER_TXSYN_Msk (_U_(0x1) << SSC_IER_TXSYN_Pos) /**< (SSC_IER) Tx Sync Interrupt Enable Mask */
#define SSC_IER_TXSYN SSC_IER_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXSYN_Msk instead */
#define SSC_IER_RXSYN_Pos 11 /**< (SSC_IER) Rx Sync Interrupt Enable Position */
#define SSC_IER_RXSYN_Msk (_U_(0x1) << SSC_IER_RXSYN_Pos) /**< (SSC_IER) Rx Sync Interrupt Enable Mask */
#define SSC_IER_RXSYN SSC_IER_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXSYN_Msk instead */
#define SSC_IER_MASK _U_(0xF33) /**< \deprecated (SSC_IER) Register MASK (Use SSC_IER_Msk instead) */
#define SSC_IER_Msk _U_(0xF33) /**< (SSC_IER) Register Mask */
#define SSC_IER_CP_Pos 8 /**< (SSC_IER Position) Compare x Interrupt Enable */
#define SSC_IER_CP_Msk (_U_(0x3) << SSC_IER_CP_Pos) /**< (SSC_IER Mask) CP */
#define SSC_IER_CP(value) (SSC_IER_CP_Msk & ((value) << SSC_IER_CP_Pos))
/* -------- SSC_IDR : (SSC Offset: 0x48) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Disable */
uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Disable */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Disable */
uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Disable */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Disable */
uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Disable */
uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */
uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :8; /**< bit: 0..7 Reserved */
uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Disable */
uint32_t :22; /**< bit: 10..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SSC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_IDR_OFFSET (0x48) /**< (SSC_IDR) Interrupt Disable Register Offset */
#define SSC_IDR_TXRDY_Pos 0 /**< (SSC_IDR) Transmit Ready Interrupt Disable Position */
#define SSC_IDR_TXRDY_Msk (_U_(0x1) << SSC_IDR_TXRDY_Pos) /**< (SSC_IDR) Transmit Ready Interrupt Disable Mask */
#define SSC_IDR_TXRDY SSC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXRDY_Msk instead */
#define SSC_IDR_TXEMPTY_Pos 1 /**< (SSC_IDR) Transmit Empty Interrupt Disable Position */
#define SSC_IDR_TXEMPTY_Msk (_U_(0x1) << SSC_IDR_TXEMPTY_Pos) /**< (SSC_IDR) Transmit Empty Interrupt Disable Mask */
#define SSC_IDR_TXEMPTY SSC_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXEMPTY_Msk instead */
#define SSC_IDR_RXRDY_Pos 4 /**< (SSC_IDR) Receive Ready Interrupt Disable Position */
#define SSC_IDR_RXRDY_Msk (_U_(0x1) << SSC_IDR_RXRDY_Pos) /**< (SSC_IDR) Receive Ready Interrupt Disable Mask */
#define SSC_IDR_RXRDY SSC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXRDY_Msk instead */
#define SSC_IDR_OVRUN_Pos 5 /**< (SSC_IDR) Receive Overrun Interrupt Disable Position */
#define SSC_IDR_OVRUN_Msk (_U_(0x1) << SSC_IDR_OVRUN_Pos) /**< (SSC_IDR) Receive Overrun Interrupt Disable Mask */
#define SSC_IDR_OVRUN SSC_IDR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_OVRUN_Msk instead */
#define SSC_IDR_CP0_Pos 8 /**< (SSC_IDR) Compare 0 Interrupt Disable Position */
#define SSC_IDR_CP0_Msk (_U_(0x1) << SSC_IDR_CP0_Pos) /**< (SSC_IDR) Compare 0 Interrupt Disable Mask */
#define SSC_IDR_CP0 SSC_IDR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP0_Msk instead */
#define SSC_IDR_CP1_Pos 9 /**< (SSC_IDR) Compare 1 Interrupt Disable Position */
#define SSC_IDR_CP1_Msk (_U_(0x1) << SSC_IDR_CP1_Pos) /**< (SSC_IDR) Compare 1 Interrupt Disable Mask */
#define SSC_IDR_CP1 SSC_IDR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP1_Msk instead */
#define SSC_IDR_TXSYN_Pos 10 /**< (SSC_IDR) Tx Sync Interrupt Enable Position */
#define SSC_IDR_TXSYN_Msk (_U_(0x1) << SSC_IDR_TXSYN_Pos) /**< (SSC_IDR) Tx Sync Interrupt Enable Mask */
#define SSC_IDR_TXSYN SSC_IDR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXSYN_Msk instead */
#define SSC_IDR_RXSYN_Pos 11 /**< (SSC_IDR) Rx Sync Interrupt Enable Position */
#define SSC_IDR_RXSYN_Msk (_U_(0x1) << SSC_IDR_RXSYN_Pos) /**< (SSC_IDR) Rx Sync Interrupt Enable Mask */
#define SSC_IDR_RXSYN SSC_IDR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXSYN_Msk instead */
#define SSC_IDR_MASK _U_(0xF33) /**< \deprecated (SSC_IDR) Register MASK (Use SSC_IDR_Msk instead) */
#define SSC_IDR_Msk _U_(0xF33) /**< (SSC_IDR) Register Mask */
#define SSC_IDR_CP_Pos 8 /**< (SSC_IDR Position) Compare x Interrupt Disable */
#define SSC_IDR_CP_Msk (_U_(0x3) << SSC_IDR_CP_Pos) /**< (SSC_IDR Mask) CP */
#define SSC_IDR_CP(value) (SSC_IDR_CP_Msk & ((value) << SSC_IDR_CP_Pos))
/* -------- SSC_IMR : (SSC Offset: 0x4c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Mask */
uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Mask */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Mask */
uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Mask */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Mask */
uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Mask */
uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Mask */
uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Mask */
uint32_t :20; /**< bit: 12..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :8; /**< bit: 0..7 Reserved */
uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Mask */
uint32_t :22; /**< bit: 10..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SSC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_IMR_OFFSET (0x4C) /**< (SSC_IMR) Interrupt Mask Register Offset */
#define SSC_IMR_TXRDY_Pos 0 /**< (SSC_IMR) Transmit Ready Interrupt Mask Position */
#define SSC_IMR_TXRDY_Msk (_U_(0x1) << SSC_IMR_TXRDY_Pos) /**< (SSC_IMR) Transmit Ready Interrupt Mask Mask */
#define SSC_IMR_TXRDY SSC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXRDY_Msk instead */
#define SSC_IMR_TXEMPTY_Pos 1 /**< (SSC_IMR) Transmit Empty Interrupt Mask Position */
#define SSC_IMR_TXEMPTY_Msk (_U_(0x1) << SSC_IMR_TXEMPTY_Pos) /**< (SSC_IMR) Transmit Empty Interrupt Mask Mask */
#define SSC_IMR_TXEMPTY SSC_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXEMPTY_Msk instead */
#define SSC_IMR_RXRDY_Pos 4 /**< (SSC_IMR) Receive Ready Interrupt Mask Position */
#define SSC_IMR_RXRDY_Msk (_U_(0x1) << SSC_IMR_RXRDY_Pos) /**< (SSC_IMR) Receive Ready Interrupt Mask Mask */
#define SSC_IMR_RXRDY SSC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXRDY_Msk instead */
#define SSC_IMR_OVRUN_Pos 5 /**< (SSC_IMR) Receive Overrun Interrupt Mask Position */
#define SSC_IMR_OVRUN_Msk (_U_(0x1) << SSC_IMR_OVRUN_Pos) /**< (SSC_IMR) Receive Overrun Interrupt Mask Mask */
#define SSC_IMR_OVRUN SSC_IMR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_OVRUN_Msk instead */
#define SSC_IMR_CP0_Pos 8 /**< (SSC_IMR) Compare 0 Interrupt Mask Position */
#define SSC_IMR_CP0_Msk (_U_(0x1) << SSC_IMR_CP0_Pos) /**< (SSC_IMR) Compare 0 Interrupt Mask Mask */
#define SSC_IMR_CP0 SSC_IMR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP0_Msk instead */
#define SSC_IMR_CP1_Pos 9 /**< (SSC_IMR) Compare 1 Interrupt Mask Position */
#define SSC_IMR_CP1_Msk (_U_(0x1) << SSC_IMR_CP1_Pos) /**< (SSC_IMR) Compare 1 Interrupt Mask Mask */
#define SSC_IMR_CP1 SSC_IMR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP1_Msk instead */
#define SSC_IMR_TXSYN_Pos 10 /**< (SSC_IMR) Tx Sync Interrupt Mask Position */
#define SSC_IMR_TXSYN_Msk (_U_(0x1) << SSC_IMR_TXSYN_Pos) /**< (SSC_IMR) Tx Sync Interrupt Mask Mask */
#define SSC_IMR_TXSYN SSC_IMR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXSYN_Msk instead */
#define SSC_IMR_RXSYN_Pos 11 /**< (SSC_IMR) Rx Sync Interrupt Mask Position */
#define SSC_IMR_RXSYN_Msk (_U_(0x1) << SSC_IMR_RXSYN_Pos) /**< (SSC_IMR) Rx Sync Interrupt Mask Mask */
#define SSC_IMR_RXSYN SSC_IMR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXSYN_Msk instead */
#define SSC_IMR_MASK _U_(0xF33) /**< \deprecated (SSC_IMR) Register MASK (Use SSC_IMR_Msk instead) */
#define SSC_IMR_Msk _U_(0xF33) /**< (SSC_IMR) Register Mask */
#define SSC_IMR_CP_Pos 8 /**< (SSC_IMR Position) Compare x Interrupt Mask */
#define SSC_IMR_CP_Msk (_U_(0x3) << SSC_IMR_CP_Pos) /**< (SSC_IMR Mask) CP */
#define SSC_IMR_CP(value) (SSC_IMR_CP_Msk & ((value) << SSC_IMR_CP_Pos))
/* -------- SSC_WPMR : (SSC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_WPMR_OFFSET (0xE4) /**< (SSC_WPMR) Write Protection Mode Register Offset */
#define SSC_WPMR_WPEN_Pos 0 /**< (SSC_WPMR) Write Protection Enable Position */
#define SSC_WPMR_WPEN_Msk (_U_(0x1) << SSC_WPMR_WPEN_Pos) /**< (SSC_WPMR) Write Protection Enable Mask */
#define SSC_WPMR_WPEN SSC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPMR_WPEN_Msk instead */
#define SSC_WPMR_WPKEY_Pos 8 /**< (SSC_WPMR) Write Protection Key Position */
#define SSC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Write Protection Key Mask */
#define SSC_WPMR_WPKEY(value) (SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))
#define SSC_WPMR_WPKEY_PASSWD_Val _U_(0x535343) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define SSC_WPMR_WPKEY_PASSWD (SSC_WPMR_WPKEY_PASSWD_Val << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define SSC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SSC_WPMR) Register MASK (Use SSC_WPMR_Msk instead) */
#define SSC_WPMR_Msk _U_(0xFFFFFF01) /**< (SSC_WPMR) Register Mask */
/* -------- SSC_WPSR : (SSC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:16; /**< bit: 8..23 Write Protect Violation Source */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SSC_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SSC_WPSR_OFFSET (0xE8) /**< (SSC_WPSR) Write Protection Status Register Offset */
#define SSC_WPSR_WPVS_Pos 0 /**< (SSC_WPSR) Write Protection Violation Status Position */
#define SSC_WPSR_WPVS_Msk (_U_(0x1) << SSC_WPSR_WPVS_Pos) /**< (SSC_WPSR) Write Protection Violation Status Mask */
#define SSC_WPSR_WPVS SSC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPSR_WPVS_Msk instead */
#define SSC_WPSR_WPVSRC_Pos 8 /**< (SSC_WPSR) Write Protect Violation Source Position */
#define SSC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SSC_WPSR_WPVSRC_Pos) /**< (SSC_WPSR) Write Protect Violation Source Mask */
#define SSC_WPSR_WPVSRC(value) (SSC_WPSR_WPVSRC_Msk & ((value) << SSC_WPSR_WPVSRC_Pos))
#define SSC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SSC_WPSR) Register MASK (Use SSC_WPSR_Msk instead) */
#define SSC_WPSR_Msk _U_(0xFFFF01) /**< (SSC_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief SSC hardware registers */
typedef struct {
__O uint32_t SSC_CR; /**< (SSC Offset: 0x00) Control Register */
__IO uint32_t SSC_CMR; /**< (SSC Offset: 0x04) Clock Mode Register */
RoReg8 Reserved1[0x8];
__IO uint32_t SSC_RCMR; /**< (SSC Offset: 0x10) Receive Clock Mode Register */
__IO uint32_t SSC_RFMR; /**< (SSC Offset: 0x14) Receive Frame Mode Register */
__IO uint32_t SSC_TCMR; /**< (SSC Offset: 0x18) Transmit Clock Mode Register */
__IO uint32_t SSC_TFMR; /**< (SSC Offset: 0x1C) Transmit Frame Mode Register */
__I uint32_t SSC_RHR; /**< (SSC Offset: 0x20) Receive Holding Register */
__O uint32_t SSC_THR; /**< (SSC Offset: 0x24) Transmit Holding Register */
RoReg8 Reserved2[0x8];
__I uint32_t SSC_RSHR; /**< (SSC Offset: 0x30) Receive Sync. Holding Register */
__IO uint32_t SSC_TSHR; /**< (SSC Offset: 0x34) Transmit Sync. Holding Register */
__IO uint32_t SSC_RC0R; /**< (SSC Offset: 0x38) Receive Compare 0 Register */
__IO uint32_t SSC_RC1R; /**< (SSC Offset: 0x3C) Receive Compare 1 Register */
__I uint32_t SSC_SR; /**< (SSC Offset: 0x40) Status Register */
__O uint32_t SSC_IER; /**< (SSC Offset: 0x44) Interrupt Enable Register */
__O uint32_t SSC_IDR; /**< (SSC Offset: 0x48) Interrupt Disable Register */
__I uint32_t SSC_IMR; /**< (SSC Offset: 0x4C) Interrupt Mask Register */
RoReg8 Reserved3[0x94];
__IO uint32_t SSC_WPMR; /**< (SSC Offset: 0xE4) Write Protection Mode Register */
__I uint32_t SSC_WPSR; /**< (SSC Offset: 0xE8) Write Protection Status Register */
} Ssc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief SSC hardware registers */
typedef struct {
__O SSC_CR_Type SSC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO SSC_CMR_Type SSC_CMR; /**< Offset: 0x04 (R/W 32) Clock Mode Register */
__I uint32_t Reserved1[2];
__IO SSC_RCMR_Type SSC_RCMR; /**< Offset: 0x10 (R/W 32) Receive Clock Mode Register */
__IO SSC_RFMR_Type SSC_RFMR; /**< Offset: 0x14 (R/W 32) Receive Frame Mode Register */
__IO SSC_TCMR_Type SSC_TCMR; /**< Offset: 0x18 (R/W 32) Transmit Clock Mode Register */
__IO SSC_TFMR_Type SSC_TFMR; /**< Offset: 0x1C (R/W 32) Transmit Frame Mode Register */
__I SSC_RHR_Type SSC_RHR; /**< Offset: 0x20 (R/ 32) Receive Holding Register */
__O SSC_THR_Type SSC_THR; /**< Offset: 0x24 ( /W 32) Transmit Holding Register */
__I uint32_t Reserved2[2];
__I SSC_RSHR_Type SSC_RSHR; /**< Offset: 0x30 (R/ 32) Receive Sync. Holding Register */
__IO SSC_TSHR_Type SSC_TSHR; /**< Offset: 0x34 (R/W 32) Transmit Sync. Holding Register */
__IO SSC_RC0R_Type SSC_RC0R; /**< Offset: 0x38 (R/W 32) Receive Compare 0 Register */
__IO SSC_RC1R_Type SSC_RC1R; /**< Offset: 0x3C (R/W 32) Receive Compare 1 Register */
__I SSC_SR_Type SSC_SR; /**< Offset: 0x40 (R/ 32) Status Register */
__O SSC_IER_Type SSC_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */
__O SSC_IDR_Type SSC_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */
__I SSC_IMR_Type SSC_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */
__I uint32_t Reserved3[37];
__IO SSC_WPMR_Type SSC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I SSC_WPSR_Type SSC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Ssc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Synchronous Serial Controller */
#endif /* _SAME70_SSC_COMPONENT_H_ */

809
ext/hal/atmel/asf/sam/include/same70b/component/supc.h Normal file
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@ -0,0 +1,809 @@
/**
* \file
*
* \brief Component description for SUPC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SUPC_COMPONENT_H_
#define _SAME70_SUPC_COMPONENT_H_
#define _SAME70_SUPC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Supply Controller
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SUPC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define SUPC_6452 /**< (SUPC) Module ID */
#define REV_SUPC ZE /**< (SUPC) Module revision */
/* -------- SUPC_CR : (SUPC Offset: 0x00) (/W 32) Supply Controller Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /**< bit: 0..1 Reserved */
uint32_t VROFF:1; /**< bit: 2 Voltage Regulator Off */
uint32_t XTALSEL:1; /**< bit: 3 Crystal Oscillator Select */
uint32_t :20; /**< bit: 4..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 Password */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SUPC_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_CR_OFFSET (0x00) /**< (SUPC_CR) Supply Controller Control Register Offset */
#define SUPC_CR_VROFF_Pos 2 /**< (SUPC_CR) Voltage Regulator Off Position */
#define SUPC_CR_VROFF_Msk (_U_(0x1) << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) Voltage Regulator Off Mask */
#define SUPC_CR_VROFF SUPC_CR_VROFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_VROFF_Msk instead */
#define SUPC_CR_VROFF_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */
#define SUPC_CR_VROFF_STOP_VREG_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */
#define SUPC_CR_VROFF_NO_EFFECT (SUPC_CR_VROFF_NO_EFFECT_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) No effect. Position */
#define SUPC_CR_VROFF_STOP_VREG (SUPC_CR_VROFF_STOP_VREG_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Position */
#define SUPC_CR_XTALSEL_Pos 3 /**< (SUPC_CR) Crystal Oscillator Select Position */
#define SUPC_CR_XTALSEL_Msk (_U_(0x1) << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) Crystal Oscillator Select Mask */
#define SUPC_CR_XTALSEL SUPC_CR_XTALSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_XTALSEL_Msk instead */
#define SUPC_CR_XTALSEL_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */
#define SUPC_CR_XTALSEL_CRYSTAL_SEL_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */
#define SUPC_CR_XTALSEL_NO_EFFECT (SUPC_CR_XTALSEL_NO_EFFECT_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) No effect. Position */
#define SUPC_CR_XTALSEL_CRYSTAL_SEL (SUPC_CR_XTALSEL_CRYSTAL_SEL_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Position */
#define SUPC_CR_KEY_Pos 24 /**< (SUPC_CR) Password Position */
#define SUPC_CR_KEY_Msk (_U_(0xFF) << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Password Mask */
#define SUPC_CR_KEY(value) (SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))
#define SUPC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. */
#define SUPC_CR_KEY_PASSWD (SUPC_CR_KEY_PASSWD_Val << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. Position */
#define SUPC_CR_MASK _U_(0xFF00000C) /**< \deprecated (SUPC_CR) Register MASK (Use SUPC_CR_Msk instead) */
#define SUPC_CR_Msk _U_(0xFF00000C) /**< (SUPC_CR) Register Mask */
/* -------- SUPC_SMMR : (SUPC Offset: 0x04) (R/W 32) Supply Controller Supply Monitor Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMTH:4; /**< bit: 0..3 Supply Monitor Threshold */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t SMSMPL:3; /**< bit: 8..10 Supply Monitor Sampling Period */
uint32_t :1; /**< bit: 11 Reserved */
uint32_t SMRSTEN:1; /**< bit: 12 Supply Monitor Reset Enable */
uint32_t SMIEN:1; /**< bit: 13 Supply Monitor Interrupt Enable */
uint32_t :18; /**< bit: 14..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SUPC_SMMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_SMMR_OFFSET (0x04) /**< (SUPC_SMMR) Supply Controller Supply Monitor Mode Register Offset */
#define SUPC_SMMR_SMTH_Pos 0 /**< (SUPC_SMMR) Supply Monitor Threshold Position */
#define SUPC_SMMR_SMTH_Msk (_U_(0xF) << SUPC_SMMR_SMTH_Pos) /**< (SUPC_SMMR) Supply Monitor Threshold Mask */
#define SUPC_SMMR_SMTH(value) (SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))
#define SUPC_SMMR_SMSMPL_Pos 8 /**< (SUPC_SMMR) Supply Monitor Sampling Period Position */
#define SUPC_SMMR_SMSMPL_Msk (_U_(0x7) << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor Sampling Period Mask */
#define SUPC_SMMR_SMSMPL(value) (SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))
#define SUPC_SMMR_SMSMPL_SMD_Val _U_(0x0) /**< (SUPC_SMMR) Supply Monitor disabled */
#define SUPC_SMMR_SMSMPL_CSM_Val _U_(0x1) /**< (SUPC_SMMR) Continuous Supply Monitor */
#define SUPC_SMMR_SMSMPL_32SLCK_Val _U_(0x2) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
#define SUPC_SMMR_SMSMPL_256SLCK_Val _U_(0x3) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
#define SUPC_SMMR_SMSMPL_2048SLCK_Val _U_(0x4) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
#define SUPC_SMMR_SMSMPL_SMD (SUPC_SMMR_SMSMPL_SMD_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor disabled Position */
#define SUPC_SMMR_SMSMPL_CSM (SUPC_SMMR_SMSMPL_CSM_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Continuous Supply Monitor Position */
#define SUPC_SMMR_SMSMPL_32SLCK (SUPC_SMMR_SMSMPL_32SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods Position */
#define SUPC_SMMR_SMSMPL_256SLCK (SUPC_SMMR_SMSMPL_256SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods Position */
#define SUPC_SMMR_SMSMPL_2048SLCK (SUPC_SMMR_SMSMPL_2048SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods Position */
#define SUPC_SMMR_SMRSTEN_Pos 12 /**< (SUPC_SMMR) Supply Monitor Reset Enable Position */
#define SUPC_SMMR_SMRSTEN_Msk (_U_(0x1) << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) Supply Monitor Reset Enable Mask */
#define SUPC_SMMR_SMRSTEN SUPC_SMMR_SMRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMRSTEN_Msk instead */
#define SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */
#define SUPC_SMMR_SMRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. Position */
#define SUPC_SMMR_SMRSTEN_ENABLE (SUPC_SMMR_SMRSTEN_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Position */
#define SUPC_SMMR_SMIEN_Pos 13 /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Position */
#define SUPC_SMMR_SMIEN_Msk (_U_(0x1) << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Mask */
#define SUPC_SMMR_SMIEN SUPC_SMMR_SMIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMIEN_Msk instead */
#define SUPC_SMMR_SMIEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */
#define SUPC_SMMR_SMIEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */
#define SUPC_SMMR_SMIEN_NOT_ENABLE (SUPC_SMMR_SMIEN_NOT_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. Position */
#define SUPC_SMMR_SMIEN_ENABLE (SUPC_SMMR_SMIEN_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. Position */
#define SUPC_SMMR_MASK _U_(0x370F) /**< \deprecated (SUPC_SMMR) Register MASK (Use SUPC_SMMR_Msk instead) */
#define SUPC_SMMR_Msk _U_(0x370F) /**< (SUPC_SMMR) Register Mask */
/* -------- SUPC_MR : (SUPC Offset: 0x08) (R/W 32) Supply Controller Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :12; /**< bit: 0..11 Reserved */
uint32_t BODRSTEN:1; /**< bit: 12 Brownout Detector Reset Enable */
uint32_t BODDIS:1; /**< bit: 13 Brownout Detector Disable */
uint32_t ONREG:1; /**< bit: 14 Voltage Regulator Enable */
uint32_t :2; /**< bit: 15..16 Reserved */
uint32_t BKUPRETON:1; /**< bit: 17 SRAM On In Backup Mode */
uint32_t :2; /**< bit: 18..19 Reserved */
uint32_t OSCBYPASS:1; /**< bit: 20 Oscillator Bypass */
uint32_t :3; /**< bit: 21..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 Password Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} SUPC_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_MR_OFFSET (0x08) /**< (SUPC_MR) Supply Controller Mode Register Offset */
#define SUPC_MR_BODRSTEN_Pos 12 /**< (SUPC_MR) Brownout Detector Reset Enable Position */
#define SUPC_MR_BODRSTEN_Msk (_U_(0x1) << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) Brownout Detector Reset Enable Mask */
#define SUPC_MR_BODRSTEN SUPC_MR_BODRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODRSTEN_Msk instead */
#define SUPC_MR_BODRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */
#define SUPC_MR_BODRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
#define SUPC_MR_BODRSTEN_NOT_ENABLE (SUPC_MR_BODRSTEN_NOT_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. Position */
#define SUPC_MR_BODRSTEN_ENABLE (SUPC_MR_BODRSTEN_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Position */
#define SUPC_MR_BODDIS_Pos 13 /**< (SUPC_MR) Brownout Detector Disable Position */
#define SUPC_MR_BODDIS_Msk (_U_(0x1) << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) Brownout Detector Disable Mask */
#define SUPC_MR_BODDIS SUPC_MR_BODDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODDIS_Msk instead */
#define SUPC_MR_BODDIS_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core brownout detector is enabled. */
#define SUPC_MR_BODDIS_DISABLE_Val _U_(0x1) /**< (SUPC_MR) The core brownout detector is disabled. */
#define SUPC_MR_BODDIS_ENABLE (SUPC_MR_BODDIS_ENABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is enabled. Position */
#define SUPC_MR_BODDIS_DISABLE (SUPC_MR_BODDIS_DISABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is disabled. Position */
#define SUPC_MR_ONREG_Pos 14 /**< (SUPC_MR) Voltage Regulator Enable Position */
#define SUPC_MR_ONREG_Msk (_U_(0x1) << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Voltage Regulator Enable Mask */
#define SUPC_MR_ONREG SUPC_MR_ONREG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_ONREG_Msk instead */
#define SUPC_MR_ONREG_ONREG_UNUSED_Val _U_(0x0) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */
#define SUPC_MR_ONREG_ONREG_USED_Val _U_(0x1) /**< (SUPC_MR) Internal voltage regulator is used. */
#define SUPC_MR_ONREG_ONREG_UNUSED (SUPC_MR_ONREG_ONREG_UNUSED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). Position */
#define SUPC_MR_ONREG_ONREG_USED (SUPC_MR_ONREG_ONREG_USED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is used. Position */
#define SUPC_MR_BKUPRETON_Pos 17 /**< (SUPC_MR) SRAM On In Backup Mode Position */
#define SUPC_MR_BKUPRETON_Msk (_U_(0x1) << SUPC_MR_BKUPRETON_Pos) /**< (SUPC_MR) SRAM On In Backup Mode Mask */
#define SUPC_MR_BKUPRETON SUPC_MR_BKUPRETON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BKUPRETON_Msk instead */
#define SUPC_MR_OSCBYPASS_Pos 20 /**< (SUPC_MR) Oscillator Bypass Position */
#define SUPC_MR_OSCBYPASS_Msk (_U_(0x1) << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) Oscillator Bypass Mask */
#define SUPC_MR_OSCBYPASS SUPC_MR_OSCBYPASS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_OSCBYPASS_Msk instead */
#define SUPC_MR_OSCBYPASS_NO_EFFECT_Val _U_(0x0) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */
#define SUPC_MR_OSCBYPASS_BYPASS_Val _U_(0x1) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */
#define SUPC_MR_OSCBYPASS_NO_EFFECT (SUPC_MR_OSCBYPASS_NO_EFFECT_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). Position */
#define SUPC_MR_OSCBYPASS_BYPASS (SUPC_MR_OSCBYPASS_BYPASS_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Position */
#define SUPC_MR_KEY_Pos 24 /**< (SUPC_MR) Password Key Position */
#define SUPC_MR_KEY_Msk (_U_(0xFF) << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Password Key Mask */
#define SUPC_MR_KEY(value) (SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))
#define SUPC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. */
#define SUPC_MR_KEY_PASSWD (SUPC_MR_KEY_PASSWD_Val << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. Position */
#define SUPC_MR_MASK _U_(0xFF127000) /**< \deprecated (SUPC_MR) Register MASK (Use SUPC_MR_Msk instead) */
#define SUPC_MR_Msk _U_(0xFF127000) /**< (SUPC_MR) Register Mask */
/* -------- SUPC_WUMR : (SUPC Offset: 0x0c) (R/W 32) Supply Controller Wake-up Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /**< bit: 0 Reserved */
uint32_t SMEN:1; /**< bit: 1 Supply Monitor Wake-up Enable */
uint32_t RTTEN:1; /**< bit: 2 Real-time Timer Wake-up Enable */
uint32_t RTCEN:1; /**< bit: 3 Real-time Clock Wake-up Enable */
uint32_t :1; /**< bit: 4 Reserved */
uint32_t LPDBCEN0:1; /**< bit: 5 Low-power Debouncer Enable WKUP0 */
uint32_t LPDBCEN1:1; /**< bit: 6 Low-power Debouncer Enable WKUP1 */
uint32_t LPDBCCLR:1; /**< bit: 7 Low-power Debouncer Clear */
uint32_t :4; /**< bit: 8..11 Reserved */
uint32_t WKUPDBC:3; /**< bit: 12..14 Wake-up Inputs Debouncer Period */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t LPDBC:3; /**< bit: 16..18 Low-power Debouncer Period */
uint32_t :13; /**< bit: 19..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :5; /**< bit: 0..4 Reserved */
uint32_t LPDBCEN:2; /**< bit: 5..6 Low-power Debouncer Enable WKUPx */
uint32_t :25; /**< bit: 7..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SUPC_WUMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_WUMR_OFFSET (0x0C) /**< (SUPC_WUMR) Supply Controller Wake-up Mode Register Offset */
#define SUPC_WUMR_SMEN_Pos 1 /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Position */
#define SUPC_WUMR_SMEN_Msk (_U_(0x1) << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Mask */
#define SUPC_WUMR_SMEN SUPC_WUMR_SMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_SMEN_Msk instead */
#define SUPC_WUMR_SMEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. */
#define SUPC_WUMR_SMEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */
#define SUPC_WUMR_SMEN_NOT_ENABLE (SUPC_WUMR_SMEN_NOT_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. Position */
#define SUPC_WUMR_SMEN_ENABLE (SUPC_WUMR_SMEN_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. Position */
#define SUPC_WUMR_RTTEN_Pos 2 /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Position */
#define SUPC_WUMR_RTTEN_Msk (_U_(0x1) << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Mask */
#define SUPC_WUMR_RTTEN SUPC_WUMR_RTTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTTEN_Msk instead */
#define SUPC_WUMR_RTTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */
#define SUPC_WUMR_RTTEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */
#define SUPC_WUMR_RTTEN_NOT_ENABLE (SUPC_WUMR_RTTEN_NOT_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. Position */
#define SUPC_WUMR_RTTEN_ENABLE (SUPC_WUMR_RTTEN_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. Position */
#define SUPC_WUMR_RTCEN_Pos 3 /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Position */
#define SUPC_WUMR_RTCEN_Msk (_U_(0x1) << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Mask */
#define SUPC_WUMR_RTCEN SUPC_WUMR_RTCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTCEN_Msk instead */
#define SUPC_WUMR_RTCEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */
#define SUPC_WUMR_RTCEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */
#define SUPC_WUMR_RTCEN_NOT_ENABLE (SUPC_WUMR_RTCEN_NOT_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. Position */
#define SUPC_WUMR_RTCEN_ENABLE (SUPC_WUMR_RTCEN_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. Position */
#define SUPC_WUMR_LPDBCEN0_Pos 5 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Position */
#define SUPC_WUMR_LPDBCEN0_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Mask */
#define SUPC_WUMR_LPDBCEN0 SUPC_WUMR_LPDBCEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN0_Msk instead */
#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */
#define SUPC_WUMR_LPDBCEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */
#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. Position */
#define SUPC_WUMR_LPDBCEN0_ENABLE (SUPC_WUMR_LPDBCEN0_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. Position */
#define SUPC_WUMR_LPDBCEN1_Pos 6 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Position */
#define SUPC_WUMR_LPDBCEN1_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Mask */
#define SUPC_WUMR_LPDBCEN1 SUPC_WUMR_LPDBCEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN1_Msk instead */
#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */
#define SUPC_WUMR_LPDBCEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */
#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. Position */
#define SUPC_WUMR_LPDBCEN1_ENABLE (SUPC_WUMR_LPDBCEN1_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. Position */
#define SUPC_WUMR_LPDBCCLR_Pos 7 /**< (SUPC_WUMR) Low-power Debouncer Clear Position */
#define SUPC_WUMR_LPDBCCLR_Msk (_U_(0x1) << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) Low-power Debouncer Clear Mask */
#define SUPC_WUMR_LPDBCCLR SUPC_WUMR_LPDBCCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCCLR_Msk instead */
#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */
#define SUPC_WUMR_LPDBCCLR_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */
#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. Position */
#define SUPC_WUMR_LPDBCCLR_ENABLE (SUPC_WUMR_LPDBCCLR_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. Position */
#define SUPC_WUMR_WKUPDBC_Pos 12 /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Position */
#define SUPC_WUMR_WKUPDBC_Msk (_U_(0x7) << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Mask */
#define SUPC_WUMR_WKUPDBC(value) (SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))
#define SUPC_WUMR_WKUPDBC_IMMEDIATE_Val _U_(0x0) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
#define SUPC_WUMR_WKUPDBC_3_SLCK_Val _U_(0x1) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
#define SUPC_WUMR_WKUPDBC_32_SLCK_Val _U_(0x2) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
#define SUPC_WUMR_WKUPDBC_512_SLCK_Val _U_(0x3) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
#define SUPC_WUMR_WKUPDBC_4096_SLCK_Val _U_(0x4) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
#define SUPC_WUMR_WKUPDBC_32768_SLCK_Val _U_(0x5) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
#define SUPC_WUMR_WKUPDBC_IMMEDIATE (SUPC_WUMR_WKUPDBC_IMMEDIATE_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. Position */
#define SUPC_WUMR_WKUPDBC_3_SLCK (SUPC_WUMR_WKUPDBC_3_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods Position */
#define SUPC_WUMR_WKUPDBC_32_SLCK (SUPC_WUMR_WKUPDBC_32_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods Position */
#define SUPC_WUMR_WKUPDBC_512_SLCK (SUPC_WUMR_WKUPDBC_512_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods Position */
#define SUPC_WUMR_WKUPDBC_4096_SLCK (SUPC_WUMR_WKUPDBC_4096_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods Position */
#define SUPC_WUMR_WKUPDBC_32768_SLCK (SUPC_WUMR_WKUPDBC_32768_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods Position */
#define SUPC_WUMR_LPDBC_Pos 16 /**< (SUPC_WUMR) Low-power Debouncer Period Position */
#define SUPC_WUMR_LPDBC_Msk (_U_(0x7) << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Low-power Debouncer Period Mask */
#define SUPC_WUMR_LPDBC(value) (SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))
#define SUPC_WUMR_LPDBC_DISABLE_Val _U_(0x0) /**< (SUPC_WUMR) Disable the low-power debouncers. */
#define SUPC_WUMR_LPDBC_2_RTCOUT_Val _U_(0x1) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_3_RTCOUT_Val _U_(0x2) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_4_RTCOUT_Val _U_(0x3) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_5_RTCOUT_Val _U_(0x4) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_6_RTCOUT_Val _U_(0x5) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_7_RTCOUT_Val _U_(0x6) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_8_RTCOUT_Val _U_(0x7) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */
#define SUPC_WUMR_LPDBC_DISABLE (SUPC_WUMR_LPDBC_DISABLE_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Disable the low-power debouncers. Position */
#define SUPC_WUMR_LPDBC_2_RTCOUT (SUPC_WUMR_LPDBC_2_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_3_RTCOUT (SUPC_WUMR_LPDBC_3_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_4_RTCOUT (SUPC_WUMR_LPDBC_4_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_5_RTCOUT (SUPC_WUMR_LPDBC_5_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_6_RTCOUT (SUPC_WUMR_LPDBC_6_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_7_RTCOUT (SUPC_WUMR_LPDBC_7_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods Position */
#define SUPC_WUMR_LPDBC_8_RTCOUT (SUPC_WUMR_LPDBC_8_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods Position */
#define SUPC_WUMR_MASK _U_(0x770EE) /**< \deprecated (SUPC_WUMR) Register MASK (Use SUPC_WUMR_Msk instead) */
#define SUPC_WUMR_Msk _U_(0x770EE) /**< (SUPC_WUMR) Register Mask */
#define SUPC_WUMR_LPDBCEN_Pos 5 /**< (SUPC_WUMR Position) Low-power Debouncer Enable WKUPx */
#define SUPC_WUMR_LPDBCEN_Msk (_U_(0x3) << SUPC_WUMR_LPDBCEN_Pos) /**< (SUPC_WUMR Mask) LPDBCEN */
#define SUPC_WUMR_LPDBCEN(value) (SUPC_WUMR_LPDBCEN_Msk & ((value) << SUPC_WUMR_LPDBCEN_Pos))
/* -------- SUPC_WUIR : (SUPC Offset: 0x10) (R/W 32) Supply Controller Wake-up Inputs Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WKUPEN0:1; /**< bit: 0 Wake-up Input Enable 0 to 0 */
uint32_t WKUPEN1:1; /**< bit: 1 Wake-up Input Enable 0 to 1 */
uint32_t WKUPEN2:1; /**< bit: 2 Wake-up Input Enable 0 to 2 */
uint32_t WKUPEN3:1; /**< bit: 3 Wake-up Input Enable 0 to 3 */
uint32_t WKUPEN4:1; /**< bit: 4 Wake-up Input Enable 0 to 4 */
uint32_t WKUPEN5:1; /**< bit: 5 Wake-up Input Enable 0 to 5 */
uint32_t WKUPEN6:1; /**< bit: 6 Wake-up Input Enable 0 to 6 */
uint32_t WKUPEN7:1; /**< bit: 7 Wake-up Input Enable 0 to 7 */
uint32_t WKUPEN8:1; /**< bit: 8 Wake-up Input Enable 0 to 8 */
uint32_t WKUPEN9:1; /**< bit: 9 Wake-up Input Enable 0 to 9 */
uint32_t WKUPEN10:1; /**< bit: 10 Wake-up Input Enable 0 to 10 */
uint32_t WKUPEN11:1; /**< bit: 11 Wake-up Input Enable 0 to 11 */
uint32_t WKUPEN12:1; /**< bit: 12 Wake-up Input Enable 0 to 12 */
uint32_t WKUPEN13:1; /**< bit: 13 Wake-up Input Enable 0 to 13 */
uint32_t :2; /**< bit: 14..15 Reserved */
uint32_t WKUPT0:1; /**< bit: 16 Wake-up Input Type 0 to 0 */
uint32_t WKUPT1:1; /**< bit: 17 Wake-up Input Type 0 to 1 */
uint32_t WKUPT2:1; /**< bit: 18 Wake-up Input Type 0 to 2 */
uint32_t WKUPT3:1; /**< bit: 19 Wake-up Input Type 0 to 3 */
uint32_t WKUPT4:1; /**< bit: 20 Wake-up Input Type 0 to 4 */
uint32_t WKUPT5:1; /**< bit: 21 Wake-up Input Type 0 to 5 */
uint32_t WKUPT6:1; /**< bit: 22 Wake-up Input Type 0 to 6 */
uint32_t WKUPT7:1; /**< bit: 23 Wake-up Input Type 0 to 7 */
uint32_t WKUPT8:1; /**< bit: 24 Wake-up Input Type 0 to 8 */
uint32_t WKUPT9:1; /**< bit: 25 Wake-up Input Type 0 to 9 */
uint32_t WKUPT10:1; /**< bit: 26 Wake-up Input Type 0 to 10 */
uint32_t WKUPT11:1; /**< bit: 27 Wake-up Input Type 0 to 11 */
uint32_t WKUPT12:1; /**< bit: 28 Wake-up Input Type 0 to 12 */
uint32_t WKUPT13:1; /**< bit: 29 Wake-up Input Type 0 to 13 */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t WKUPEN:14; /**< bit: 0..13 Wake-up Input Enable x to x */
uint32_t :2; /**< bit: 14..15 Reserved */
uint32_t WKUPT:14; /**< bit: 16..29 Wake-up Input Type x to x3 */
uint32_t :2; /**< bit: 30..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SUPC_WUIR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_WUIR_OFFSET (0x10) /**< (SUPC_WUIR) Supply Controller Wake-up Inputs Register Offset */
#define SUPC_WUIR_WKUPEN0_Pos 0 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Position */
#define SUPC_WUIR_WKUPEN0_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Mask */
#define SUPC_WUIR_WKUPEN0 SUPC_WUIR_WKUPEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN0_Msk instead */
#define SUPC_WUIR_WKUPEN0_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN0_DISABLE (SUPC_WUIR_WKUPEN0_DISABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN0_ENABLE (SUPC_WUIR_WKUPEN0_ENABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN1_Pos 1 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Position */
#define SUPC_WUIR_WKUPEN1_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Mask */
#define SUPC_WUIR_WKUPEN1 SUPC_WUIR_WKUPEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN1_Msk instead */
#define SUPC_WUIR_WKUPEN1_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN1_DISABLE (SUPC_WUIR_WKUPEN1_DISABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN1_ENABLE (SUPC_WUIR_WKUPEN1_ENABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN2_Pos 2 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Position */
#define SUPC_WUIR_WKUPEN2_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Mask */
#define SUPC_WUIR_WKUPEN2 SUPC_WUIR_WKUPEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN2_Msk instead */
#define SUPC_WUIR_WKUPEN2_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN2_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN2_DISABLE (SUPC_WUIR_WKUPEN2_DISABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN2_ENABLE (SUPC_WUIR_WKUPEN2_ENABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN3_Pos 3 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Position */
#define SUPC_WUIR_WKUPEN3_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Mask */
#define SUPC_WUIR_WKUPEN3 SUPC_WUIR_WKUPEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN3_Msk instead */
#define SUPC_WUIR_WKUPEN3_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN3_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN3_DISABLE (SUPC_WUIR_WKUPEN3_DISABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN3_ENABLE (SUPC_WUIR_WKUPEN3_ENABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN4_Pos 4 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Position */
#define SUPC_WUIR_WKUPEN4_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Mask */
#define SUPC_WUIR_WKUPEN4 SUPC_WUIR_WKUPEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN4_Msk instead */
#define SUPC_WUIR_WKUPEN4_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN4_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN4_DISABLE (SUPC_WUIR_WKUPEN4_DISABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN4_ENABLE (SUPC_WUIR_WKUPEN4_ENABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN5_Pos 5 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Position */
#define SUPC_WUIR_WKUPEN5_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Mask */
#define SUPC_WUIR_WKUPEN5 SUPC_WUIR_WKUPEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN5_Msk instead */
#define SUPC_WUIR_WKUPEN5_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN5_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN5_DISABLE (SUPC_WUIR_WKUPEN5_DISABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN5_ENABLE (SUPC_WUIR_WKUPEN5_ENABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN6_Pos 6 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Position */
#define SUPC_WUIR_WKUPEN6_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Mask */
#define SUPC_WUIR_WKUPEN6 SUPC_WUIR_WKUPEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN6_Msk instead */
#define SUPC_WUIR_WKUPEN6_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN6_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN6_DISABLE (SUPC_WUIR_WKUPEN6_DISABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN6_ENABLE (SUPC_WUIR_WKUPEN6_ENABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN7_Pos 7 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Position */
#define SUPC_WUIR_WKUPEN7_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Mask */
#define SUPC_WUIR_WKUPEN7 SUPC_WUIR_WKUPEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN7_Msk instead */
#define SUPC_WUIR_WKUPEN7_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN7_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN7_DISABLE (SUPC_WUIR_WKUPEN7_DISABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN7_ENABLE (SUPC_WUIR_WKUPEN7_ENABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN8_Pos 8 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Position */
#define SUPC_WUIR_WKUPEN8_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Mask */
#define SUPC_WUIR_WKUPEN8 SUPC_WUIR_WKUPEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN8_Msk instead */
#define SUPC_WUIR_WKUPEN8_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN8_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN8_DISABLE (SUPC_WUIR_WKUPEN8_DISABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN8_ENABLE (SUPC_WUIR_WKUPEN8_ENABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN9_Pos 9 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Position */
#define SUPC_WUIR_WKUPEN9_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Mask */
#define SUPC_WUIR_WKUPEN9 SUPC_WUIR_WKUPEN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN9_Msk instead */
#define SUPC_WUIR_WKUPEN9_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN9_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN9_DISABLE (SUPC_WUIR_WKUPEN9_DISABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN9_ENABLE (SUPC_WUIR_WKUPEN9_ENABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN10_Pos 10 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Position */
#define SUPC_WUIR_WKUPEN10_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Mask */
#define SUPC_WUIR_WKUPEN10 SUPC_WUIR_WKUPEN10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN10_Msk instead */
#define SUPC_WUIR_WKUPEN10_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN10_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN10_DISABLE (SUPC_WUIR_WKUPEN10_DISABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN10_ENABLE (SUPC_WUIR_WKUPEN10_ENABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN11_Pos 11 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Position */
#define SUPC_WUIR_WKUPEN11_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Mask */
#define SUPC_WUIR_WKUPEN11 SUPC_WUIR_WKUPEN11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN11_Msk instead */
#define SUPC_WUIR_WKUPEN11_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN11_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN11_DISABLE (SUPC_WUIR_WKUPEN11_DISABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN11_ENABLE (SUPC_WUIR_WKUPEN11_ENABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN12_Pos 12 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Position */
#define SUPC_WUIR_WKUPEN12_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Mask */
#define SUPC_WUIR_WKUPEN12 SUPC_WUIR_WKUPEN12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN12_Msk instead */
#define SUPC_WUIR_WKUPEN12_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN12_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN12_DISABLE (SUPC_WUIR_WKUPEN12_DISABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN12_ENABLE (SUPC_WUIR_WKUPEN12_ENABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPEN13_Pos 13 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Position */
#define SUPC_WUIR_WKUPEN13_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Mask */
#define SUPC_WUIR_WKUPEN13 SUPC_WUIR_WKUPEN13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN13_Msk instead */
#define SUPC_WUIR_WKUPEN13_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
#define SUPC_WUIR_WKUPEN13_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
#define SUPC_WUIR_WKUPEN13_DISABLE (SUPC_WUIR_WKUPEN13_DISABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */
#define SUPC_WUIR_WKUPEN13_ENABLE (SUPC_WUIR_WKUPEN13_ENABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT0_Pos 16 /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Position */
#define SUPC_WUIR_WKUPT0_Msk (_U_(0x1) << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Mask */
#define SUPC_WUIR_WKUPT0 SUPC_WUIR_WKUPT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT0_Msk instead */
#define SUPC_WUIR_WKUPT0_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT0_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT0_LOW (SUPC_WUIR_WKUPT0_LOW_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT0_HIGH (SUPC_WUIR_WKUPT0_HIGH_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT1_Pos 17 /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Position */
#define SUPC_WUIR_WKUPT1_Msk (_U_(0x1) << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Mask */
#define SUPC_WUIR_WKUPT1 SUPC_WUIR_WKUPT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT1_Msk instead */
#define SUPC_WUIR_WKUPT1_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT1_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT1_LOW (SUPC_WUIR_WKUPT1_LOW_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT1_HIGH (SUPC_WUIR_WKUPT1_HIGH_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT2_Pos 18 /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Position */
#define SUPC_WUIR_WKUPT2_Msk (_U_(0x1) << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Mask */
#define SUPC_WUIR_WKUPT2 SUPC_WUIR_WKUPT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT2_Msk instead */
#define SUPC_WUIR_WKUPT2_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT2_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT2_LOW (SUPC_WUIR_WKUPT2_LOW_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT2_HIGH (SUPC_WUIR_WKUPT2_HIGH_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT3_Pos 19 /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Position */
#define SUPC_WUIR_WKUPT3_Msk (_U_(0x1) << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Mask */
#define SUPC_WUIR_WKUPT3 SUPC_WUIR_WKUPT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT3_Msk instead */
#define SUPC_WUIR_WKUPT3_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT3_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT3_LOW (SUPC_WUIR_WKUPT3_LOW_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT3_HIGH (SUPC_WUIR_WKUPT3_HIGH_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT4_Pos 20 /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Position */
#define SUPC_WUIR_WKUPT4_Msk (_U_(0x1) << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Mask */
#define SUPC_WUIR_WKUPT4 SUPC_WUIR_WKUPT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT4_Msk instead */
#define SUPC_WUIR_WKUPT4_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT4_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT4_LOW (SUPC_WUIR_WKUPT4_LOW_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT4_HIGH (SUPC_WUIR_WKUPT4_HIGH_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT5_Pos 21 /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Position */
#define SUPC_WUIR_WKUPT5_Msk (_U_(0x1) << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Mask */
#define SUPC_WUIR_WKUPT5 SUPC_WUIR_WKUPT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT5_Msk instead */
#define SUPC_WUIR_WKUPT5_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT5_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT5_LOW (SUPC_WUIR_WKUPT5_LOW_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT5_HIGH (SUPC_WUIR_WKUPT5_HIGH_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT6_Pos 22 /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Position */
#define SUPC_WUIR_WKUPT6_Msk (_U_(0x1) << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Mask */
#define SUPC_WUIR_WKUPT6 SUPC_WUIR_WKUPT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT6_Msk instead */
#define SUPC_WUIR_WKUPT6_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT6_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT6_LOW (SUPC_WUIR_WKUPT6_LOW_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT6_HIGH (SUPC_WUIR_WKUPT6_HIGH_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT7_Pos 23 /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Position */
#define SUPC_WUIR_WKUPT7_Msk (_U_(0x1) << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Mask */
#define SUPC_WUIR_WKUPT7 SUPC_WUIR_WKUPT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT7_Msk instead */
#define SUPC_WUIR_WKUPT7_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT7_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT7_LOW (SUPC_WUIR_WKUPT7_LOW_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT7_HIGH (SUPC_WUIR_WKUPT7_HIGH_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT8_Pos 24 /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Position */
#define SUPC_WUIR_WKUPT8_Msk (_U_(0x1) << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Mask */
#define SUPC_WUIR_WKUPT8 SUPC_WUIR_WKUPT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT8_Msk instead */
#define SUPC_WUIR_WKUPT8_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT8_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT8_LOW (SUPC_WUIR_WKUPT8_LOW_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT8_HIGH (SUPC_WUIR_WKUPT8_HIGH_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT9_Pos 25 /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Position */
#define SUPC_WUIR_WKUPT9_Msk (_U_(0x1) << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Mask */
#define SUPC_WUIR_WKUPT9 SUPC_WUIR_WKUPT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT9_Msk instead */
#define SUPC_WUIR_WKUPT9_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT9_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT9_LOW (SUPC_WUIR_WKUPT9_LOW_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT9_HIGH (SUPC_WUIR_WKUPT9_HIGH_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT10_Pos 26 /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Position */
#define SUPC_WUIR_WKUPT10_Msk (_U_(0x1) << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Mask */
#define SUPC_WUIR_WKUPT10 SUPC_WUIR_WKUPT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT10_Msk instead */
#define SUPC_WUIR_WKUPT10_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT10_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT10_LOW (SUPC_WUIR_WKUPT10_LOW_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT10_HIGH (SUPC_WUIR_WKUPT10_HIGH_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT11_Pos 27 /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Position */
#define SUPC_WUIR_WKUPT11_Msk (_U_(0x1) << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Mask */
#define SUPC_WUIR_WKUPT11 SUPC_WUIR_WKUPT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT11_Msk instead */
#define SUPC_WUIR_WKUPT11_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT11_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT11_LOW (SUPC_WUIR_WKUPT11_LOW_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT11_HIGH (SUPC_WUIR_WKUPT11_HIGH_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT12_Pos 28 /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Position */
#define SUPC_WUIR_WKUPT12_Msk (_U_(0x1) << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Mask */
#define SUPC_WUIR_WKUPT12 SUPC_WUIR_WKUPT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT12_Msk instead */
#define SUPC_WUIR_WKUPT12_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT12_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT12_LOW (SUPC_WUIR_WKUPT12_LOW_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT12_HIGH (SUPC_WUIR_WKUPT12_HIGH_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT13_Pos 29 /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Position */
#define SUPC_WUIR_WKUPT13_Msk (_U_(0x1) << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Mask */
#define SUPC_WUIR_WKUPT13 SUPC_WUIR_WKUPT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT13_Msk instead */
#define SUPC_WUIR_WKUPT13_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT13_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
#define SUPC_WUIR_WKUPT13_LOW (SUPC_WUIR_WKUPT13_LOW_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_WKUPT13_HIGH (SUPC_WUIR_WKUPT13_HIGH_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */
#define SUPC_WUIR_MASK _U_(0x3FFF3FFF) /**< \deprecated (SUPC_WUIR) Register MASK (Use SUPC_WUIR_Msk instead) */
#define SUPC_WUIR_Msk _U_(0x3FFF3FFF) /**< (SUPC_WUIR) Register Mask */
#define SUPC_WUIR_WKUPEN_Pos 0 /**< (SUPC_WUIR Position) Wake-up Input Enable x to x */
#define SUPC_WUIR_WKUPEN_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPEN_Pos) /**< (SUPC_WUIR Mask) WKUPEN */
#define SUPC_WUIR_WKUPEN(value) (SUPC_WUIR_WKUPEN_Msk & ((value) << SUPC_WUIR_WKUPEN_Pos))
#define SUPC_WUIR_WKUPT_Pos 16 /**< (SUPC_WUIR Position) Wake-up Input Type x to x3 */
#define SUPC_WUIR_WKUPT_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPT_Pos) /**< (SUPC_WUIR Mask) WKUPT */
#define SUPC_WUIR_WKUPT(value) (SUPC_WUIR_WKUPT_Msk & ((value) << SUPC_WUIR_WKUPT_Pos))
/* -------- SUPC_SR : (SUPC Offset: 0x14) (R/ 32) Supply Controller Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /**< bit: 0 Reserved */
uint32_t WKUPS:1; /**< bit: 1 WKUP Wake-up Status (cleared on read) */
uint32_t SMWS:1; /**< bit: 2 Supply Monitor Detection Wake-up Status (cleared on read) */
uint32_t BODRSTS:1; /**< bit: 3 Brownout Detector Reset Status (cleared on read) */
uint32_t SMRSTS:1; /**< bit: 4 Supply Monitor Reset Status (cleared on read) */
uint32_t SMS:1; /**< bit: 5 Supply Monitor Status (cleared on read) */
uint32_t SMOS:1; /**< bit: 6 Supply Monitor Output Status */
uint32_t OSCSEL:1; /**< bit: 7 32-kHz Oscillator Selection Status */
uint32_t :5; /**< bit: 8..12 Reserved */
uint32_t LPDBCS0:1; /**< bit: 13 Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */
uint32_t LPDBCS1:1; /**< bit: 14 Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t WKUPIS0:1; /**< bit: 16 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS1:1; /**< bit: 17 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS2:1; /**< bit: 18 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS3:1; /**< bit: 19 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS4:1; /**< bit: 20 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS5:1; /**< bit: 21 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS6:1; /**< bit: 22 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS7:1; /**< bit: 23 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS8:1; /**< bit: 24 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS9:1; /**< bit: 25 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS10:1; /**< bit: 26 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS11:1; /**< bit: 27 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS12:1; /**< bit: 28 WKUPx Input Status (cleared on read) */
uint32_t WKUPIS13:1; /**< bit: 29 WKUPx Input Status (cleared on read) */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t :13; /**< bit: 0..12 Reserved */
uint32_t LPDBCS:2; /**< bit: 13..14 Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t WKUPIS:14; /**< bit: 16..29 WKUPx Input Status (cleared on read) */
uint32_t :2; /**< bit: 30..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} SUPC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_SR_OFFSET (0x14) /**< (SUPC_SR) Supply Controller Status Register Offset */
#define SUPC_SR_WKUPS_Pos 1 /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Position */
#define SUPC_SR_WKUPS_Msk (_U_(0x1) << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Mask */
#define SUPC_SR_WKUPS SUPC_SR_WKUPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPS_Msk instead */
#define SUPC_SR_WKUPS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
#define SUPC_SR_WKUPS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
#define SUPC_SR_WKUPS_NO (SUPC_SR_WKUPS_NO_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPS_PRESENT (SUPC_SR_WKUPS_PRESENT_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_SMWS_Pos 2 /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Position */
#define SUPC_SR_SMWS_Msk (_U_(0x1) << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Mask */
#define SUPC_SR_SMWS SUPC_SR_SMWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMWS_Msk instead */
#define SUPC_SR_SMWS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
#define SUPC_SR_SMWS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
#define SUPC_SR_SMWS_NO (SUPC_SR_SMWS_NO_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_SMWS_PRESENT (SUPC_SR_SMWS_PRESENT_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_BODRSTS_Pos 3 /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Position */
#define SUPC_SR_BODRSTS_Msk (_U_(0x1) << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Mask */
#define SUPC_SR_BODRSTS SUPC_SR_BODRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_BODRSTS_Msk instead */
#define SUPC_SR_BODRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */
#define SUPC_SR_BODRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
#define SUPC_SR_BODRSTS_NO (SUPC_SR_BODRSTS_NO_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. Position */
#define SUPC_SR_BODRSTS_PRESENT (SUPC_SR_BODRSTS_PRESENT_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Position */
#define SUPC_SR_SMRSTS_Pos 4 /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Position */
#define SUPC_SR_SMRSTS_Msk (_U_(0x1) << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Mask */
#define SUPC_SR_SMRSTS SUPC_SR_SMRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMRSTS_Msk instead */
#define SUPC_SR_SMRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
#define SUPC_SR_SMRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
#define SUPC_SR_SMRSTS_NO (SUPC_SR_SMRSTS_NO_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */
#define SUPC_SR_SMRSTS_PRESENT (SUPC_SR_SMRSTS_PRESENT_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */
#define SUPC_SR_SMS_Pos 5 /**< (SUPC_SR) Supply Monitor Status (cleared on read) Position */
#define SUPC_SR_SMS_Msk (_U_(0x1) << SUPC_SR_SMS_Pos) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Mask */
#define SUPC_SR_SMS SUPC_SR_SMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMS_Msk instead */
#define SUPC_SR_SMS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */
#define SUPC_SR_SMS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */
#define SUPC_SR_SMS_NO (SUPC_SR_SMS_NO_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. Position */
#define SUPC_SR_SMS_PRESENT (SUPC_SR_SMS_PRESENT_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. Position */
#define SUPC_SR_SMOS_Pos 6 /**< (SUPC_SR) Supply Monitor Output Status Position */
#define SUPC_SR_SMOS_Msk (_U_(0x1) << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) Supply Monitor Output Status Mask */
#define SUPC_SR_SMOS SUPC_SR_SMOS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMOS_Msk instead */
#define SUPC_SR_SMOS_HIGH_Val _U_(0x0) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */
#define SUPC_SR_SMOS_LOW_Val _U_(0x1) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */
#define SUPC_SR_SMOS_HIGH (SUPC_SR_SMOS_HIGH_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. Position */
#define SUPC_SR_SMOS_LOW (SUPC_SR_SMOS_LOW_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. Position */
#define SUPC_SR_OSCSEL_Pos 7 /**< (SUPC_SR) 32-kHz Oscillator Selection Status Position */
#define SUPC_SR_OSCSEL_Msk (_U_(0x1) << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Mask */
#define SUPC_SR_OSCSEL SUPC_SR_OSCSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_OSCSEL_Msk instead */
#define SUPC_SR_OSCSEL_RC_Val _U_(0x0) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */
#define SUPC_SR_OSCSEL_CRYST_Val _U_(0x1) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */
#define SUPC_SR_OSCSEL_RC (SUPC_SR_OSCSEL_RC_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. Position */
#define SUPC_SR_OSCSEL_CRYST (SUPC_SR_OSCSEL_CRYST_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. Position */
#define SUPC_SR_LPDBCS0_Pos 13 /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Position */
#define SUPC_SR_LPDBCS0_Msk (_U_(0x1) << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Mask */
#define SUPC_SR_LPDBCS0 SUPC_SR_LPDBCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS0_Msk instead */
#define SUPC_SR_LPDBCS0_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
#define SUPC_SR_LPDBCS0_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
#define SUPC_SR_LPDBCS0_NO (SUPC_SR_LPDBCS0_NO_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_LPDBCS0_PRESENT (SUPC_SR_LPDBCS0_PRESENT_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_LPDBCS1_Pos 14 /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Position */
#define SUPC_SR_LPDBCS1_Msk (_U_(0x1) << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Mask */
#define SUPC_SR_LPDBCS1 SUPC_SR_LPDBCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS1_Msk instead */
#define SUPC_SR_LPDBCS1_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
#define SUPC_SR_LPDBCS1_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
#define SUPC_SR_LPDBCS1_NO (SUPC_SR_LPDBCS1_NO_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_LPDBCS1_PRESENT (SUPC_SR_LPDBCS1_PRESENT_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS0_Pos 16 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS0_Msk (_U_(0x1) << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS0 SUPC_SR_WKUPIS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS0_Msk instead */
#define SUPC_SR_WKUPIS0_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS0_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS0_DIS (SUPC_SR_WKUPIS0_DIS_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS0_EN (SUPC_SR_WKUPIS0_EN_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS1_Pos 17 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS1_Msk (_U_(0x1) << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS1 SUPC_SR_WKUPIS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS1_Msk instead */
#define SUPC_SR_WKUPIS1_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS1_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS1_DIS (SUPC_SR_WKUPIS1_DIS_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS1_EN (SUPC_SR_WKUPIS1_EN_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS2_Pos 18 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS2_Msk (_U_(0x1) << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS2 SUPC_SR_WKUPIS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS2_Msk instead */
#define SUPC_SR_WKUPIS2_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS2_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS2_DIS (SUPC_SR_WKUPIS2_DIS_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS2_EN (SUPC_SR_WKUPIS2_EN_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS3_Pos 19 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS3_Msk (_U_(0x1) << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS3 SUPC_SR_WKUPIS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS3_Msk instead */
#define SUPC_SR_WKUPIS3_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS3_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS3_DIS (SUPC_SR_WKUPIS3_DIS_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS3_EN (SUPC_SR_WKUPIS3_EN_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS4_Pos 20 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS4_Msk (_U_(0x1) << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS4 SUPC_SR_WKUPIS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS4_Msk instead */
#define SUPC_SR_WKUPIS4_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS4_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS4_DIS (SUPC_SR_WKUPIS4_DIS_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS4_EN (SUPC_SR_WKUPIS4_EN_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS5_Pos 21 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS5_Msk (_U_(0x1) << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS5 SUPC_SR_WKUPIS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS5_Msk instead */
#define SUPC_SR_WKUPIS5_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS5_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS5_DIS (SUPC_SR_WKUPIS5_DIS_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS5_EN (SUPC_SR_WKUPIS5_EN_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS6_Pos 22 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS6_Msk (_U_(0x1) << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS6 SUPC_SR_WKUPIS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS6_Msk instead */
#define SUPC_SR_WKUPIS6_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS6_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS6_DIS (SUPC_SR_WKUPIS6_DIS_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS6_EN (SUPC_SR_WKUPIS6_EN_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS7_Pos 23 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS7_Msk (_U_(0x1) << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS7 SUPC_SR_WKUPIS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS7_Msk instead */
#define SUPC_SR_WKUPIS7_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS7_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS7_DIS (SUPC_SR_WKUPIS7_DIS_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS7_EN (SUPC_SR_WKUPIS7_EN_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS8_Pos 24 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS8_Msk (_U_(0x1) << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS8 SUPC_SR_WKUPIS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS8_Msk instead */
#define SUPC_SR_WKUPIS8_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS8_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS8_DIS (SUPC_SR_WKUPIS8_DIS_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS8_EN (SUPC_SR_WKUPIS8_EN_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS9_Pos 25 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS9_Msk (_U_(0x1) << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS9 SUPC_SR_WKUPIS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS9_Msk instead */
#define SUPC_SR_WKUPIS9_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS9_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS9_DIS (SUPC_SR_WKUPIS9_DIS_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS9_EN (SUPC_SR_WKUPIS9_EN_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS10_Pos 26 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS10_Msk (_U_(0x1) << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS10 SUPC_SR_WKUPIS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS10_Msk instead */
#define SUPC_SR_WKUPIS10_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS10_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS10_DIS (SUPC_SR_WKUPIS10_DIS_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS10_EN (SUPC_SR_WKUPIS10_EN_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS11_Pos 27 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS11_Msk (_U_(0x1) << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS11 SUPC_SR_WKUPIS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS11_Msk instead */
#define SUPC_SR_WKUPIS11_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS11_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS11_DIS (SUPC_SR_WKUPIS11_DIS_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS11_EN (SUPC_SR_WKUPIS11_EN_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS12_Pos 28 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS12_Msk (_U_(0x1) << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS12 SUPC_SR_WKUPIS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS12_Msk instead */
#define SUPC_SR_WKUPIS12_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS12_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS12_DIS (SUPC_SR_WKUPIS12_DIS_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS12_EN (SUPC_SR_WKUPIS12_EN_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_WKUPIS13_Pos 29 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */
#define SUPC_SR_WKUPIS13_Msk (_U_(0x1) << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */
#define SUPC_SR_WKUPIS13 SUPC_SR_WKUPIS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS13_Msk instead */
#define SUPC_SR_WKUPIS13_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
#define SUPC_SR_WKUPIS13_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
#define SUPC_SR_WKUPIS13_DIS (SUPC_SR_WKUPIS13_DIS_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */
#define SUPC_SR_WKUPIS13_EN (SUPC_SR_WKUPIS13_EN_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */
#define SUPC_SR_MASK _U_(0x3FFF60FE) /**< \deprecated (SUPC_SR) Register MASK (Use SUPC_SR_Msk instead) */
#define SUPC_SR_Msk _U_(0x3FFF60FE) /**< (SUPC_SR) Register Mask */
#define SUPC_SR_LPDBCS_Pos 13 /**< (SUPC_SR Position) Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */
#define SUPC_SR_LPDBCS_Msk (_U_(0x3) << SUPC_SR_LPDBCS_Pos) /**< (SUPC_SR Mask) LPDBCS */
#define SUPC_SR_LPDBCS(value) (SUPC_SR_LPDBCS_Msk & ((value) << SUPC_SR_LPDBCS_Pos))
#define SUPC_SR_WKUPIS_Pos 16 /**< (SUPC_SR Position) WKUPx Input Status (cleared on read) */
#define SUPC_SR_WKUPIS_Msk (_U_(0x3FFF) << SUPC_SR_WKUPIS_Pos) /**< (SUPC_SR Mask) WKUPIS */
#define SUPC_SR_WKUPIS(value) (SUPC_SR_WKUPIS_Msk & ((value) << SUPC_SR_WKUPIS_Pos))
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief SUPC hardware registers */
typedef struct {
__O uint32_t SUPC_CR; /**< (SUPC Offset: 0x00) Supply Controller Control Register */
__IO uint32_t SUPC_SMMR; /**< (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register */
__IO uint32_t SUPC_MR; /**< (SUPC Offset: 0x08) Supply Controller Mode Register */
__IO uint32_t SUPC_WUMR; /**< (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register */
__IO uint32_t SUPC_WUIR; /**< (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register */
__I uint32_t SUPC_SR; /**< (SUPC Offset: 0x14) Supply Controller Status Register */
} Supc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief SUPC hardware registers */
typedef struct {
__O SUPC_CR_Type SUPC_CR; /**< Offset: 0x00 ( /W 32) Supply Controller Control Register */
__IO SUPC_SMMR_Type SUPC_SMMR; /**< Offset: 0x04 (R/W 32) Supply Controller Supply Monitor Mode Register */
__IO SUPC_MR_Type SUPC_MR; /**< Offset: 0x08 (R/W 32) Supply Controller Mode Register */
__IO SUPC_WUMR_Type SUPC_WUMR; /**< Offset: 0x0C (R/W 32) Supply Controller Wake-up Mode Register */
__IO SUPC_WUIR_Type SUPC_WUIR; /**< Offset: 0x10 (R/W 32) Supply Controller Wake-up Inputs Register */
__I SUPC_SR_Type SUPC_SR; /**< Offset: 0x14 (R/ 32) Supply Controller Status Register */
} Supc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Supply Controller */
#endif /* _SAME70_SUPC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for TC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TC_COMPONENT_H_
#define _SAME70_TC_COMPONENT_H_
#define _SAME70_TC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Timer Counter
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TC */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define TC_6082 /**< (TC) Module ID */
#define REV_TC ZG /**< (TC) Module revision */
/* -------- TC_CCR : (TC Offset: 0x00) (/W 32) Channel Control Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CLKEN:1; /**< bit: 0 Counter Clock Enable Command */
uint32_t CLKDIS:1; /**< bit: 1 Counter Clock Disable Command */
uint32_t SWTRG:1; /**< bit: 2 Software Trigger Command */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_CCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CCR_OFFSET (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */
#define TC_CCR_CLKEN_Pos 0 /**< (TC_CCR) Counter Clock Enable Command Position */
#define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */
#define TC_CCR_CLKEN TC_CCR_CLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKEN_Msk instead */
#define TC_CCR_CLKDIS_Pos 1 /**< (TC_CCR) Counter Clock Disable Command Position */
#define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */
#define TC_CCR_CLKDIS TC_CCR_CLKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKDIS_Msk instead */
#define TC_CCR_SWTRG_Pos 2 /**< (TC_CCR) Software Trigger Command Position */
#define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */
#define TC_CCR_SWTRG TC_CCR_SWTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_SWTRG_Msk instead */
#define TC_CCR_MASK _U_(0x07) /**< \deprecated (TC_CCR) Register MASK (Use TC_CCR_Msk instead) */
#define TC_CCR_Msk _U_(0x07) /**< (TC_CCR) Register Mask */
/* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TCCLKS:3; /**< bit: 0..2 Clock Selection */
uint32_t CLKI:1; /**< bit: 3 Clock Invert */
uint32_t BURST:2; /**< bit: 4..5 Burst Signal Selection */
uint32_t LDBSTOP:1; /**< bit: 6 Counter Clock Stopped with RB Loading */
uint32_t LDBDIS:1; /**< bit: 7 Counter Clock Disable with RB Loading */
uint32_t ETRGEDG:2; /**< bit: 8..9 External Trigger Edge Selection */
uint32_t ABETRG:1; /**< bit: 10 TIOAx or TIOBx External Trigger Selection */
uint32_t :3; /**< bit: 11..13 Reserved */
uint32_t CPCTRG:1; /**< bit: 14 RC Compare Trigger Enable */
uint32_t WAVE:1; /**< bit: 15 Waveform Mode */
uint32_t LDRA:2; /**< bit: 16..17 RA Loading Edge Selection */
uint32_t LDRB:2; /**< bit: 18..19 RB Loading Edge Selection */
uint32_t SBSMPLR:3; /**< bit: 20..22 Loading Edge Subsampling Ratio */
uint32_t :9; /**< bit: 23..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_CMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CMR_OFFSET (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */
#define TC_CMR_TCCLKS_Pos 0 /**< (TC_CMR) Clock Selection Position */
#define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */
#define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))
#define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */
#define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */
#define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */
#define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */
#define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */
#define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */
#define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */
#define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */
#define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */
#define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */
#define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */
#define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */
#define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */
#define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */
#define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */
#define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */
#define TC_CMR_CLKI_Pos 3 /**< (TC_CMR) Clock Invert Position */
#define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */
#define TC_CMR_CLKI TC_CMR_CLKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CLKI_Msk instead */
#define TC_CMR_BURST_Pos 4 /**< (TC_CMR) Burst Signal Selection Position */
#define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */
#define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))
#define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */
#define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */
#define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */
#define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */
#define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */
#define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */
#define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */
#define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */
#define TC_CMR_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */
#define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */
#define TC_CMR_LDBSTOP TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */
#define TC_CMR_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */
#define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */
#define TC_CMR_LDBDIS TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */
#define TC_CMR_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */
#define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */
#define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))
#define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */
#define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */
#define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */
#define TC_CMR_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */
#define TC_CMR_ETRGEDG_NONE (TC_CMR_ETRGEDG_NONE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */
#define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */
#define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */
#define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */
#define TC_CMR_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */
#define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */
#define TC_CMR_ABETRG TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */
#define TC_CMR_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */
#define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */
#define TC_CMR_CPCTRG TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */
#define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */
#define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */
#define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */
#define TC_CMR_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */
#define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */
#define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))
#define TC_CMR_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */
#define TC_CMR_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */
#define TC_CMR_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */
#define TC_CMR_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */
#define TC_CMR_LDRA_NONE (TC_CMR_LDRA_NONE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) None Position */
#define TC_CMR_LDRA_RISING (TC_CMR_LDRA_RISING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */
#define TC_CMR_LDRA_FALLING (TC_CMR_LDRA_FALLING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */
#define TC_CMR_LDRA_EDGE (TC_CMR_LDRA_EDGE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */
#define TC_CMR_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */
#define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */
#define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))
#define TC_CMR_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */
#define TC_CMR_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */
#define TC_CMR_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */
#define TC_CMR_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */
#define TC_CMR_LDRB_NONE (TC_CMR_LDRB_NONE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) None Position */
#define TC_CMR_LDRB_RISING (TC_CMR_LDRB_RISING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */
#define TC_CMR_LDRB_FALLING (TC_CMR_LDRB_FALLING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */
#define TC_CMR_LDRB_EDGE (TC_CMR_LDRB_EDGE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */
#define TC_CMR_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */
#define TC_CMR_SBSMPLR_Msk (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */
#define TC_CMR_SBSMPLR(value) (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))
#define TC_CMR_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */
#define TC_CMR_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */
#define TC_CMR_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */
#define TC_CMR_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */
#define TC_CMR_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */
#define TC_CMR_SBSMPLR_ONE (TC_CMR_SBSMPLR_ONE_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */
#define TC_CMR_SBSMPLR_HALF (TC_CMR_SBSMPLR_HALF_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */
#define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */
#define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */
#define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */
#define TC_CMR_MASK _U_(0x7FC7FF) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */
#define TC_CMR_Msk _U_(0x7FC7FF) /**< (TC_CMR) Register Mask */
/* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GCEN:1; /**< bit: 0 Gray Count Enable */
uint32_t DOWN:1; /**< bit: 1 Down Count */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_SMMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_SMMR_OFFSET (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */
#define TC_SMMR_GCEN_Pos 0 /**< (TC_SMMR) Gray Count Enable Position */
#define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */
#define TC_SMMR_GCEN TC_SMMR_GCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_GCEN_Msk instead */
#define TC_SMMR_DOWN_Pos 1 /**< (TC_SMMR) Down Count Position */
#define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */
#define TC_SMMR_DOWN TC_SMMR_DOWN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_DOWN_Msk instead */
#define TC_SMMR_MASK _U_(0x03) /**< \deprecated (TC_SMMR) Register MASK (Use TC_SMMR_Msk instead) */
#define TC_SMMR_Msk _U_(0x03) /**< (TC_SMMR) Register Mask */
/* -------- TC_RAB : (TC Offset: 0x0c) (R/ 32) Register AB (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RAB:32; /**< bit: 0..31 Register A or Register B */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_RAB_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_RAB_OFFSET (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */
#define TC_RAB_RAB_Pos 0 /**< (TC_RAB) Register A or Register B Position */
#define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */
#define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos))
#define TC_RAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RAB) Register MASK (Use TC_RAB_Msk instead) */
#define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */
/* -------- TC_CV : (TC Offset: 0x10) (R/ 32) Counter Value (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CV:32; /**< bit: 0..31 Counter Value */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_CV_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CV_OFFSET (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */
#define TC_CV_CV_Pos 0 /**< (TC_CV) Counter Value Position */
#define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */
#define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos))
#define TC_CV_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_CV) Register MASK (Use TC_CV_Msk instead) */
#define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */
/* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RA:32; /**< bit: 0..31 Register A */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_RA_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_RA_OFFSET (0x14) /**< (TC_RA) Register A (channel = 0) Offset */
#define TC_RA_RA_Pos 0 /**< (TC_RA) Register A Position */
#define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */
#define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))
#define TC_RA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RA) Register MASK (Use TC_RA_Msk instead) */
#define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */
/* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RB:32; /**< bit: 0..31 Register B */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_RB_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_RB_OFFSET (0x18) /**< (TC_RB) Register B (channel = 0) Offset */
#define TC_RB_RB_Pos 0 /**< (TC_RB) Register B Position */
#define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */
#define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))
#define TC_RB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RB) Register MASK (Use TC_RB_Msk instead) */
#define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */
/* -------- TC_RC : (TC Offset: 0x1c) (R/W 32) Register C (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RC:32; /**< bit: 0..31 Register C */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_RC_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_RC_OFFSET (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */
#define TC_RC_RC_Pos 0 /**< (TC_RC) Register C Position */
#define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */
#define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))
#define TC_RC_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RC) Register MASK (Use TC_RC_Msk instead) */
#define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */
/* -------- TC_SR : (TC Offset: 0x20) (R/ 32) Status Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COVFS:1; /**< bit: 0 Counter Overflow Status (cleared on read) */
uint32_t LOVRS:1; /**< bit: 1 Load Overrun Status (cleared on read) */
uint32_t CPAS:1; /**< bit: 2 RA Compare Status (cleared on read) */
uint32_t CPBS:1; /**< bit: 3 RB Compare Status (cleared on read) */
uint32_t CPCS:1; /**< bit: 4 RC Compare Status (cleared on read) */
uint32_t LDRAS:1; /**< bit: 5 RA Loading Status (cleared on read) */
uint32_t LDRBS:1; /**< bit: 6 RB Loading Status (cleared on read) */
uint32_t ETRGS:1; /**< bit: 7 External Trigger Status (cleared on read) */
uint32_t :8; /**< bit: 8..15 Reserved */
uint32_t CLKSTA:1; /**< bit: 16 Clock Enabling Status */
uint32_t MTIOA:1; /**< bit: 17 TIOAx Mirror */
uint32_t MTIOB:1; /**< bit: 18 TIOBx Mirror */
uint32_t :13; /**< bit: 19..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_SR_OFFSET (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */
#define TC_SR_COVFS_Pos 0 /**< (TC_SR) Counter Overflow Status (cleared on read) Position */
#define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */
#define TC_SR_COVFS TC_SR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_COVFS_Msk instead */
#define TC_SR_LOVRS_Pos 1 /**< (TC_SR) Load Overrun Status (cleared on read) Position */
#define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */
#define TC_SR_LOVRS TC_SR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LOVRS_Msk instead */
#define TC_SR_CPAS_Pos 2 /**< (TC_SR) RA Compare Status (cleared on read) Position */
#define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */
#define TC_SR_CPAS TC_SR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPAS_Msk instead */
#define TC_SR_CPBS_Pos 3 /**< (TC_SR) RB Compare Status (cleared on read) Position */
#define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */
#define TC_SR_CPBS TC_SR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPBS_Msk instead */
#define TC_SR_CPCS_Pos 4 /**< (TC_SR) RC Compare Status (cleared on read) Position */
#define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */
#define TC_SR_CPCS TC_SR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPCS_Msk instead */
#define TC_SR_LDRAS_Pos 5 /**< (TC_SR) RA Loading Status (cleared on read) Position */
#define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */
#define TC_SR_LDRAS TC_SR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRAS_Msk instead */
#define TC_SR_LDRBS_Pos 6 /**< (TC_SR) RB Loading Status (cleared on read) Position */
#define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */
#define TC_SR_LDRBS TC_SR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRBS_Msk instead */
#define TC_SR_ETRGS_Pos 7 /**< (TC_SR) External Trigger Status (cleared on read) Position */
#define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */
#define TC_SR_ETRGS TC_SR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_ETRGS_Msk instead */
#define TC_SR_CLKSTA_Pos 16 /**< (TC_SR) Clock Enabling Status Position */
#define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */
#define TC_SR_CLKSTA TC_SR_CLKSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CLKSTA_Msk instead */
#define TC_SR_MTIOA_Pos 17 /**< (TC_SR) TIOAx Mirror Position */
#define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */
#define TC_SR_MTIOA TC_SR_MTIOA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOA_Msk instead */
#define TC_SR_MTIOB_Pos 18 /**< (TC_SR) TIOBx Mirror Position */
#define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */
#define TC_SR_MTIOB TC_SR_MTIOB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOB_Msk instead */
#define TC_SR_MASK _U_(0x700FF) /**< \deprecated (TC_SR) Register MASK (Use TC_SR_Msk instead) */
#define TC_SR_Msk _U_(0x700FF) /**< (TC_SR) Register Mask */
/* -------- TC_IER : (TC Offset: 0x24) (/W 32) Interrupt Enable Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COVFS:1; /**< bit: 0 Counter Overflow */
uint32_t LOVRS:1; /**< bit: 1 Load Overrun */
uint32_t CPAS:1; /**< bit: 2 RA Compare */
uint32_t CPBS:1; /**< bit: 3 RB Compare */
uint32_t CPCS:1; /**< bit: 4 RC Compare */
uint32_t LDRAS:1; /**< bit: 5 RA Loading */
uint32_t LDRBS:1; /**< bit: 6 RB Loading */
uint32_t ETRGS:1; /**< bit: 7 External Trigger */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_IER_OFFSET (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */
#define TC_IER_COVFS_Pos 0 /**< (TC_IER) Counter Overflow Position */
#define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */
#define TC_IER_COVFS TC_IER_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_COVFS_Msk instead */
#define TC_IER_LOVRS_Pos 1 /**< (TC_IER) Load Overrun Position */
#define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */
#define TC_IER_LOVRS TC_IER_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LOVRS_Msk instead */
#define TC_IER_CPAS_Pos 2 /**< (TC_IER) RA Compare Position */
#define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */
#define TC_IER_CPAS TC_IER_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPAS_Msk instead */
#define TC_IER_CPBS_Pos 3 /**< (TC_IER) RB Compare Position */
#define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */
#define TC_IER_CPBS TC_IER_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPBS_Msk instead */
#define TC_IER_CPCS_Pos 4 /**< (TC_IER) RC Compare Position */
#define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */
#define TC_IER_CPCS TC_IER_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPCS_Msk instead */
#define TC_IER_LDRAS_Pos 5 /**< (TC_IER) RA Loading Position */
#define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */
#define TC_IER_LDRAS TC_IER_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRAS_Msk instead */
#define TC_IER_LDRBS_Pos 6 /**< (TC_IER) RB Loading Position */
#define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */
#define TC_IER_LDRBS TC_IER_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRBS_Msk instead */
#define TC_IER_ETRGS_Pos 7 /**< (TC_IER) External Trigger Position */
#define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */
#define TC_IER_ETRGS TC_IER_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_ETRGS_Msk instead */
#define TC_IER_MASK _U_(0xFF) /**< \deprecated (TC_IER) Register MASK (Use TC_IER_Msk instead) */
#define TC_IER_Msk _U_(0xFF) /**< (TC_IER) Register Mask */
/* -------- TC_IDR : (TC Offset: 0x28) (/W 32) Interrupt Disable Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COVFS:1; /**< bit: 0 Counter Overflow */
uint32_t LOVRS:1; /**< bit: 1 Load Overrun */
uint32_t CPAS:1; /**< bit: 2 RA Compare */
uint32_t CPBS:1; /**< bit: 3 RB Compare */
uint32_t CPCS:1; /**< bit: 4 RC Compare */
uint32_t LDRAS:1; /**< bit: 5 RA Loading */
uint32_t LDRBS:1; /**< bit: 6 RB Loading */
uint32_t ETRGS:1; /**< bit: 7 External Trigger */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_IDR_OFFSET (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */
#define TC_IDR_COVFS_Pos 0 /**< (TC_IDR) Counter Overflow Position */
#define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */
#define TC_IDR_COVFS TC_IDR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_COVFS_Msk instead */
#define TC_IDR_LOVRS_Pos 1 /**< (TC_IDR) Load Overrun Position */
#define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */
#define TC_IDR_LOVRS TC_IDR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LOVRS_Msk instead */
#define TC_IDR_CPAS_Pos 2 /**< (TC_IDR) RA Compare Position */
#define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */
#define TC_IDR_CPAS TC_IDR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPAS_Msk instead */
#define TC_IDR_CPBS_Pos 3 /**< (TC_IDR) RB Compare Position */
#define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */
#define TC_IDR_CPBS TC_IDR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPBS_Msk instead */
#define TC_IDR_CPCS_Pos 4 /**< (TC_IDR) RC Compare Position */
#define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */
#define TC_IDR_CPCS TC_IDR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPCS_Msk instead */
#define TC_IDR_LDRAS_Pos 5 /**< (TC_IDR) RA Loading Position */
#define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */
#define TC_IDR_LDRAS TC_IDR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRAS_Msk instead */
#define TC_IDR_LDRBS_Pos 6 /**< (TC_IDR) RB Loading Position */
#define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */
#define TC_IDR_LDRBS TC_IDR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRBS_Msk instead */
#define TC_IDR_ETRGS_Pos 7 /**< (TC_IDR) External Trigger Position */
#define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */
#define TC_IDR_ETRGS TC_IDR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_ETRGS_Msk instead */
#define TC_IDR_MASK _U_(0xFF) /**< \deprecated (TC_IDR) Register MASK (Use TC_IDR_Msk instead) */
#define TC_IDR_Msk _U_(0xFF) /**< (TC_IDR) Register Mask */
/* -------- TC_IMR : (TC Offset: 0x2c) (R/ 32) Interrupt Mask Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COVFS:1; /**< bit: 0 Counter Overflow */
uint32_t LOVRS:1; /**< bit: 1 Load Overrun */
uint32_t CPAS:1; /**< bit: 2 RA Compare */
uint32_t CPBS:1; /**< bit: 3 RB Compare */
uint32_t CPCS:1; /**< bit: 4 RC Compare */
uint32_t LDRAS:1; /**< bit: 5 RA Loading */
uint32_t LDRBS:1; /**< bit: 6 RB Loading */
uint32_t ETRGS:1; /**< bit: 7 External Trigger */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_IMR_OFFSET (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */
#define TC_IMR_COVFS_Pos 0 /**< (TC_IMR) Counter Overflow Position */
#define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */
#define TC_IMR_COVFS TC_IMR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_COVFS_Msk instead */
#define TC_IMR_LOVRS_Pos 1 /**< (TC_IMR) Load Overrun Position */
#define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */
#define TC_IMR_LOVRS TC_IMR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LOVRS_Msk instead */
#define TC_IMR_CPAS_Pos 2 /**< (TC_IMR) RA Compare Position */
#define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */
#define TC_IMR_CPAS TC_IMR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPAS_Msk instead */
#define TC_IMR_CPBS_Pos 3 /**< (TC_IMR) RB Compare Position */
#define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */
#define TC_IMR_CPBS TC_IMR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPBS_Msk instead */
#define TC_IMR_CPCS_Pos 4 /**< (TC_IMR) RC Compare Position */
#define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */
#define TC_IMR_CPCS TC_IMR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPCS_Msk instead */
#define TC_IMR_LDRAS_Pos 5 /**< (TC_IMR) RA Loading Position */
#define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */
#define TC_IMR_LDRAS TC_IMR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRAS_Msk instead */
#define TC_IMR_LDRBS_Pos 6 /**< (TC_IMR) RB Loading Position */
#define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */
#define TC_IMR_LDRBS TC_IMR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRBS_Msk instead */
#define TC_IMR_ETRGS_Pos 7 /**< (TC_IMR) External Trigger Position */
#define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */
#define TC_IMR_ETRGS TC_IMR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_ETRGS_Msk instead */
#define TC_IMR_MASK _U_(0xFF) /**< \deprecated (TC_IMR) Register MASK (Use TC_IMR_Msk instead) */
#define TC_IMR_Msk _U_(0xFF) /**< (TC_IMR) Register Mask */
/* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TRIGSRCA:2; /**< bit: 0..1 Trigger Source for Input A */
uint32_t :2; /**< bit: 2..3 Reserved */
uint32_t TRIGSRCB:2; /**< bit: 4..5 Trigger Source for Input B */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t NODIVCLK:1; /**< bit: 8 No Divided Clock */
uint32_t :23; /**< bit: 9..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_EMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_EMR_OFFSET (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */
#define TC_EMR_TRIGSRCA_Pos 0 /**< (TC_EMR) Trigger Source for Input A Position */
#define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */
#define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))
#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */
#define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */
#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */
#define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */
#define TC_EMR_TRIGSRCB_Pos 4 /**< (TC_EMR) Trigger Source for Input B Position */
#define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */
#define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))
#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */
#define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */
#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */
#define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */
#define TC_EMR_NODIVCLK_Pos 8 /**< (TC_EMR) No Divided Clock Position */
#define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */
#define TC_EMR_NODIVCLK TC_EMR_NODIVCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_EMR_NODIVCLK_Msk instead */
#define TC_EMR_MASK _U_(0x133) /**< \deprecated (TC_EMR) Register MASK (Use TC_EMR_Msk instead) */
#define TC_EMR_Msk _U_(0x133) /**< (TC_EMR) Register Mask */
/* -------- TC_BCR : (TC Offset: 0xc0) (/W 32) Block Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SYNC:1; /**< bit: 0 Synchro Command */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_BCR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_BCR_OFFSET (0xC0) /**< (TC_BCR) Block Control Register Offset */
#define TC_BCR_SYNC_Pos 0 /**< (TC_BCR) Synchro Command Position */
#define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */
#define TC_BCR_SYNC TC_BCR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BCR_SYNC_Msk instead */
#define TC_BCR_MASK _U_(0x01) /**< \deprecated (TC_BCR) Register MASK (Use TC_BCR_Msk instead) */
#define TC_BCR_Msk _U_(0x01) /**< (TC_BCR) Register Mask */
/* -------- TC_BMR : (TC Offset: 0xc4) (R/W 32) Block Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TC0XC0S:2; /**< bit: 0..1 External Clock Signal 0 Selection */
uint32_t TC1XC1S:2; /**< bit: 2..3 External Clock Signal 1 Selection */
uint32_t TC2XC2S:2; /**< bit: 4..5 External Clock Signal 2 Selection */
uint32_t :2; /**< bit: 6..7 Reserved */
uint32_t QDEN:1; /**< bit: 8 Quadrature Decoder Enabled */
uint32_t POSEN:1; /**< bit: 9 Position Enabled */
uint32_t SPEEDEN:1; /**< bit: 10 Speed Enabled */
uint32_t QDTRANS:1; /**< bit: 11 Quadrature Decoding Transparent */
uint32_t EDGPHA:1; /**< bit: 12 Edge on PHA Count Mode */
uint32_t INVA:1; /**< bit: 13 Inverted PHA */
uint32_t INVB:1; /**< bit: 14 Inverted PHB */
uint32_t INVIDX:1; /**< bit: 15 Inverted Index */
uint32_t SWAP:1; /**< bit: 16 Swap PHA and PHB */
uint32_t IDXPHB:1; /**< bit: 17 Index Pin is PHB Pin */
uint32_t :2; /**< bit: 18..19 Reserved */
uint32_t MAXFILT:6; /**< bit: 20..25 Maximum Filter */
uint32_t :6; /**< bit: 26..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_BMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_BMR_OFFSET (0xC4) /**< (TC_BMR) Block Mode Register Offset */
#define TC_BMR_TC0XC0S_Pos 0 /**< (TC_BMR) External Clock Signal 0 Selection Position */
#define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */
#define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))
#define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */
#define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */
#define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */
#define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */
#define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */
#define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */
#define TC_BMR_TC1XC1S_Pos 2 /**< (TC_BMR) External Clock Signal 1 Selection Position */
#define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */
#define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))
#define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */
#define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */
#define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */
#define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */
#define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */
#define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */
#define TC_BMR_TC2XC2S_Pos 4 /**< (TC_BMR) External Clock Signal 2 Selection Position */
#define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */
#define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))
#define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */
#define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */
#define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */
#define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */
#define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */
#define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */
#define TC_BMR_QDEN_Pos 8 /**< (TC_BMR) Quadrature Decoder Enabled Position */
#define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */
#define TC_BMR_QDEN TC_BMR_QDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDEN_Msk instead */
#define TC_BMR_POSEN_Pos 9 /**< (TC_BMR) Position Enabled Position */
#define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */
#define TC_BMR_POSEN TC_BMR_POSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_POSEN_Msk instead */
#define TC_BMR_SPEEDEN_Pos 10 /**< (TC_BMR) Speed Enabled Position */
#define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */
#define TC_BMR_SPEEDEN TC_BMR_SPEEDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SPEEDEN_Msk instead */
#define TC_BMR_QDTRANS_Pos 11 /**< (TC_BMR) Quadrature Decoding Transparent Position */
#define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */
#define TC_BMR_QDTRANS TC_BMR_QDTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDTRANS_Msk instead */
#define TC_BMR_EDGPHA_Pos 12 /**< (TC_BMR) Edge on PHA Count Mode Position */
#define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */
#define TC_BMR_EDGPHA TC_BMR_EDGPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_EDGPHA_Msk instead */
#define TC_BMR_INVA_Pos 13 /**< (TC_BMR) Inverted PHA Position */
#define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */
#define TC_BMR_INVA TC_BMR_INVA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVA_Msk instead */
#define TC_BMR_INVB_Pos 14 /**< (TC_BMR) Inverted PHB Position */
#define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */
#define TC_BMR_INVB TC_BMR_INVB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVB_Msk instead */
#define TC_BMR_INVIDX_Pos 15 /**< (TC_BMR) Inverted Index Position */
#define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */
#define TC_BMR_INVIDX TC_BMR_INVIDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVIDX_Msk instead */
#define TC_BMR_SWAP_Pos 16 /**< (TC_BMR) Swap PHA and PHB Position */
#define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */
#define TC_BMR_SWAP TC_BMR_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SWAP_Msk instead */
#define TC_BMR_IDXPHB_Pos 17 /**< (TC_BMR) Index Pin is PHB Pin Position */
#define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */
#define TC_BMR_IDXPHB TC_BMR_IDXPHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_IDXPHB_Msk instead */
#define TC_BMR_MAXFILT_Pos 20 /**< (TC_BMR) Maximum Filter Position */
#define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */
#define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))
#define TC_BMR_MASK _U_(0x3F3FF3F) /**< \deprecated (TC_BMR) Register MASK (Use TC_BMR_Msk instead) */
#define TC_BMR_Msk _U_(0x3F3FF3F) /**< (TC_BMR) Register Mask */
/* -------- TC_QIER : (TC Offset: 0xc8) (/W 32) QDEC Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IDX:1; /**< bit: 0 Index */
uint32_t DIRCHG:1; /**< bit: 1 Direction Change */
uint32_t QERR:1; /**< bit: 2 Quadrature Error */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_QIER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_QIER_OFFSET (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */
#define TC_QIER_IDX_Pos 0 /**< (TC_QIER) Index Position */
#define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */
#define TC_QIER_IDX TC_QIER_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_IDX_Msk instead */
#define TC_QIER_DIRCHG_Pos 1 /**< (TC_QIER) Direction Change Position */
#define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */
#define TC_QIER_DIRCHG TC_QIER_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_DIRCHG_Msk instead */
#define TC_QIER_QERR_Pos 2 /**< (TC_QIER) Quadrature Error Position */
#define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */
#define TC_QIER_QERR TC_QIER_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_QERR_Msk instead */
#define TC_QIER_MASK _U_(0x07) /**< \deprecated (TC_QIER) Register MASK (Use TC_QIER_Msk instead) */
#define TC_QIER_Msk _U_(0x07) /**< (TC_QIER) Register Mask */
/* -------- TC_QIDR : (TC Offset: 0xcc) (/W 32) QDEC Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IDX:1; /**< bit: 0 Index */
uint32_t DIRCHG:1; /**< bit: 1 Direction Change */
uint32_t QERR:1; /**< bit: 2 Quadrature Error */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_QIDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_QIDR_OFFSET (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */
#define TC_QIDR_IDX_Pos 0 /**< (TC_QIDR) Index Position */
#define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */
#define TC_QIDR_IDX TC_QIDR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_IDX_Msk instead */
#define TC_QIDR_DIRCHG_Pos 1 /**< (TC_QIDR) Direction Change Position */
#define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */
#define TC_QIDR_DIRCHG TC_QIDR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_DIRCHG_Msk instead */
#define TC_QIDR_QERR_Pos 2 /**< (TC_QIDR) Quadrature Error Position */
#define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */
#define TC_QIDR_QERR TC_QIDR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_QERR_Msk instead */
#define TC_QIDR_MASK _U_(0x07) /**< \deprecated (TC_QIDR) Register MASK (Use TC_QIDR_Msk instead) */
#define TC_QIDR_Msk _U_(0x07) /**< (TC_QIDR) Register Mask */
/* -------- TC_QIMR : (TC Offset: 0xd0) (R/ 32) QDEC Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IDX:1; /**< bit: 0 Index */
uint32_t DIRCHG:1; /**< bit: 1 Direction Change */
uint32_t QERR:1; /**< bit: 2 Quadrature Error */
uint32_t :29; /**< bit: 3..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_QIMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_QIMR_OFFSET (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */
#define TC_QIMR_IDX_Pos 0 /**< (TC_QIMR) Index Position */
#define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */
#define TC_QIMR_IDX TC_QIMR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_IDX_Msk instead */
#define TC_QIMR_DIRCHG_Pos 1 /**< (TC_QIMR) Direction Change Position */
#define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */
#define TC_QIMR_DIRCHG TC_QIMR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_DIRCHG_Msk instead */
#define TC_QIMR_QERR_Pos 2 /**< (TC_QIMR) Quadrature Error Position */
#define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */
#define TC_QIMR_QERR TC_QIMR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_QERR_Msk instead */
#define TC_QIMR_MASK _U_(0x07) /**< \deprecated (TC_QIMR) Register MASK (Use TC_QIMR_Msk instead) */
#define TC_QIMR_Msk _U_(0x07) /**< (TC_QIMR) Register Mask */
/* -------- TC_QISR : (TC Offset: 0xd4) (R/ 32) QDEC Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IDX:1; /**< bit: 0 Index */
uint32_t DIRCHG:1; /**< bit: 1 Direction Change */
uint32_t QERR:1; /**< bit: 2 Quadrature Error */
uint32_t :5; /**< bit: 3..7 Reserved */
uint32_t DIR:1; /**< bit: 8 Direction */
uint32_t :23; /**< bit: 9..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_QISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_QISR_OFFSET (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */
#define TC_QISR_IDX_Pos 0 /**< (TC_QISR) Index Position */
#define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */
#define TC_QISR_IDX TC_QISR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_IDX_Msk instead */
#define TC_QISR_DIRCHG_Pos 1 /**< (TC_QISR) Direction Change Position */
#define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */
#define TC_QISR_DIRCHG TC_QISR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIRCHG_Msk instead */
#define TC_QISR_QERR_Pos 2 /**< (TC_QISR) Quadrature Error Position */
#define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */
#define TC_QISR_QERR TC_QISR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_QERR_Msk instead */
#define TC_QISR_DIR_Pos 8 /**< (TC_QISR) Direction Position */
#define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */
#define TC_QISR_DIR TC_QISR_DIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIR_Msk instead */
#define TC_QISR_MASK _U_(0x107) /**< \deprecated (TC_QISR) Register MASK (Use TC_QISR_Msk instead) */
#define TC_QISR_Msk _U_(0x107) /**< (TC_QISR) Register Mask */
/* -------- TC_FMR : (TC Offset: 0xd8) (R/W 32) Fault Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENCF0:1; /**< bit: 0 Enable Compare Fault Channel 0 */
uint32_t ENCF1:1; /**< bit: 1 Enable Compare Fault Channel 1 */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
struct {
uint32_t ENCF:2; /**< bit: 0..1 Enable Compare Fault Channel x */
uint32_t :30; /**< bit: 2..31 Reserved */
} vec; /**< Structure used for vec access */
uint32_t reg; /**< Type used for register access */
} TC_FMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_FMR_OFFSET (0xD8) /**< (TC_FMR) Fault Mode Register Offset */
#define TC_FMR_ENCF0_Pos 0 /**< (TC_FMR) Enable Compare Fault Channel 0 Position */
#define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */
#define TC_FMR_ENCF0 TC_FMR_ENCF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF0_Msk instead */
#define TC_FMR_ENCF1_Pos 1 /**< (TC_FMR) Enable Compare Fault Channel 1 Position */
#define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */
#define TC_FMR_ENCF1 TC_FMR_ENCF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF1_Msk instead */
#define TC_FMR_MASK _U_(0x03) /**< \deprecated (TC_FMR) Register MASK (Use TC_FMR_Msk instead) */
#define TC_FMR_Msk _U_(0x03) /**< (TC_FMR) Register Mask */
#define TC_FMR_ENCF_Pos 0 /**< (TC_FMR Position) Enable Compare Fault Channel x */
#define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */
#define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos))
/* -------- TC_WPMR : (TC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TC_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_WPMR_OFFSET (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */
#define TC_WPMR_WPEN_Pos 0 /**< (TC_WPMR) Write Protection Enable Position */
#define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */
#define TC_WPMR_WPEN TC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_WPMR_WPEN_Msk instead */
#define TC_WPMR_WPKEY_Pos 8 /**< (TC_WPMR) Write Protection Key Position */
#define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */
#define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))
#define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
#define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
#define TC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TC_WPMR) Register MASK (Use TC_WPMR_Msk instead) */
#define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief TC_CHANNEL hardware registers */
typedef struct {
__O uint32_t TC_CCR; /**< (TC_CHANNEL Offset: 0x00) Channel Control Register (channel = 0) */
__IO uint32_t TC_CMR; /**< (TC_CHANNEL Offset: 0x04) Channel Mode Register (channel = 0) */
__IO uint32_t TC_SMMR; /**< (TC_CHANNEL Offset: 0x08) Stepper Motor Mode Register (channel = 0) */
__I uint32_t TC_RAB; /**< (TC_CHANNEL Offset: 0x0C) Register AB (channel = 0) */
__I uint32_t TC_CV; /**< (TC_CHANNEL Offset: 0x10) Counter Value (channel = 0) */
__IO uint32_t TC_RA; /**< (TC_CHANNEL Offset: 0x14) Register A (channel = 0) */
__IO uint32_t TC_RB; /**< (TC_CHANNEL Offset: 0x18) Register B (channel = 0) */
__IO uint32_t TC_RC; /**< (TC_CHANNEL Offset: 0x1C) Register C (channel = 0) */
__I uint32_t TC_SR; /**< (TC_CHANNEL Offset: 0x20) Status Register (channel = 0) */
__O uint32_t TC_IER; /**< (TC_CHANNEL Offset: 0x24) Interrupt Enable Register (channel = 0) */
__O uint32_t TC_IDR; /**< (TC_CHANNEL Offset: 0x28) Interrupt Disable Register (channel = 0) */
__I uint32_t TC_IMR; /**< (TC_CHANNEL Offset: 0x2C) Interrupt Mask Register (channel = 0) */
__IO uint32_t TC_EMR; /**< (TC_CHANNEL Offset: 0x30) Extended Mode Register (channel = 0) */
RoReg8 Reserved1[0x0C];
} TcChannel;
#define TCCHANNEL_NUMBER 3
/** \brief TC hardware registers */
typedef struct {
TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */
__O uint32_t TC_BCR; /**< (TC Offset: 0xC0) Block Control Register */
__IO uint32_t TC_BMR; /**< (TC Offset: 0xC4) Block Mode Register */
__O uint32_t TC_QIER; /**< (TC Offset: 0xC8) QDEC Interrupt Enable Register */
__O uint32_t TC_QIDR; /**< (TC Offset: 0xCC) QDEC Interrupt Disable Register */
__I uint32_t TC_QIMR; /**< (TC Offset: 0xD0) QDEC Interrupt Mask Register */
__I uint32_t TC_QISR; /**< (TC Offset: 0xD4) QDEC Interrupt Status Register */
__IO uint32_t TC_FMR; /**< (TC Offset: 0xD8) Fault Mode Register */
RoReg8 Reserved1[0x8];
__IO uint32_t TC_WPMR; /**< (TC Offset: 0xE4) Write Protection Mode Register */
} Tc;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief TC_CHANNEL hardware registers */
typedef struct {
__O TC_CCR_Type TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */
__IO TC_CMR_Type TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */
__IO TC_SMMR_Type TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */
__I TC_RAB_Type TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */
__I TC_CV_Type TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */
__IO TC_RA_Type TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */
__IO TC_RB_Type TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */
__IO TC_RC_Type TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */
__I TC_SR_Type TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */
__O TC_IER_Type TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */
__O TC_IDR_Type TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */
__I TC_IMR_Type TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */
__IO TC_EMR_Type TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */
RoReg8 Reserved1[0x0C];
} TcChannel;
/** \brief TC hardware registers */
typedef struct {
TcChannel TC_CHANNEL[3]; /**< Offset: 0x00 Channel Control Register (channel = 0) */
__O TC_BCR_Type TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */
__IO TC_BMR_Type TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */
__O TC_QIER_Type TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */
__O TC_QIDR_Type TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */
__I TC_QIMR_Type TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */
__I TC_QISR_Type TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */
__IO TC_FMR_Type TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */
__I uint32_t Reserved1[2];
__IO TC_WPMR_Type TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
} Tc;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Timer Counter */
#endif /* _SAME70_TC_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for TRNG
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TRNG_COMPONENT_H_
#define _SAME70_TRNG_COMPONENT_H_
#define _SAME70_TRNG_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 True Random Number Generator
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TRNG */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define TRNG_6334 /**< (TRNG) Module ID */
#define REV_TRNG G /**< (TRNG) Module revision */
/* -------- TRNG_CR : (TRNG Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /**< bit: 0 Enables the TRNG to Provide Random Values */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t KEY:24; /**< bit: 8..31 Security Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_CR_OFFSET (0x00) /**< (TRNG_CR) Control Register Offset */
#define TRNG_CR_ENABLE_Pos 0 /**< (TRNG_CR) Enables the TRNG to Provide Random Values Position */
#define TRNG_CR_ENABLE_Msk (_U_(0x1) << TRNG_CR_ENABLE_Pos) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Mask */
#define TRNG_CR_ENABLE TRNG_CR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_CR_ENABLE_Msk instead */
#define TRNG_CR_KEY_Pos 8 /**< (TRNG_CR) Security Key Position */
#define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Security Key Mask */
#define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))
#define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */
#define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */
#define TRNG_CR_MASK _U_(0xFFFFFF01) /**< \deprecated (TRNG_CR) Register MASK (Use TRNG_CR_Msk instead) */
#define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */
/* -------- TRNG_IER : (TRNG Offset: 0x10) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_IER_OFFSET (0x10) /**< (TRNG_IER) Interrupt Enable Register Offset */
#define TRNG_IER_DATRDY_Pos 0 /**< (TRNG_IER) Data Ready Interrupt Enable Position */
#define TRNG_IER_DATRDY_Msk (_U_(0x1) << TRNG_IER_DATRDY_Pos) /**< (TRNG_IER) Data Ready Interrupt Enable Mask */
#define TRNG_IER_DATRDY TRNG_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IER_DATRDY_Msk instead */
#define TRNG_IER_MASK _U_(0x01) /**< \deprecated (TRNG_IER) Register MASK (Use TRNG_IER_Msk instead) */
#define TRNG_IER_Msk _U_(0x01) /**< (TRNG_IER) Register Mask */
/* -------- TRNG_IDR : (TRNG Offset: 0x14) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_IDR_OFFSET (0x14) /**< (TRNG_IDR) Interrupt Disable Register Offset */
#define TRNG_IDR_DATRDY_Pos 0 /**< (TRNG_IDR) Data Ready Interrupt Disable Position */
#define TRNG_IDR_DATRDY_Msk (_U_(0x1) << TRNG_IDR_DATRDY_Pos) /**< (TRNG_IDR) Data Ready Interrupt Disable Mask */
#define TRNG_IDR_DATRDY TRNG_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IDR_DATRDY_Msk instead */
#define TRNG_IDR_MASK _U_(0x01) /**< \deprecated (TRNG_IDR) Register MASK (Use TRNG_IDR_Msk instead) */
#define TRNG_IDR_Msk _U_(0x01) /**< (TRNG_IDR) Register Mask */
/* -------- TRNG_IMR : (TRNG Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_IMR_OFFSET (0x18) /**< (TRNG_IMR) Interrupt Mask Register Offset */
#define TRNG_IMR_DATRDY_Pos 0 /**< (TRNG_IMR) Data Ready Interrupt Mask Position */
#define TRNG_IMR_DATRDY_Msk (_U_(0x1) << TRNG_IMR_DATRDY_Pos) /**< (TRNG_IMR) Data Ready Interrupt Mask Mask */
#define TRNG_IMR_DATRDY TRNG_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IMR_DATRDY_Msk instead */
#define TRNG_IMR_MASK _U_(0x01) /**< \deprecated (TRNG_IMR) Register MASK (Use TRNG_IMR_Msk instead) */
#define TRNG_IMR_Msk _U_(0x01) /**< (TRNG_IMR) Register Mask */
/* -------- TRNG_ISR : (TRNG Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATRDY:1; /**< bit: 0 Data Ready */
uint32_t :31; /**< bit: 1..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_ISR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_ISR_OFFSET (0x1C) /**< (TRNG_ISR) Interrupt Status Register Offset */
#define TRNG_ISR_DATRDY_Pos 0 /**< (TRNG_ISR) Data Ready Position */
#define TRNG_ISR_DATRDY_Msk (_U_(0x1) << TRNG_ISR_DATRDY_Pos) /**< (TRNG_ISR) Data Ready Mask */
#define TRNG_ISR_DATRDY TRNG_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_ISR_DATRDY_Msk instead */
#define TRNG_ISR_MASK _U_(0x01) /**< \deprecated (TRNG_ISR) Register MASK (Use TRNG_ISR_Msk instead) */
#define TRNG_ISR_Msk _U_(0x01) /**< (TRNG_ISR) Register Mask */
/* -------- TRNG_ODATA : (TRNG Offset: 0x50) (R/ 32) Output Data Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ODATA:32; /**< bit: 0..31 Output Data */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TRNG_ODATA_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_ODATA_OFFSET (0x50) /**< (TRNG_ODATA) Output Data Register Offset */
#define TRNG_ODATA_ODATA_Pos 0 /**< (TRNG_ODATA) Output Data Position */
#define TRNG_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << TRNG_ODATA_ODATA_Pos) /**< (TRNG_ODATA) Output Data Mask */
#define TRNG_ODATA_ODATA(value) (TRNG_ODATA_ODATA_Msk & ((value) << TRNG_ODATA_ODATA_Pos))
#define TRNG_ODATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TRNG_ODATA) Register MASK (Use TRNG_ODATA_Msk instead) */
#define TRNG_ODATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_ODATA) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief TRNG hardware registers */
typedef struct {
__O uint32_t TRNG_CR; /**< (TRNG Offset: 0x00) Control Register */
RoReg8 Reserved1[0xC];
__O uint32_t TRNG_IER; /**< (TRNG Offset: 0x10) Interrupt Enable Register */
__O uint32_t TRNG_IDR; /**< (TRNG Offset: 0x14) Interrupt Disable Register */
__I uint32_t TRNG_IMR; /**< (TRNG Offset: 0x18) Interrupt Mask Register */
__I uint32_t TRNG_ISR; /**< (TRNG Offset: 0x1C) Interrupt Status Register */
RoReg8 Reserved2[0x30];
__I uint32_t TRNG_ODATA; /**< (TRNG Offset: 0x50) Output Data Register */
} Trng;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief TRNG hardware registers */
typedef struct {
__O TRNG_CR_Type TRNG_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__I uint32_t Reserved1[3];
__O TRNG_IER_Type TRNG_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
__O TRNG_IDR_Type TRNG_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
__I TRNG_IMR_Type TRNG_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
__I TRNG_ISR_Type TRNG_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
__I uint32_t Reserved2[12];
__I TRNG_ODATA_Type TRNG_ODATA; /**< Offset: 0x50 (R/ 32) Output Data Register */
} Trng;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of True Random Number Generator */
#endif /* _SAME70_TRNG_COMPONENT_H_ */

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ext/hal/atmel/asf/sam/include/same70b/component/twihs.h Normal file
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/**
* \file
*
* \brief Component description for TWIHS
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TWIHS_COMPONENT_H_
#define _SAME70_TWIHS_COMPONENT_H_
#define _SAME70_TWIHS_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Two-wire Interface High Speed
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TWIHS */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define TWIHS_11210 /**< (TWIHS) Module ID */
#define REV_TWIHS Z /**< (TWIHS) Module revision */
/* -------- TWIHS_CR : (TWIHS Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t START:1; /**< bit: 0 Send a START Condition */
uint32_t STOP:1; /**< bit: 1 Send a STOP Condition */
uint32_t MSEN:1; /**< bit: 2 TWIHS Master Mode Enabled */
uint32_t MSDIS:1; /**< bit: 3 TWIHS Master Mode Disabled */
uint32_t SVEN:1; /**< bit: 4 TWIHS Slave Mode Enabled */
uint32_t SVDIS:1; /**< bit: 5 TWIHS Slave Mode Disabled */
uint32_t QUICK:1; /**< bit: 6 SMBus Quick Command */
uint32_t SWRST:1; /**< bit: 7 Software Reset */
uint32_t HSEN:1; /**< bit: 8 TWIHS High-Speed Mode Enabled */
uint32_t HSDIS:1; /**< bit: 9 TWIHS High-Speed Mode Disabled */
uint32_t SMBEN:1; /**< bit: 10 SMBus Mode Enabled */
uint32_t SMBDIS:1; /**< bit: 11 SMBus Mode Disabled */
uint32_t PECEN:1; /**< bit: 12 Packet Error Checking Enable */
uint32_t PECDIS:1; /**< bit: 13 Packet Error Checking Disable */
uint32_t PECRQ:1; /**< bit: 14 PEC Request */
uint32_t CLEAR:1; /**< bit: 15 Bus CLEAR Command */
uint32_t ACMEN:1; /**< bit: 16 Alternative Command Mode Enable */
uint32_t ACMDIS:1; /**< bit: 17 Alternative Command Mode Disable */
uint32_t :6; /**< bit: 18..23 Reserved */
uint32_t THRCLR:1; /**< bit: 24 Transmit Holding Register Clear */
uint32_t :1; /**< bit: 25 Reserved */
uint32_t LOCKCLR:1; /**< bit: 26 Lock Clear */
uint32_t :1; /**< bit: 27 Reserved */
uint32_t FIFOEN:1; /**< bit: 28 FIFO Enable */
uint32_t FIFODIS:1; /**< bit: 29 FIFO Disable */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_CR_OFFSET (0x00) /**< (TWIHS_CR) Control Register Offset */
#define TWIHS_CR_START_Pos 0 /**< (TWIHS_CR) Send a START Condition Position */
#define TWIHS_CR_START_Msk (_U_(0x1) << TWIHS_CR_START_Pos) /**< (TWIHS_CR) Send a START Condition Mask */
#define TWIHS_CR_START TWIHS_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_START_Msk instead */
#define TWIHS_CR_STOP_Pos 1 /**< (TWIHS_CR) Send a STOP Condition Position */
#define TWIHS_CR_STOP_Msk (_U_(0x1) << TWIHS_CR_STOP_Pos) /**< (TWIHS_CR) Send a STOP Condition Mask */
#define TWIHS_CR_STOP TWIHS_CR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_STOP_Msk instead */
#define TWIHS_CR_MSEN_Pos 2 /**< (TWIHS_CR) TWIHS Master Mode Enabled Position */
#define TWIHS_CR_MSEN_Msk (_U_(0x1) << TWIHS_CR_MSEN_Pos) /**< (TWIHS_CR) TWIHS Master Mode Enabled Mask */
#define TWIHS_CR_MSEN TWIHS_CR_MSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSEN_Msk instead */
#define TWIHS_CR_MSDIS_Pos 3 /**< (TWIHS_CR) TWIHS Master Mode Disabled Position */
#define TWIHS_CR_MSDIS_Msk (_U_(0x1) << TWIHS_CR_MSDIS_Pos) /**< (TWIHS_CR) TWIHS Master Mode Disabled Mask */
#define TWIHS_CR_MSDIS TWIHS_CR_MSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSDIS_Msk instead */
#define TWIHS_CR_SVEN_Pos 4 /**< (TWIHS_CR) TWIHS Slave Mode Enabled Position */
#define TWIHS_CR_SVEN_Msk (_U_(0x1) << TWIHS_CR_SVEN_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Mask */
#define TWIHS_CR_SVEN TWIHS_CR_SVEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVEN_Msk instead */
#define TWIHS_CR_SVDIS_Pos 5 /**< (TWIHS_CR) TWIHS Slave Mode Disabled Position */
#define TWIHS_CR_SVDIS_Msk (_U_(0x1) << TWIHS_CR_SVDIS_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Mask */
#define TWIHS_CR_SVDIS TWIHS_CR_SVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVDIS_Msk instead */
#define TWIHS_CR_QUICK_Pos 6 /**< (TWIHS_CR) SMBus Quick Command Position */
#define TWIHS_CR_QUICK_Msk (_U_(0x1) << TWIHS_CR_QUICK_Pos) /**< (TWIHS_CR) SMBus Quick Command Mask */
#define TWIHS_CR_QUICK TWIHS_CR_QUICK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_QUICK_Msk instead */
#define TWIHS_CR_SWRST_Pos 7 /**< (TWIHS_CR) Software Reset Position */
#define TWIHS_CR_SWRST_Msk (_U_(0x1) << TWIHS_CR_SWRST_Pos) /**< (TWIHS_CR) Software Reset Mask */
#define TWIHS_CR_SWRST TWIHS_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SWRST_Msk instead */
#define TWIHS_CR_HSEN_Pos 8 /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Position */
#define TWIHS_CR_HSEN_Msk (_U_(0x1) << TWIHS_CR_HSEN_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Mask */
#define TWIHS_CR_HSEN TWIHS_CR_HSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSEN_Msk instead */
#define TWIHS_CR_HSDIS_Pos 9 /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Position */
#define TWIHS_CR_HSDIS_Msk (_U_(0x1) << TWIHS_CR_HSDIS_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Mask */
#define TWIHS_CR_HSDIS TWIHS_CR_HSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSDIS_Msk instead */
#define TWIHS_CR_SMBEN_Pos 10 /**< (TWIHS_CR) SMBus Mode Enabled Position */
#define TWIHS_CR_SMBEN_Msk (_U_(0x1) << TWIHS_CR_SMBEN_Pos) /**< (TWIHS_CR) SMBus Mode Enabled Mask */
#define TWIHS_CR_SMBEN TWIHS_CR_SMBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBEN_Msk instead */
#define TWIHS_CR_SMBDIS_Pos 11 /**< (TWIHS_CR) SMBus Mode Disabled Position */
#define TWIHS_CR_SMBDIS_Msk (_U_(0x1) << TWIHS_CR_SMBDIS_Pos) /**< (TWIHS_CR) SMBus Mode Disabled Mask */
#define TWIHS_CR_SMBDIS TWIHS_CR_SMBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBDIS_Msk instead */
#define TWIHS_CR_PECEN_Pos 12 /**< (TWIHS_CR) Packet Error Checking Enable Position */
#define TWIHS_CR_PECEN_Msk (_U_(0x1) << TWIHS_CR_PECEN_Pos) /**< (TWIHS_CR) Packet Error Checking Enable Mask */
#define TWIHS_CR_PECEN TWIHS_CR_PECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECEN_Msk instead */
#define TWIHS_CR_PECDIS_Pos 13 /**< (TWIHS_CR) Packet Error Checking Disable Position */
#define TWIHS_CR_PECDIS_Msk (_U_(0x1) << TWIHS_CR_PECDIS_Pos) /**< (TWIHS_CR) Packet Error Checking Disable Mask */
#define TWIHS_CR_PECDIS TWIHS_CR_PECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECDIS_Msk instead */
#define TWIHS_CR_PECRQ_Pos 14 /**< (TWIHS_CR) PEC Request Position */
#define TWIHS_CR_PECRQ_Msk (_U_(0x1) << TWIHS_CR_PECRQ_Pos) /**< (TWIHS_CR) PEC Request Mask */
#define TWIHS_CR_PECRQ TWIHS_CR_PECRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECRQ_Msk instead */
#define TWIHS_CR_CLEAR_Pos 15 /**< (TWIHS_CR) Bus CLEAR Command Position */
#define TWIHS_CR_CLEAR_Msk (_U_(0x1) << TWIHS_CR_CLEAR_Pos) /**< (TWIHS_CR) Bus CLEAR Command Mask */
#define TWIHS_CR_CLEAR TWIHS_CR_CLEAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_CLEAR_Msk instead */
#define TWIHS_CR_ACMEN_Pos 16 /**< (TWIHS_CR) Alternative Command Mode Enable Position */
#define TWIHS_CR_ACMEN_Msk (_U_(0x1) << TWIHS_CR_ACMEN_Pos) /**< (TWIHS_CR) Alternative Command Mode Enable Mask */
#define TWIHS_CR_ACMEN TWIHS_CR_ACMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMEN_Msk instead */
#define TWIHS_CR_ACMDIS_Pos 17 /**< (TWIHS_CR) Alternative Command Mode Disable Position */
#define TWIHS_CR_ACMDIS_Msk (_U_(0x1) << TWIHS_CR_ACMDIS_Pos) /**< (TWIHS_CR) Alternative Command Mode Disable Mask */
#define TWIHS_CR_ACMDIS TWIHS_CR_ACMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMDIS_Msk instead */
#define TWIHS_CR_THRCLR_Pos 24 /**< (TWIHS_CR) Transmit Holding Register Clear Position */
#define TWIHS_CR_THRCLR_Msk (_U_(0x1) << TWIHS_CR_THRCLR_Pos) /**< (TWIHS_CR) Transmit Holding Register Clear Mask */
#define TWIHS_CR_THRCLR TWIHS_CR_THRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_THRCLR_Msk instead */
#define TWIHS_CR_LOCKCLR_Pos 26 /**< (TWIHS_CR) Lock Clear Position */
#define TWIHS_CR_LOCKCLR_Msk (_U_(0x1) << TWIHS_CR_LOCKCLR_Pos) /**< (TWIHS_CR) Lock Clear Mask */
#define TWIHS_CR_LOCKCLR TWIHS_CR_LOCKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_LOCKCLR_Msk instead */
#define TWIHS_CR_FIFOEN_Pos 28 /**< (TWIHS_CR) FIFO Enable Position */
#define TWIHS_CR_FIFOEN_Msk (_U_(0x1) << TWIHS_CR_FIFOEN_Pos) /**< (TWIHS_CR) FIFO Enable Mask */
#define TWIHS_CR_FIFOEN TWIHS_CR_FIFOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFOEN_Msk instead */
#define TWIHS_CR_FIFODIS_Pos 29 /**< (TWIHS_CR) FIFO Disable Position */
#define TWIHS_CR_FIFODIS_Msk (_U_(0x1) << TWIHS_CR_FIFODIS_Pos) /**< (TWIHS_CR) FIFO Disable Mask */
#define TWIHS_CR_FIFODIS TWIHS_CR_FIFODIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFODIS_Msk instead */
#define TWIHS_CR_MASK _U_(0x3503FFFF) /**< \deprecated (TWIHS_CR) Register MASK (Use TWIHS_CR_Msk instead) */
#define TWIHS_CR_Msk _U_(0x3503FFFF) /**< (TWIHS_CR) Register Mask */
/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) (R/W 32) Master Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :8; /**< bit: 0..7 Reserved */
uint32_t IADRSZ:2; /**< bit: 8..9 Internal Device Address Size */
uint32_t :2; /**< bit: 10..11 Reserved */
uint32_t MREAD:1; /**< bit: 12 Master Read Direction */
uint32_t :3; /**< bit: 13..15 Reserved */
uint32_t DADR:7; /**< bit: 16..22 Device Address */
uint32_t :9; /**< bit: 23..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_MMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_MMR_OFFSET (0x04) /**< (TWIHS_MMR) Master Mode Register Offset */
#define TWIHS_MMR_IADRSZ_Pos 8 /**< (TWIHS_MMR) Internal Device Address Size Position */
#define TWIHS_MMR_IADRSZ_Msk (_U_(0x3) << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Internal Device Address Size Mask */
#define TWIHS_MMR_IADRSZ(value) (TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))
#define TWIHS_MMR_IADRSZ_NONE_Val _U_(0x0) /**< (TWIHS_MMR) No internal device address */
#define TWIHS_MMR_IADRSZ_1_BYTE_Val _U_(0x1) /**< (TWIHS_MMR) One-byte internal device address */
#define TWIHS_MMR_IADRSZ_2_BYTE_Val _U_(0x2) /**< (TWIHS_MMR) Two-byte internal device address */
#define TWIHS_MMR_IADRSZ_3_BYTE_Val _U_(0x3) /**< (TWIHS_MMR) Three-byte internal device address */
#define TWIHS_MMR_IADRSZ_NONE (TWIHS_MMR_IADRSZ_NONE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) No internal device address Position */
#define TWIHS_MMR_IADRSZ_1_BYTE (TWIHS_MMR_IADRSZ_1_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) One-byte internal device address Position */
#define TWIHS_MMR_IADRSZ_2_BYTE (TWIHS_MMR_IADRSZ_2_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Two-byte internal device address Position */
#define TWIHS_MMR_IADRSZ_3_BYTE (TWIHS_MMR_IADRSZ_3_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Three-byte internal device address Position */
#define TWIHS_MMR_MREAD_Pos 12 /**< (TWIHS_MMR) Master Read Direction Position */
#define TWIHS_MMR_MREAD_Msk (_U_(0x1) << TWIHS_MMR_MREAD_Pos) /**< (TWIHS_MMR) Master Read Direction Mask */
#define TWIHS_MMR_MREAD TWIHS_MMR_MREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_MMR_MREAD_Msk instead */
#define TWIHS_MMR_DADR_Pos 16 /**< (TWIHS_MMR) Device Address Position */
#define TWIHS_MMR_DADR_Msk (_U_(0x7F) << TWIHS_MMR_DADR_Pos) /**< (TWIHS_MMR) Device Address Mask */
#define TWIHS_MMR_DADR(value) (TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))
#define TWIHS_MMR_MASK _U_(0x7F1300) /**< \deprecated (TWIHS_MMR) Register MASK (Use TWIHS_MMR_Msk instead) */
#define TWIHS_MMR_Msk _U_(0x7F1300) /**< (TWIHS_MMR) Register Mask */
/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) (R/W 32) Slave Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NACKEN:1; /**< bit: 0 Slave Receiver Data Phase NACK enable */
uint32_t :1; /**< bit: 1 Reserved */
uint32_t SMDA:1; /**< bit: 2 SMBus Default Address */
uint32_t SMHH:1; /**< bit: 3 SMBus Host Header */
uint32_t :2; /**< bit: 4..5 Reserved */
uint32_t SCLWSDIS:1; /**< bit: 6 Clock Wait State Disable */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t MASK:7; /**< bit: 8..14 Slave Address Mask */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t SADR:7; /**< bit: 16..22 Slave Address */
uint32_t :5; /**< bit: 23..27 Reserved */
uint32_t SADR1EN:1; /**< bit: 28 Slave Address 1 Enable */
uint32_t SADR2EN:1; /**< bit: 29 Slave Address 2 Enable */
uint32_t SADR3EN:1; /**< bit: 30 Slave Address 3 Enable */
uint32_t DATAMEN:1; /**< bit: 31 Data Matching Enable */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_SMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_SMR_OFFSET (0x08) /**< (TWIHS_SMR) Slave Mode Register Offset */
#define TWIHS_SMR_NACKEN_Pos 0 /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Position */
#define TWIHS_SMR_NACKEN_Msk (_U_(0x1) << TWIHS_SMR_NACKEN_Pos) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Mask */
#define TWIHS_SMR_NACKEN TWIHS_SMR_NACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_NACKEN_Msk instead */
#define TWIHS_SMR_SMDA_Pos 2 /**< (TWIHS_SMR) SMBus Default Address Position */
#define TWIHS_SMR_SMDA_Msk (_U_(0x1) << TWIHS_SMR_SMDA_Pos) /**< (TWIHS_SMR) SMBus Default Address Mask */
#define TWIHS_SMR_SMDA TWIHS_SMR_SMDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMDA_Msk instead */
#define TWIHS_SMR_SMHH_Pos 3 /**< (TWIHS_SMR) SMBus Host Header Position */
#define TWIHS_SMR_SMHH_Msk (_U_(0x1) << TWIHS_SMR_SMHH_Pos) /**< (TWIHS_SMR) SMBus Host Header Mask */
#define TWIHS_SMR_SMHH TWIHS_SMR_SMHH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMHH_Msk instead */
#define TWIHS_SMR_SCLWSDIS_Pos 6 /**< (TWIHS_SMR) Clock Wait State Disable Position */
#define TWIHS_SMR_SCLWSDIS_Msk (_U_(0x1) << TWIHS_SMR_SCLWSDIS_Pos) /**< (TWIHS_SMR) Clock Wait State Disable Mask */
#define TWIHS_SMR_SCLWSDIS TWIHS_SMR_SCLWSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SCLWSDIS_Msk instead */
#define TWIHS_SMR_MASK_Pos 8 /**< (TWIHS_SMR) Slave Address Mask Position */
#define TWIHS_SMR_MASK_Msk (_U_(0x7F) << TWIHS_SMR_MASK_Pos) /**< (TWIHS_SMR) Slave Address Mask Mask */
#define TWIHS_SMR_MASK(value) (TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))
#define TWIHS_SMR_SADR_Pos 16 /**< (TWIHS_SMR) Slave Address Position */
#define TWIHS_SMR_SADR_Msk (_U_(0x7F) << TWIHS_SMR_SADR_Pos) /**< (TWIHS_SMR) Slave Address Mask */
#define TWIHS_SMR_SADR(value) (TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))
#define TWIHS_SMR_SADR1EN_Pos 28 /**< (TWIHS_SMR) Slave Address 1 Enable Position */
#define TWIHS_SMR_SADR1EN_Msk (_U_(0x1) << TWIHS_SMR_SADR1EN_Pos) /**< (TWIHS_SMR) Slave Address 1 Enable Mask */
#define TWIHS_SMR_SADR1EN TWIHS_SMR_SADR1EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR1EN_Msk instead */
#define TWIHS_SMR_SADR2EN_Pos 29 /**< (TWIHS_SMR) Slave Address 2 Enable Position */
#define TWIHS_SMR_SADR2EN_Msk (_U_(0x1) << TWIHS_SMR_SADR2EN_Pos) /**< (TWIHS_SMR) Slave Address 2 Enable Mask */
#define TWIHS_SMR_SADR2EN TWIHS_SMR_SADR2EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR2EN_Msk instead */
#define TWIHS_SMR_SADR3EN_Pos 30 /**< (TWIHS_SMR) Slave Address 3 Enable Position */
#define TWIHS_SMR_SADR3EN_Msk (_U_(0x1) << TWIHS_SMR_SADR3EN_Pos) /**< (TWIHS_SMR) Slave Address 3 Enable Mask */
#define TWIHS_SMR_SADR3EN TWIHS_SMR_SADR3EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR3EN_Msk instead */
#define TWIHS_SMR_DATAMEN_Pos 31 /**< (TWIHS_SMR) Data Matching Enable Position */
#define TWIHS_SMR_DATAMEN_Msk (_U_(0x1) << TWIHS_SMR_DATAMEN_Pos) /**< (TWIHS_SMR) Data Matching Enable Mask */
#define TWIHS_SMR_DATAMEN TWIHS_SMR_DATAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_DATAMEN_Msk instead */
#define TWIHS_SMR_Msk _U_(0xF07F7F4D) /**< (TWIHS_SMR) Register Mask */
/* -------- TWIHS_IADR : (TWIHS Offset: 0x0c) (R/W 32) Internal Address Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IADR:24; /**< bit: 0..23 Internal Address */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_IADR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_IADR_OFFSET (0x0C) /**< (TWIHS_IADR) Internal Address Register Offset */
#define TWIHS_IADR_IADR_Pos 0 /**< (TWIHS_IADR) Internal Address Position */
#define TWIHS_IADR_IADR_Msk (_U_(0xFFFFFF) << TWIHS_IADR_IADR_Pos) /**< (TWIHS_IADR) Internal Address Mask */
#define TWIHS_IADR_IADR(value) (TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))
#define TWIHS_IADR_MASK _U_(0xFFFFFF) /**< \deprecated (TWIHS_IADR) Register MASK (Use TWIHS_IADR_Msk instead) */
#define TWIHS_IADR_Msk _U_(0xFFFFFF) /**< (TWIHS_IADR) Register Mask */
/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) (R/W 32) Clock Waveform Generator Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CLDIV:8; /**< bit: 0..7 Clock Low Divider */
uint32_t CHDIV:8; /**< bit: 8..15 Clock High Divider */
uint32_t CKDIV:3; /**< bit: 16..18 Clock Divider */
uint32_t :5; /**< bit: 19..23 Reserved */
uint32_t HOLD:6; /**< bit: 24..29 TWD Hold Time Versus TWCK Falling */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_CWGR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_CWGR_OFFSET (0x10) /**< (TWIHS_CWGR) Clock Waveform Generator Register Offset */
#define TWIHS_CWGR_CLDIV_Pos 0 /**< (TWIHS_CWGR) Clock Low Divider Position */
#define TWIHS_CWGR_CLDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CLDIV_Pos) /**< (TWIHS_CWGR) Clock Low Divider Mask */
#define TWIHS_CWGR_CLDIV(value) (TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))
#define TWIHS_CWGR_CHDIV_Pos 8 /**< (TWIHS_CWGR) Clock High Divider Position */
#define TWIHS_CWGR_CHDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CHDIV_Pos) /**< (TWIHS_CWGR) Clock High Divider Mask */
#define TWIHS_CWGR_CHDIV(value) (TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))
#define TWIHS_CWGR_CKDIV_Pos 16 /**< (TWIHS_CWGR) Clock Divider Position */
#define TWIHS_CWGR_CKDIV_Msk (_U_(0x7) << TWIHS_CWGR_CKDIV_Pos) /**< (TWIHS_CWGR) Clock Divider Mask */
#define TWIHS_CWGR_CKDIV(value) (TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))
#define TWIHS_CWGR_HOLD_Pos 24 /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Position */
#define TWIHS_CWGR_HOLD_Msk (_U_(0x3F) << TWIHS_CWGR_HOLD_Pos) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Mask */
#define TWIHS_CWGR_HOLD(value) (TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))
#define TWIHS_CWGR_MASK _U_(0x3F07FFFF) /**< \deprecated (TWIHS_CWGR) Register MASK (Use TWIHS_CWGR_Msk instead) */
#define TWIHS_CWGR_Msk _U_(0x3F07FFFF) /**< (TWIHS_CWGR) Register Mask */
/* -------- TWIHS_SR : (TWIHS Offset: 0x20) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed (cleared by writing TWIHS_THR) */
uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready (cleared by reading TWIHS_RHR) */
uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready (cleared by writing TWIHS_THR) */
uint32_t SVREAD:1; /**< bit: 3 Slave Read */
uint32_t SVACC:1; /**< bit: 4 Slave Access */
uint32_t GACC:1; /**< bit: 5 General Call Access (cleared on read) */
uint32_t OVRE:1; /**< bit: 6 Overrun Error (cleared on read) */
uint32_t UNRE:1; /**< bit: 7 Underrun Error (cleared on read) */
uint32_t NACK:1; /**< bit: 8 Not Acknowledged (cleared on read) */
uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost (cleared on read) */
uint32_t SCLWS:1; /**< bit: 10 Clock Wait State */
uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access (cleared on read) */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge (cleared on read) */
uint32_t :1; /**< bit: 17 Reserved */
uint32_t TOUT:1; /**< bit: 18 Timeout Error (cleared on read) */
uint32_t PECERR:1; /**< bit: 19 PEC Error (cleared on read) */
uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match (cleared on read) */
uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match (cleared on read) */
uint32_t :2; /**< bit: 22..23 Reserved */
uint32_t SCL:1; /**< bit: 24 SCL Line Value */
uint32_t SDA:1; /**< bit: 25 SDA Line Value */
uint32_t :6; /**< bit: 26..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_SR_OFFSET (0x20) /**< (TWIHS_SR) Status Register Offset */
#define TWIHS_SR_TXCOMP_Pos 0 /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Position */
#define TWIHS_SR_TXCOMP_Msk (_U_(0x1) << TWIHS_SR_TXCOMP_Pos) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Mask */
#define TWIHS_SR_TXCOMP TWIHS_SR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXCOMP_Msk instead */
#define TWIHS_SR_RXRDY_Pos 1 /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Position */
#define TWIHS_SR_RXRDY_Msk (_U_(0x1) << TWIHS_SR_RXRDY_Pos) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Mask */
#define TWIHS_SR_RXRDY TWIHS_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_RXRDY_Msk instead */
#define TWIHS_SR_TXRDY_Pos 2 /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Position */
#define TWIHS_SR_TXRDY_Msk (_U_(0x1) << TWIHS_SR_TXRDY_Pos) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Mask */
#define TWIHS_SR_TXRDY TWIHS_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXRDY_Msk instead */
#define TWIHS_SR_SVREAD_Pos 3 /**< (TWIHS_SR) Slave Read Position */
#define TWIHS_SR_SVREAD_Msk (_U_(0x1) << TWIHS_SR_SVREAD_Pos) /**< (TWIHS_SR) Slave Read Mask */
#define TWIHS_SR_SVREAD TWIHS_SR_SVREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVREAD_Msk instead */
#define TWIHS_SR_SVACC_Pos 4 /**< (TWIHS_SR) Slave Access Position */
#define TWIHS_SR_SVACC_Msk (_U_(0x1) << TWIHS_SR_SVACC_Pos) /**< (TWIHS_SR) Slave Access Mask */
#define TWIHS_SR_SVACC TWIHS_SR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVACC_Msk instead */
#define TWIHS_SR_GACC_Pos 5 /**< (TWIHS_SR) General Call Access (cleared on read) Position */
#define TWIHS_SR_GACC_Msk (_U_(0x1) << TWIHS_SR_GACC_Pos) /**< (TWIHS_SR) General Call Access (cleared on read) Mask */
#define TWIHS_SR_GACC TWIHS_SR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_GACC_Msk instead */
#define TWIHS_SR_OVRE_Pos 6 /**< (TWIHS_SR) Overrun Error (cleared on read) Position */
#define TWIHS_SR_OVRE_Msk (_U_(0x1) << TWIHS_SR_OVRE_Pos) /**< (TWIHS_SR) Overrun Error (cleared on read) Mask */
#define TWIHS_SR_OVRE TWIHS_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_OVRE_Msk instead */
#define TWIHS_SR_UNRE_Pos 7 /**< (TWIHS_SR) Underrun Error (cleared on read) Position */
#define TWIHS_SR_UNRE_Msk (_U_(0x1) << TWIHS_SR_UNRE_Pos) /**< (TWIHS_SR) Underrun Error (cleared on read) Mask */
#define TWIHS_SR_UNRE TWIHS_SR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_UNRE_Msk instead */
#define TWIHS_SR_NACK_Pos 8 /**< (TWIHS_SR) Not Acknowledged (cleared on read) Position */
#define TWIHS_SR_NACK_Msk (_U_(0x1) << TWIHS_SR_NACK_Pos) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Mask */
#define TWIHS_SR_NACK TWIHS_SR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_NACK_Msk instead */
#define TWIHS_SR_ARBLST_Pos 9 /**< (TWIHS_SR) Arbitration Lost (cleared on read) Position */
#define TWIHS_SR_ARBLST_Msk (_U_(0x1) << TWIHS_SR_ARBLST_Pos) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Mask */
#define TWIHS_SR_ARBLST TWIHS_SR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_ARBLST_Msk instead */
#define TWIHS_SR_SCLWS_Pos 10 /**< (TWIHS_SR) Clock Wait State Position */
#define TWIHS_SR_SCLWS_Msk (_U_(0x1) << TWIHS_SR_SCLWS_Pos) /**< (TWIHS_SR) Clock Wait State Mask */
#define TWIHS_SR_SCLWS TWIHS_SR_SCLWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCLWS_Msk instead */
#define TWIHS_SR_EOSACC_Pos 11 /**< (TWIHS_SR) End Of Slave Access (cleared on read) Position */
#define TWIHS_SR_EOSACC_Msk (_U_(0x1) << TWIHS_SR_EOSACC_Pos) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Mask */
#define TWIHS_SR_EOSACC TWIHS_SR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_EOSACC_Msk instead */
#define TWIHS_SR_MCACK_Pos 16 /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Position */
#define TWIHS_SR_MCACK_Msk (_U_(0x1) << TWIHS_SR_MCACK_Pos) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Mask */
#define TWIHS_SR_MCACK TWIHS_SR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_MCACK_Msk instead */
#define TWIHS_SR_TOUT_Pos 18 /**< (TWIHS_SR) Timeout Error (cleared on read) Position */
#define TWIHS_SR_TOUT_Msk (_U_(0x1) << TWIHS_SR_TOUT_Pos) /**< (TWIHS_SR) Timeout Error (cleared on read) Mask */
#define TWIHS_SR_TOUT TWIHS_SR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TOUT_Msk instead */
#define TWIHS_SR_PECERR_Pos 19 /**< (TWIHS_SR) PEC Error (cleared on read) Position */
#define TWIHS_SR_PECERR_Msk (_U_(0x1) << TWIHS_SR_PECERR_Pos) /**< (TWIHS_SR) PEC Error (cleared on read) Mask */
#define TWIHS_SR_PECERR TWIHS_SR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_PECERR_Msk instead */
#define TWIHS_SR_SMBDAM_Pos 20 /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Position */
#define TWIHS_SR_SMBDAM_Msk (_U_(0x1) << TWIHS_SR_SMBDAM_Pos) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Mask */
#define TWIHS_SR_SMBDAM TWIHS_SR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBDAM_Msk instead */
#define TWIHS_SR_SMBHHM_Pos 21 /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Position */
#define TWIHS_SR_SMBHHM_Msk (_U_(0x1) << TWIHS_SR_SMBHHM_Pos) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Mask */
#define TWIHS_SR_SMBHHM TWIHS_SR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBHHM_Msk instead */
#define TWIHS_SR_SCL_Pos 24 /**< (TWIHS_SR) SCL Line Value Position */
#define TWIHS_SR_SCL_Msk (_U_(0x1) << TWIHS_SR_SCL_Pos) /**< (TWIHS_SR) SCL Line Value Mask */
#define TWIHS_SR_SCL TWIHS_SR_SCL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCL_Msk instead */
#define TWIHS_SR_SDA_Pos 25 /**< (TWIHS_SR) SDA Line Value Position */
#define TWIHS_SR_SDA_Msk (_U_(0x1) << TWIHS_SR_SDA_Pos) /**< (TWIHS_SR) SDA Line Value Mask */
#define TWIHS_SR_SDA TWIHS_SR_SDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SDA_Msk instead */
#define TWIHS_SR_MASK _U_(0x33D0FFF) /**< \deprecated (TWIHS_SR) Register MASK (Use TWIHS_SR_Msk instead) */
#define TWIHS_SR_Msk _U_(0x33D0FFF) /**< (TWIHS_SR) Register Mask */
/* -------- TWIHS_IER : (TWIHS Offset: 0x24) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Enable */
uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Enable */
uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Enable */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Enable */
uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Enable */
uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Enable */
uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Enable */
uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Enable */
uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Enable */
uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Enable */
uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Enable */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Enable */
uint32_t :1; /**< bit: 17 Reserved */
uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Enable */
uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Enable */
uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Enable */
uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Enable */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_IER_OFFSET (0x24) /**< (TWIHS_IER) Interrupt Enable Register Offset */
#define TWIHS_IER_TXCOMP_Pos 0 /**< (TWIHS_IER) Transmission Completed Interrupt Enable Position */
#define TWIHS_IER_TXCOMP_Msk (_U_(0x1) << TWIHS_IER_TXCOMP_Pos) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Mask */
#define TWIHS_IER_TXCOMP TWIHS_IER_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXCOMP_Msk instead */
#define TWIHS_IER_RXRDY_Pos 1 /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Position */
#define TWIHS_IER_RXRDY_Msk (_U_(0x1) << TWIHS_IER_RXRDY_Pos) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Mask */
#define TWIHS_IER_RXRDY TWIHS_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_RXRDY_Msk instead */
#define TWIHS_IER_TXRDY_Pos 2 /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Position */
#define TWIHS_IER_TXRDY_Msk (_U_(0x1) << TWIHS_IER_TXRDY_Pos) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Mask */
#define TWIHS_IER_TXRDY TWIHS_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXRDY_Msk instead */
#define TWIHS_IER_SVACC_Pos 4 /**< (TWIHS_IER) Slave Access Interrupt Enable Position */
#define TWIHS_IER_SVACC_Msk (_U_(0x1) << TWIHS_IER_SVACC_Pos) /**< (TWIHS_IER) Slave Access Interrupt Enable Mask */
#define TWIHS_IER_SVACC TWIHS_IER_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SVACC_Msk instead */
#define TWIHS_IER_GACC_Pos 5 /**< (TWIHS_IER) General Call Access Interrupt Enable Position */
#define TWIHS_IER_GACC_Msk (_U_(0x1) << TWIHS_IER_GACC_Pos) /**< (TWIHS_IER) General Call Access Interrupt Enable Mask */
#define TWIHS_IER_GACC TWIHS_IER_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_GACC_Msk instead */
#define TWIHS_IER_OVRE_Pos 6 /**< (TWIHS_IER) Overrun Error Interrupt Enable Position */
#define TWIHS_IER_OVRE_Msk (_U_(0x1) << TWIHS_IER_OVRE_Pos) /**< (TWIHS_IER) Overrun Error Interrupt Enable Mask */
#define TWIHS_IER_OVRE TWIHS_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_OVRE_Msk instead */
#define TWIHS_IER_UNRE_Pos 7 /**< (TWIHS_IER) Underrun Error Interrupt Enable Position */
#define TWIHS_IER_UNRE_Msk (_U_(0x1) << TWIHS_IER_UNRE_Pos) /**< (TWIHS_IER) Underrun Error Interrupt Enable Mask */
#define TWIHS_IER_UNRE TWIHS_IER_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_UNRE_Msk instead */
#define TWIHS_IER_NACK_Pos 8 /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Position */
#define TWIHS_IER_NACK_Msk (_U_(0x1) << TWIHS_IER_NACK_Pos) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Mask */
#define TWIHS_IER_NACK TWIHS_IER_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_NACK_Msk instead */
#define TWIHS_IER_ARBLST_Pos 9 /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Position */
#define TWIHS_IER_ARBLST_Msk (_U_(0x1) << TWIHS_IER_ARBLST_Pos) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Mask */
#define TWIHS_IER_ARBLST TWIHS_IER_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_ARBLST_Msk instead */
#define TWIHS_IER_SCL_WS_Pos 10 /**< (TWIHS_IER) Clock Wait State Interrupt Enable Position */
#define TWIHS_IER_SCL_WS_Msk (_U_(0x1) << TWIHS_IER_SCL_WS_Pos) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Mask */
#define TWIHS_IER_SCL_WS TWIHS_IER_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SCL_WS_Msk instead */
#define TWIHS_IER_EOSACC_Pos 11 /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Position */
#define TWIHS_IER_EOSACC_Msk (_U_(0x1) << TWIHS_IER_EOSACC_Pos) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Mask */
#define TWIHS_IER_EOSACC TWIHS_IER_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_EOSACC_Msk instead */
#define TWIHS_IER_MCACK_Pos 16 /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Position */
#define TWIHS_IER_MCACK_Msk (_U_(0x1) << TWIHS_IER_MCACK_Pos) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Mask */
#define TWIHS_IER_MCACK TWIHS_IER_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_MCACK_Msk instead */
#define TWIHS_IER_TOUT_Pos 18 /**< (TWIHS_IER) Timeout Error Interrupt Enable Position */
#define TWIHS_IER_TOUT_Msk (_U_(0x1) << TWIHS_IER_TOUT_Pos) /**< (TWIHS_IER) Timeout Error Interrupt Enable Mask */
#define TWIHS_IER_TOUT TWIHS_IER_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TOUT_Msk instead */
#define TWIHS_IER_PECERR_Pos 19 /**< (TWIHS_IER) PEC Error Interrupt Enable Position */
#define TWIHS_IER_PECERR_Msk (_U_(0x1) << TWIHS_IER_PECERR_Pos) /**< (TWIHS_IER) PEC Error Interrupt Enable Mask */
#define TWIHS_IER_PECERR TWIHS_IER_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_PECERR_Msk instead */
#define TWIHS_IER_SMBDAM_Pos 20 /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Position */
#define TWIHS_IER_SMBDAM_Msk (_U_(0x1) << TWIHS_IER_SMBDAM_Pos) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Mask */
#define TWIHS_IER_SMBDAM TWIHS_IER_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBDAM_Msk instead */
#define TWIHS_IER_SMBHHM_Pos 21 /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Position */
#define TWIHS_IER_SMBHHM_Msk (_U_(0x1) << TWIHS_IER_SMBHHM_Pos) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Mask */
#define TWIHS_IER_SMBHHM TWIHS_IER_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBHHM_Msk instead */
#define TWIHS_IER_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IER) Register MASK (Use TWIHS_IER_Msk instead) */
#define TWIHS_IER_Msk _U_(0x3D0FF7) /**< (TWIHS_IER) Register Mask */
/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Disable */
uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Disable */
uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Disable */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Disable */
uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Disable */
uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Disable */
uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Disable */
uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Disable */
uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Disable */
uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Disable */
uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Disable */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Disable */
uint32_t :1; /**< bit: 17 Reserved */
uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Disable */
uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Disable */
uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Disable */
uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Disable */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_IDR_OFFSET (0x28) /**< (TWIHS_IDR) Interrupt Disable Register Offset */
#define TWIHS_IDR_TXCOMP_Pos 0 /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Position */
#define TWIHS_IDR_TXCOMP_Msk (_U_(0x1) << TWIHS_IDR_TXCOMP_Pos) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Mask */
#define TWIHS_IDR_TXCOMP TWIHS_IDR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXCOMP_Msk instead */
#define TWIHS_IDR_RXRDY_Pos 1 /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Position */
#define TWIHS_IDR_RXRDY_Msk (_U_(0x1) << TWIHS_IDR_RXRDY_Pos) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Mask */
#define TWIHS_IDR_RXRDY TWIHS_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_RXRDY_Msk instead */
#define TWIHS_IDR_TXRDY_Pos 2 /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Position */
#define TWIHS_IDR_TXRDY_Msk (_U_(0x1) << TWIHS_IDR_TXRDY_Pos) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Mask */
#define TWIHS_IDR_TXRDY TWIHS_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXRDY_Msk instead */
#define TWIHS_IDR_SVACC_Pos 4 /**< (TWIHS_IDR) Slave Access Interrupt Disable Position */
#define TWIHS_IDR_SVACC_Msk (_U_(0x1) << TWIHS_IDR_SVACC_Pos) /**< (TWIHS_IDR) Slave Access Interrupt Disable Mask */
#define TWIHS_IDR_SVACC TWIHS_IDR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SVACC_Msk instead */
#define TWIHS_IDR_GACC_Pos 5 /**< (TWIHS_IDR) General Call Access Interrupt Disable Position */
#define TWIHS_IDR_GACC_Msk (_U_(0x1) << TWIHS_IDR_GACC_Pos) /**< (TWIHS_IDR) General Call Access Interrupt Disable Mask */
#define TWIHS_IDR_GACC TWIHS_IDR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_GACC_Msk instead */
#define TWIHS_IDR_OVRE_Pos 6 /**< (TWIHS_IDR) Overrun Error Interrupt Disable Position */
#define TWIHS_IDR_OVRE_Msk (_U_(0x1) << TWIHS_IDR_OVRE_Pos) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Mask */
#define TWIHS_IDR_OVRE TWIHS_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_OVRE_Msk instead */
#define TWIHS_IDR_UNRE_Pos 7 /**< (TWIHS_IDR) Underrun Error Interrupt Disable Position */
#define TWIHS_IDR_UNRE_Msk (_U_(0x1) << TWIHS_IDR_UNRE_Pos) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Mask */
#define TWIHS_IDR_UNRE TWIHS_IDR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_UNRE_Msk instead */
#define TWIHS_IDR_NACK_Pos 8 /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Position */
#define TWIHS_IDR_NACK_Msk (_U_(0x1) << TWIHS_IDR_NACK_Pos) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Mask */
#define TWIHS_IDR_NACK TWIHS_IDR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_NACK_Msk instead */
#define TWIHS_IDR_ARBLST_Pos 9 /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Position */
#define TWIHS_IDR_ARBLST_Msk (_U_(0x1) << TWIHS_IDR_ARBLST_Pos) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Mask */
#define TWIHS_IDR_ARBLST TWIHS_IDR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_ARBLST_Msk instead */
#define TWIHS_IDR_SCL_WS_Pos 10 /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Position */
#define TWIHS_IDR_SCL_WS_Msk (_U_(0x1) << TWIHS_IDR_SCL_WS_Pos) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Mask */
#define TWIHS_IDR_SCL_WS TWIHS_IDR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SCL_WS_Msk instead */
#define TWIHS_IDR_EOSACC_Pos 11 /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Position */
#define TWIHS_IDR_EOSACC_Msk (_U_(0x1) << TWIHS_IDR_EOSACC_Pos) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Mask */
#define TWIHS_IDR_EOSACC TWIHS_IDR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_EOSACC_Msk instead */
#define TWIHS_IDR_MCACK_Pos 16 /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Position */
#define TWIHS_IDR_MCACK_Msk (_U_(0x1) << TWIHS_IDR_MCACK_Pos) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Mask */
#define TWIHS_IDR_MCACK TWIHS_IDR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_MCACK_Msk instead */
#define TWIHS_IDR_TOUT_Pos 18 /**< (TWIHS_IDR) Timeout Error Interrupt Disable Position */
#define TWIHS_IDR_TOUT_Msk (_U_(0x1) << TWIHS_IDR_TOUT_Pos) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Mask */
#define TWIHS_IDR_TOUT TWIHS_IDR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TOUT_Msk instead */
#define TWIHS_IDR_PECERR_Pos 19 /**< (TWIHS_IDR) PEC Error Interrupt Disable Position */
#define TWIHS_IDR_PECERR_Msk (_U_(0x1) << TWIHS_IDR_PECERR_Pos) /**< (TWIHS_IDR) PEC Error Interrupt Disable Mask */
#define TWIHS_IDR_PECERR TWIHS_IDR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_PECERR_Msk instead */
#define TWIHS_IDR_SMBDAM_Pos 20 /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Position */
#define TWIHS_IDR_SMBDAM_Msk (_U_(0x1) << TWIHS_IDR_SMBDAM_Pos) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Mask */
#define TWIHS_IDR_SMBDAM TWIHS_IDR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBDAM_Msk instead */
#define TWIHS_IDR_SMBHHM_Pos 21 /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Position */
#define TWIHS_IDR_SMBHHM_Msk (_U_(0x1) << TWIHS_IDR_SMBHHM_Pos) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Mask */
#define TWIHS_IDR_SMBHHM TWIHS_IDR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBHHM_Msk instead */
#define TWIHS_IDR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IDR) Register MASK (Use TWIHS_IDR_Msk instead) */
#define TWIHS_IDR_Msk _U_(0x3D0FF7) /**< (TWIHS_IDR) Register Mask */
/* -------- TWIHS_IMR : (TWIHS Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Mask */
uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Mask */
uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Mask */
uint32_t :1; /**< bit: 3 Reserved */
uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Mask */
uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Mask */
uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Mask */
uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Mask */
uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Mask */
uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Mask */
uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Mask */
uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Mask */
uint32_t :4; /**< bit: 12..15 Reserved */
uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Mask */
uint32_t :1; /**< bit: 17 Reserved */
uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Mask */
uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Mask */
uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Mask */
uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Mask */
uint32_t :10; /**< bit: 22..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_IMR_OFFSET (0x2C) /**< (TWIHS_IMR) Interrupt Mask Register Offset */
#define TWIHS_IMR_TXCOMP_Pos 0 /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Position */
#define TWIHS_IMR_TXCOMP_Msk (_U_(0x1) << TWIHS_IMR_TXCOMP_Pos) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Mask */
#define TWIHS_IMR_TXCOMP TWIHS_IMR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXCOMP_Msk instead */
#define TWIHS_IMR_RXRDY_Pos 1 /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Position */
#define TWIHS_IMR_RXRDY_Msk (_U_(0x1) << TWIHS_IMR_RXRDY_Pos) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Mask */
#define TWIHS_IMR_RXRDY TWIHS_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_RXRDY_Msk instead */
#define TWIHS_IMR_TXRDY_Pos 2 /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Position */
#define TWIHS_IMR_TXRDY_Msk (_U_(0x1) << TWIHS_IMR_TXRDY_Pos) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Mask */
#define TWIHS_IMR_TXRDY TWIHS_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXRDY_Msk instead */
#define TWIHS_IMR_SVACC_Pos 4 /**< (TWIHS_IMR) Slave Access Interrupt Mask Position */
#define TWIHS_IMR_SVACC_Msk (_U_(0x1) << TWIHS_IMR_SVACC_Pos) /**< (TWIHS_IMR) Slave Access Interrupt Mask Mask */
#define TWIHS_IMR_SVACC TWIHS_IMR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SVACC_Msk instead */
#define TWIHS_IMR_GACC_Pos 5 /**< (TWIHS_IMR) General Call Access Interrupt Mask Position */
#define TWIHS_IMR_GACC_Msk (_U_(0x1) << TWIHS_IMR_GACC_Pos) /**< (TWIHS_IMR) General Call Access Interrupt Mask Mask */
#define TWIHS_IMR_GACC TWIHS_IMR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_GACC_Msk instead */
#define TWIHS_IMR_OVRE_Pos 6 /**< (TWIHS_IMR) Overrun Error Interrupt Mask Position */
#define TWIHS_IMR_OVRE_Msk (_U_(0x1) << TWIHS_IMR_OVRE_Pos) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Mask */
#define TWIHS_IMR_OVRE TWIHS_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_OVRE_Msk instead */
#define TWIHS_IMR_UNRE_Pos 7 /**< (TWIHS_IMR) Underrun Error Interrupt Mask Position */
#define TWIHS_IMR_UNRE_Msk (_U_(0x1) << TWIHS_IMR_UNRE_Pos) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Mask */
#define TWIHS_IMR_UNRE TWIHS_IMR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_UNRE_Msk instead */
#define TWIHS_IMR_NACK_Pos 8 /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Position */
#define TWIHS_IMR_NACK_Msk (_U_(0x1) << TWIHS_IMR_NACK_Pos) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Mask */
#define TWIHS_IMR_NACK TWIHS_IMR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_NACK_Msk instead */
#define TWIHS_IMR_ARBLST_Pos 9 /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Position */
#define TWIHS_IMR_ARBLST_Msk (_U_(0x1) << TWIHS_IMR_ARBLST_Pos) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Mask */
#define TWIHS_IMR_ARBLST TWIHS_IMR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_ARBLST_Msk instead */
#define TWIHS_IMR_SCL_WS_Pos 10 /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Position */
#define TWIHS_IMR_SCL_WS_Msk (_U_(0x1) << TWIHS_IMR_SCL_WS_Pos) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Mask */
#define TWIHS_IMR_SCL_WS TWIHS_IMR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SCL_WS_Msk instead */
#define TWIHS_IMR_EOSACC_Pos 11 /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Position */
#define TWIHS_IMR_EOSACC_Msk (_U_(0x1) << TWIHS_IMR_EOSACC_Pos) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Mask */
#define TWIHS_IMR_EOSACC TWIHS_IMR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_EOSACC_Msk instead */
#define TWIHS_IMR_MCACK_Pos 16 /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Position */
#define TWIHS_IMR_MCACK_Msk (_U_(0x1) << TWIHS_IMR_MCACK_Pos) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Mask */
#define TWIHS_IMR_MCACK TWIHS_IMR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_MCACK_Msk instead */
#define TWIHS_IMR_TOUT_Pos 18 /**< (TWIHS_IMR) Timeout Error Interrupt Mask Position */
#define TWIHS_IMR_TOUT_Msk (_U_(0x1) << TWIHS_IMR_TOUT_Pos) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Mask */
#define TWIHS_IMR_TOUT TWIHS_IMR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TOUT_Msk instead */
#define TWIHS_IMR_PECERR_Pos 19 /**< (TWIHS_IMR) PEC Error Interrupt Mask Position */
#define TWIHS_IMR_PECERR_Msk (_U_(0x1) << TWIHS_IMR_PECERR_Pos) /**< (TWIHS_IMR) PEC Error Interrupt Mask Mask */
#define TWIHS_IMR_PECERR TWIHS_IMR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_PECERR_Msk instead */
#define TWIHS_IMR_SMBDAM_Pos 20 /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Position */
#define TWIHS_IMR_SMBDAM_Msk (_U_(0x1) << TWIHS_IMR_SMBDAM_Pos) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Mask */
#define TWIHS_IMR_SMBDAM TWIHS_IMR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBDAM_Msk instead */
#define TWIHS_IMR_SMBHHM_Pos 21 /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Position */
#define TWIHS_IMR_SMBHHM_Msk (_U_(0x1) << TWIHS_IMR_SMBHHM_Pos) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Mask */
#define TWIHS_IMR_SMBHHM TWIHS_IMR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBHHM_Msk instead */
#define TWIHS_IMR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IMR) Register MASK (Use TWIHS_IMR_Msk instead) */
#define TWIHS_IMR_Msk _U_(0x3D0FF7) /**< (TWIHS_IMR) Register Mask */
/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) (R/ 32) Receive Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXDATA:8; /**< bit: 0..7 Master or Slave Receive Holding Data */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_RHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_RHR_OFFSET (0x30) /**< (TWIHS_RHR) Receive Holding Register Offset */
#define TWIHS_RHR_RXDATA_Pos 0 /**< (TWIHS_RHR) Master or Slave Receive Holding Data Position */
#define TWIHS_RHR_RXDATA_Msk (_U_(0xFF) << TWIHS_RHR_RXDATA_Pos) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Mask */
#define TWIHS_RHR_RXDATA(value) (TWIHS_RHR_RXDATA_Msk & ((value) << TWIHS_RHR_RXDATA_Pos))
#define TWIHS_RHR_MASK _U_(0xFF) /**< \deprecated (TWIHS_RHR) Register MASK (Use TWIHS_RHR_Msk instead) */
#define TWIHS_RHR_Msk _U_(0xFF) /**< (TWIHS_RHR) Register Mask */
/* -------- TWIHS_THR : (TWIHS Offset: 0x34) (/W 32) Transmit Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXDATA:8; /**< bit: 0..7 Master or Slave Transmit Holding Data */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_THR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_THR_OFFSET (0x34) /**< (TWIHS_THR) Transmit Holding Register Offset */
#define TWIHS_THR_TXDATA_Pos 0 /**< (TWIHS_THR) Master or Slave Transmit Holding Data Position */
#define TWIHS_THR_TXDATA_Msk (_U_(0xFF) << TWIHS_THR_TXDATA_Pos) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Mask */
#define TWIHS_THR_TXDATA(value) (TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))
#define TWIHS_THR_MASK _U_(0xFF) /**< \deprecated (TWIHS_THR) Register MASK (Use TWIHS_THR_Msk instead) */
#define TWIHS_THR_Msk _U_(0xFF) /**< (TWIHS_THR) Register Mask */
/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) (R/W 32) SMBus Timing Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PRESC:4; /**< bit: 0..3 SMBus Clock Prescaler */
uint32_t :4; /**< bit: 4..7 Reserved */
uint32_t TLOWS:8; /**< bit: 8..15 Slave Clock Stretch Maximum Cycles */
uint32_t TLOWM:8; /**< bit: 16..23 Master Clock Stretch Maximum Cycles */
uint32_t THMAX:8; /**< bit: 24..31 Clock High Maximum Cycles */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_SMBTR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_SMBTR_OFFSET (0x38) /**< (TWIHS_SMBTR) SMBus Timing Register Offset */
#define TWIHS_SMBTR_PRESC_Pos 0 /**< (TWIHS_SMBTR) SMBus Clock Prescaler Position */
#define TWIHS_SMBTR_PRESC_Msk (_U_(0xF) << TWIHS_SMBTR_PRESC_Pos) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Mask */
#define TWIHS_SMBTR_PRESC(value) (TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))
#define TWIHS_SMBTR_TLOWS_Pos 8 /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Position */
#define TWIHS_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWS_Pos) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Mask */
#define TWIHS_SMBTR_TLOWS(value) (TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))
#define TWIHS_SMBTR_TLOWM_Pos 16 /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Position */
#define TWIHS_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWM_Pos) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Mask */
#define TWIHS_SMBTR_TLOWM(value) (TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))
#define TWIHS_SMBTR_THMAX_Pos 24 /**< (TWIHS_SMBTR) Clock High Maximum Cycles Position */
#define TWIHS_SMBTR_THMAX_Msk (_U_(0xFF) << TWIHS_SMBTR_THMAX_Pos) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Mask */
#define TWIHS_SMBTR_THMAX(value) (TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))
#define TWIHS_SMBTR_MASK _U_(0xFFFFFF0F) /**< \deprecated (TWIHS_SMBTR) Register MASK (Use TWIHS_SMBTR_Msk instead) */
#define TWIHS_SMBTR_Msk _U_(0xFFFFFF0F) /**< (TWIHS_SMBTR) Register Mask */
/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) (R/W 32) Filter Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILT:1; /**< bit: 0 RX Digital Filter */
uint32_t PADFEN:1; /**< bit: 1 PAD Filter Enable */
uint32_t PADFCFG:1; /**< bit: 2 PAD Filter Config */
uint32_t :5; /**< bit: 3..7 Reserved */
uint32_t THRES:3; /**< bit: 8..10 Digital Filter Threshold */
uint32_t :21; /**< bit: 11..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_FILTR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_FILTR_OFFSET (0x44) /**< (TWIHS_FILTR) Filter Register Offset */
#define TWIHS_FILTR_FILT_Pos 0 /**< (TWIHS_FILTR) RX Digital Filter Position */
#define TWIHS_FILTR_FILT_Msk (_U_(0x1) << TWIHS_FILTR_FILT_Pos) /**< (TWIHS_FILTR) RX Digital Filter Mask */
#define TWIHS_FILTR_FILT TWIHS_FILTR_FILT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_FILT_Msk instead */
#define TWIHS_FILTR_PADFEN_Pos 1 /**< (TWIHS_FILTR) PAD Filter Enable Position */
#define TWIHS_FILTR_PADFEN_Msk (_U_(0x1) << TWIHS_FILTR_PADFEN_Pos) /**< (TWIHS_FILTR) PAD Filter Enable Mask */
#define TWIHS_FILTR_PADFEN TWIHS_FILTR_PADFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFEN_Msk instead */
#define TWIHS_FILTR_PADFCFG_Pos 2 /**< (TWIHS_FILTR) PAD Filter Config Position */
#define TWIHS_FILTR_PADFCFG_Msk (_U_(0x1) << TWIHS_FILTR_PADFCFG_Pos) /**< (TWIHS_FILTR) PAD Filter Config Mask */
#define TWIHS_FILTR_PADFCFG TWIHS_FILTR_PADFCFG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFCFG_Msk instead */
#define TWIHS_FILTR_THRES_Pos 8 /**< (TWIHS_FILTR) Digital Filter Threshold Position */
#define TWIHS_FILTR_THRES_Msk (_U_(0x7) << TWIHS_FILTR_THRES_Pos) /**< (TWIHS_FILTR) Digital Filter Threshold Mask */
#define TWIHS_FILTR_THRES(value) (TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))
#define TWIHS_FILTR_MASK _U_(0x707) /**< \deprecated (TWIHS_FILTR) Register MASK (Use TWIHS_FILTR_Msk instead) */
#define TWIHS_FILTR_Msk _U_(0x707) /**< (TWIHS_FILTR) Register Mask */
/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4c) (R/W 32) SleepWalking Matching Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SADR1:7; /**< bit: 0..6 Slave Address 1 */
uint32_t :1; /**< bit: 7 Reserved */
uint32_t SADR2:7; /**< bit: 8..14 Slave Address 2 */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t SADR3:7; /**< bit: 16..22 Slave Address 3 */
uint32_t :1; /**< bit: 23 Reserved */
uint32_t DATAM:8; /**< bit: 24..31 Data Match */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_SWMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_SWMR_OFFSET (0x4C) /**< (TWIHS_SWMR) SleepWalking Matching Register Offset */
#define TWIHS_SWMR_SADR1_Pos 0 /**< (TWIHS_SWMR) Slave Address 1 Position */
#define TWIHS_SWMR_SADR1_Msk (_U_(0x7F) << TWIHS_SWMR_SADR1_Pos) /**< (TWIHS_SWMR) Slave Address 1 Mask */
#define TWIHS_SWMR_SADR1(value) (TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))
#define TWIHS_SWMR_SADR2_Pos 8 /**< (TWIHS_SWMR) Slave Address 2 Position */
#define TWIHS_SWMR_SADR2_Msk (_U_(0x7F) << TWIHS_SWMR_SADR2_Pos) /**< (TWIHS_SWMR) Slave Address 2 Mask */
#define TWIHS_SWMR_SADR2(value) (TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))
#define TWIHS_SWMR_SADR3_Pos 16 /**< (TWIHS_SWMR) Slave Address 3 Position */
#define TWIHS_SWMR_SADR3_Msk (_U_(0x7F) << TWIHS_SWMR_SADR3_Pos) /**< (TWIHS_SWMR) Slave Address 3 Mask */
#define TWIHS_SWMR_SADR3(value) (TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))
#define TWIHS_SWMR_DATAM_Pos 24 /**< (TWIHS_SWMR) Data Match Position */
#define TWIHS_SWMR_DATAM_Msk (_U_(0xFF) << TWIHS_SWMR_DATAM_Pos) /**< (TWIHS_SWMR) Data Match Mask */
#define TWIHS_SWMR_DATAM(value) (TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))
#define TWIHS_SWMR_MASK _U_(0xFF7F7F7F) /**< \deprecated (TWIHS_SWMR) Register MASK (Use TWIHS_SWMR_Msk instead) */
#define TWIHS_SWMR_Msk _U_(0xFF7F7F7F) /**< (TWIHS_SWMR) Register Mask */
/* -------- TWIHS_WPMR : (TWIHS Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_WPMR_OFFSET (0xE4) /**< (TWIHS_WPMR) Write Protection Mode Register Offset */
#define TWIHS_WPMR_WPEN_Pos 0 /**< (TWIHS_WPMR) Write Protection Enable Position */
#define TWIHS_WPMR_WPEN_Msk (_U_(0x1) << TWIHS_WPMR_WPEN_Pos) /**< (TWIHS_WPMR) Write Protection Enable Mask */
#define TWIHS_WPMR_WPEN TWIHS_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPMR_WPEN_Msk instead */
#define TWIHS_WPMR_WPKEY_Pos 8 /**< (TWIHS_WPMR) Write Protection Key Position */
#define TWIHS_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Write Protection Key Mask */
#define TWIHS_WPMR_WPKEY(value) (TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))
#define TWIHS_WPMR_WPKEY_PASSWD_Val _U_(0x545749) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
#define TWIHS_WPMR_WPKEY_PASSWD (TWIHS_WPMR_WPKEY_PASSWD_Val << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 Position */
#define TWIHS_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPMR) Register MASK (Use TWIHS_WPMR_Msk instead) */
#define TWIHS_WPMR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPMR) Register Mask */
/* -------- TWIHS_WPSR : (TWIHS Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPVSRC:24; /**< bit: 8..31 Write Protection Violation Source */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} TWIHS_WPSR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TWIHS_WPSR_OFFSET (0xE8) /**< (TWIHS_WPSR) Write Protection Status Register Offset */
#define TWIHS_WPSR_WPVS_Pos 0 /**< (TWIHS_WPSR) Write Protection Violation Status Position */
#define TWIHS_WPSR_WPVS_Msk (_U_(0x1) << TWIHS_WPSR_WPVS_Pos) /**< (TWIHS_WPSR) Write Protection Violation Status Mask */
#define TWIHS_WPSR_WPVS TWIHS_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPSR_WPVS_Msk instead */
#define TWIHS_WPSR_WPVSRC_Pos 8 /**< (TWIHS_WPSR) Write Protection Violation Source Position */
#define TWIHS_WPSR_WPVSRC_Msk (_U_(0xFFFFFF) << TWIHS_WPSR_WPVSRC_Pos) /**< (TWIHS_WPSR) Write Protection Violation Source Mask */
#define TWIHS_WPSR_WPVSRC(value) (TWIHS_WPSR_WPVSRC_Msk & ((value) << TWIHS_WPSR_WPVSRC_Pos))
#define TWIHS_WPSR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPSR) Register MASK (Use TWIHS_WPSR_Msk instead) */
#define TWIHS_WPSR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPSR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief TWIHS hardware registers */
typedef struct {
__O uint32_t TWIHS_CR; /**< (TWIHS Offset: 0x00) Control Register */
__IO uint32_t TWIHS_MMR; /**< (TWIHS Offset: 0x04) Master Mode Register */
__IO uint32_t TWIHS_SMR; /**< (TWIHS Offset: 0x08) Slave Mode Register */
__IO uint32_t TWIHS_IADR; /**< (TWIHS Offset: 0x0C) Internal Address Register */
__IO uint32_t TWIHS_CWGR; /**< (TWIHS Offset: 0x10) Clock Waveform Generator Register */
RoReg8 Reserved1[0xC];
__I uint32_t TWIHS_SR; /**< (TWIHS Offset: 0x20) Status Register */
__O uint32_t TWIHS_IER; /**< (TWIHS Offset: 0x24) Interrupt Enable Register */
__O uint32_t TWIHS_IDR; /**< (TWIHS Offset: 0x28) Interrupt Disable Register */
__I uint32_t TWIHS_IMR; /**< (TWIHS Offset: 0x2C) Interrupt Mask Register */
__I uint32_t TWIHS_RHR; /**< (TWIHS Offset: 0x30) Receive Holding Register */
__O uint32_t TWIHS_THR; /**< (TWIHS Offset: 0x34) Transmit Holding Register */
__IO uint32_t TWIHS_SMBTR; /**< (TWIHS Offset: 0x38) SMBus Timing Register */
RoReg8 Reserved2[0x8];
__IO uint32_t TWIHS_FILTR; /**< (TWIHS Offset: 0x44) Filter Register */
RoReg8 Reserved3[0x4];
__IO uint32_t TWIHS_SWMR; /**< (TWIHS Offset: 0x4C) SleepWalking Matching Register */
RoReg8 Reserved4[0x94];
__IO uint32_t TWIHS_WPMR; /**< (TWIHS Offset: 0xE4) Write Protection Mode Register */
__I uint32_t TWIHS_WPSR; /**< (TWIHS Offset: 0xE8) Write Protection Status Register */
} Twihs;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief TWIHS hardware registers */
typedef struct {
__O TWIHS_CR_Type TWIHS_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO TWIHS_MMR_Type TWIHS_MMR; /**< Offset: 0x04 (R/W 32) Master Mode Register */
__IO TWIHS_SMR_Type TWIHS_SMR; /**< Offset: 0x08 (R/W 32) Slave Mode Register */
__IO TWIHS_IADR_Type TWIHS_IADR; /**< Offset: 0x0C (R/W 32) Internal Address Register */
__IO TWIHS_CWGR_Type TWIHS_CWGR; /**< Offset: 0x10 (R/W 32) Clock Waveform Generator Register */
__I uint32_t Reserved1[3];
__I TWIHS_SR_Type TWIHS_SR; /**< Offset: 0x20 (R/ 32) Status Register */
__O TWIHS_IER_Type TWIHS_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
__O TWIHS_IDR_Type TWIHS_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
__I TWIHS_IMR_Type TWIHS_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
__I TWIHS_RHR_Type TWIHS_RHR; /**< Offset: 0x30 (R/ 32) Receive Holding Register */
__O TWIHS_THR_Type TWIHS_THR; /**< Offset: 0x34 ( /W 32) Transmit Holding Register */
__IO TWIHS_SMBTR_Type TWIHS_SMBTR; /**< Offset: 0x38 (R/W 32) SMBus Timing Register */
__I uint32_t Reserved2[2];
__IO TWIHS_FILTR_Type TWIHS_FILTR; /**< Offset: 0x44 (R/W 32) Filter Register */
__I uint32_t Reserved3[1];
__IO TWIHS_SWMR_Type TWIHS_SWMR; /**< Offset: 0x4C (R/W 32) SleepWalking Matching Register */
__I uint32_t Reserved4[37];
__IO TWIHS_WPMR_Type TWIHS_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
__I TWIHS_WPSR_Type TWIHS_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
} Twihs;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Two-wire Interface High Speed */
#endif /* _SAME70_TWIHS_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for UART
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART_COMPONENT_H_
#define _SAME70_UART_COMPONENT_H_
#define _SAME70_UART_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Universal Asynchronous Receiver Transmitter
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR UART */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define UART_6418 /**< (UART) Module ID */
#define REV_UART R /**< (UART) Module revision */
/* -------- UART_CR : (UART Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /**< bit: 0..1 Reserved */
uint32_t RSTRX:1; /**< bit: 2 Reset Receiver */
uint32_t RSTTX:1; /**< bit: 3 Reset Transmitter */
uint32_t RXEN:1; /**< bit: 4 Receiver Enable */
uint32_t RXDIS:1; /**< bit: 5 Receiver Disable */
uint32_t TXEN:1; /**< bit: 6 Transmitter Enable */
uint32_t TXDIS:1; /**< bit: 7 Transmitter Disable */
uint32_t RSTSTA:1; /**< bit: 8 Reset Status */
uint32_t :3; /**< bit: 9..11 Reserved */
uint32_t REQCLR:1; /**< bit: 12 Request Clear */
uint32_t :19; /**< bit: 13..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_CR_OFFSET (0x00) /**< (UART_CR) Control Register Offset */
#define UART_CR_RSTRX_Pos 2 /**< (UART_CR) Reset Receiver Position */
#define UART_CR_RSTRX_Msk (_U_(0x1) << UART_CR_RSTRX_Pos) /**< (UART_CR) Reset Receiver Mask */
#define UART_CR_RSTRX UART_CR_RSTRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTRX_Msk instead */
#define UART_CR_RSTTX_Pos 3 /**< (UART_CR) Reset Transmitter Position */
#define UART_CR_RSTTX_Msk (_U_(0x1) << UART_CR_RSTTX_Pos) /**< (UART_CR) Reset Transmitter Mask */
#define UART_CR_RSTTX UART_CR_RSTTX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTTX_Msk instead */
#define UART_CR_RXEN_Pos 4 /**< (UART_CR) Receiver Enable Position */
#define UART_CR_RXEN_Msk (_U_(0x1) << UART_CR_RXEN_Pos) /**< (UART_CR) Receiver Enable Mask */
#define UART_CR_RXEN UART_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXEN_Msk instead */
#define UART_CR_RXDIS_Pos 5 /**< (UART_CR) Receiver Disable Position */
#define UART_CR_RXDIS_Msk (_U_(0x1) << UART_CR_RXDIS_Pos) /**< (UART_CR) Receiver Disable Mask */
#define UART_CR_RXDIS UART_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXDIS_Msk instead */
#define UART_CR_TXEN_Pos 6 /**< (UART_CR) Transmitter Enable Position */
#define UART_CR_TXEN_Msk (_U_(0x1) << UART_CR_TXEN_Pos) /**< (UART_CR) Transmitter Enable Mask */
#define UART_CR_TXEN UART_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXEN_Msk instead */
#define UART_CR_TXDIS_Pos 7 /**< (UART_CR) Transmitter Disable Position */
#define UART_CR_TXDIS_Msk (_U_(0x1) << UART_CR_TXDIS_Pos) /**< (UART_CR) Transmitter Disable Mask */
#define UART_CR_TXDIS UART_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXDIS_Msk instead */
#define UART_CR_RSTSTA_Pos 8 /**< (UART_CR) Reset Status Position */
#define UART_CR_RSTSTA_Msk (_U_(0x1) << UART_CR_RSTSTA_Pos) /**< (UART_CR) Reset Status Mask */
#define UART_CR_RSTSTA UART_CR_RSTSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTSTA_Msk instead */
#define UART_CR_REQCLR_Pos 12 /**< (UART_CR) Request Clear Position */
#define UART_CR_REQCLR_Msk (_U_(0x1) << UART_CR_REQCLR_Pos) /**< (UART_CR) Request Clear Mask */
#define UART_CR_REQCLR UART_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_REQCLR_Msk instead */
#define UART_CR_MASK _U_(0x11FC) /**< \deprecated (UART_CR) Register MASK (Use UART_CR_Msk instead) */
#define UART_CR_Msk _U_(0x11FC) /**< (UART_CR) Register Mask */
/* -------- UART_MR : (UART Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :4; /**< bit: 0..3 Reserved */
uint32_t FILTER:1; /**< bit: 4 Receiver Digital Filter */
uint32_t :4; /**< bit: 5..8 Reserved */
uint32_t PAR:3; /**< bit: 9..11 Parity Type */
uint32_t BRSRCCK:1; /**< bit: 12 Baud Rate Source Clock */
uint32_t :1; /**< bit: 13 Reserved */
uint32_t CHMODE:2; /**< bit: 14..15 Channel Mode */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_MR_OFFSET (0x04) /**< (UART_MR) Mode Register Offset */
#define UART_MR_FILTER_Pos 4 /**< (UART_MR) Receiver Digital Filter Position */
#define UART_MR_FILTER_Msk (_U_(0x1) << UART_MR_FILTER_Pos) /**< (UART_MR) Receiver Digital Filter Mask */
#define UART_MR_FILTER UART_MR_FILTER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_FILTER_Msk instead */
#define UART_MR_FILTER_DISABLED_Val _U_(0x0) /**< (UART_MR) UART does not filter the receive line. */
#define UART_MR_FILTER_ENABLED_Val _U_(0x1) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */
#define UART_MR_FILTER_DISABLED (UART_MR_FILTER_DISABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART does not filter the receive line. Position */
#define UART_MR_FILTER_ENABLED (UART_MR_FILTER_ENABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). Position */
#define UART_MR_PAR_Pos 9 /**< (UART_MR) Parity Type Position */
#define UART_MR_PAR_Msk (_U_(0x7) << UART_MR_PAR_Pos) /**< (UART_MR) Parity Type Mask */
#define UART_MR_PAR(value) (UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))
#define UART_MR_PAR_EVEN_Val _U_(0x0) /**< (UART_MR) Even Parity */
#define UART_MR_PAR_ODD_Val _U_(0x1) /**< (UART_MR) Odd Parity */
#define UART_MR_PAR_SPACE_Val _U_(0x2) /**< (UART_MR) Space: parity forced to 0 */
#define UART_MR_PAR_MARK_Val _U_(0x3) /**< (UART_MR) Mark: parity forced to 1 */
#define UART_MR_PAR_NO_Val _U_(0x4) /**< (UART_MR) No parity */
#define UART_MR_PAR_EVEN (UART_MR_PAR_EVEN_Val << UART_MR_PAR_Pos) /**< (UART_MR) Even Parity Position */
#define UART_MR_PAR_ODD (UART_MR_PAR_ODD_Val << UART_MR_PAR_Pos) /**< (UART_MR) Odd Parity Position */
#define UART_MR_PAR_SPACE (UART_MR_PAR_SPACE_Val << UART_MR_PAR_Pos) /**< (UART_MR) Space: parity forced to 0 Position */
#define UART_MR_PAR_MARK (UART_MR_PAR_MARK_Val << UART_MR_PAR_Pos) /**< (UART_MR) Mark: parity forced to 1 Position */
#define UART_MR_PAR_NO (UART_MR_PAR_NO_Val << UART_MR_PAR_Pos) /**< (UART_MR) No parity Position */
#define UART_MR_BRSRCCK_Pos 12 /**< (UART_MR) Baud Rate Source Clock Position */
#define UART_MR_BRSRCCK_Msk (_U_(0x1) << UART_MR_BRSRCCK_Pos) /**< (UART_MR) Baud Rate Source Clock Mask */
#define UART_MR_BRSRCCK UART_MR_BRSRCCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_BRSRCCK_Msk instead */
#define UART_MR_BRSRCCK_PERIPH_CLK_Val _U_(0x0) /**< (UART_MR) The baud rate is driven by the peripheral clock */
#define UART_MR_BRSRCCK_PMC_PCK_Val _U_(0x1) /**< (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */
#define UART_MR_BRSRCCK_PERIPH_CLK (UART_MR_BRSRCCK_PERIPH_CLK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by the peripheral clock Position */
#define UART_MR_BRSRCCK_PMC_PCK (UART_MR_BRSRCCK_PMC_PCK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). Position */
#define UART_MR_CHMODE_Pos 14 /**< (UART_MR) Channel Mode Position */
#define UART_MR_CHMODE_Msk (_U_(0x3) << UART_MR_CHMODE_Pos) /**< (UART_MR) Channel Mode Mask */
#define UART_MR_CHMODE(value) (UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))
#define UART_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (UART_MR) Normal mode */
#define UART_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (UART_MR) Automatic echo */
#define UART_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (UART_MR) Local loopback */
#define UART_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (UART_MR) Remote loopback */
#define UART_MR_CHMODE_NORMAL (UART_MR_CHMODE_NORMAL_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Normal mode Position */
#define UART_MR_CHMODE_AUTOMATIC (UART_MR_CHMODE_AUTOMATIC_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Automatic echo Position */
#define UART_MR_CHMODE_LOCAL_LOOPBACK (UART_MR_CHMODE_LOCAL_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Local loopback Position */
#define UART_MR_CHMODE_REMOTE_LOOPBACK (UART_MR_CHMODE_REMOTE_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Remote loopback Position */
#define UART_MR_MASK _U_(0xDE10) /**< \deprecated (UART_MR) Register MASK (Use UART_MR_Msk instead) */
#define UART_MR_Msk _U_(0xDE10) /**< (UART_MR) Register Mask */
/* -------- UART_IER : (UART Offset: 0x08) (/W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXRDY:1; /**< bit: 0 Enable RXRDY Interrupt */
uint32_t TXRDY:1; /**< bit: 1 Enable TXRDY Interrupt */
uint32_t :3; /**< bit: 2..4 Reserved */
uint32_t OVRE:1; /**< bit: 5 Enable Overrun Error Interrupt */
uint32_t FRAME:1; /**< bit: 6 Enable Framing Error Interrupt */
uint32_t PARE:1; /**< bit: 7 Enable Parity Error Interrupt */
uint32_t :1; /**< bit: 8 Reserved */
uint32_t TXEMPTY:1; /**< bit: 9 Enable TXEMPTY Interrupt */
uint32_t :5; /**< bit: 10..14 Reserved */
uint32_t CMP:1; /**< bit: 15 Enable Comparison Interrupt */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_IER_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_IER_OFFSET (0x08) /**< (UART_IER) Interrupt Enable Register Offset */
#define UART_IER_RXRDY_Pos 0 /**< (UART_IER) Enable RXRDY Interrupt Position */
#define UART_IER_RXRDY_Msk (_U_(0x1) << UART_IER_RXRDY_Pos) /**< (UART_IER) Enable RXRDY Interrupt Mask */
#define UART_IER_RXRDY UART_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_RXRDY_Msk instead */
#define UART_IER_TXRDY_Pos 1 /**< (UART_IER) Enable TXRDY Interrupt Position */
#define UART_IER_TXRDY_Msk (_U_(0x1) << UART_IER_TXRDY_Pos) /**< (UART_IER) Enable TXRDY Interrupt Mask */
#define UART_IER_TXRDY UART_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXRDY_Msk instead */
#define UART_IER_OVRE_Pos 5 /**< (UART_IER) Enable Overrun Error Interrupt Position */
#define UART_IER_OVRE_Msk (_U_(0x1) << UART_IER_OVRE_Pos) /**< (UART_IER) Enable Overrun Error Interrupt Mask */
#define UART_IER_OVRE UART_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_OVRE_Msk instead */
#define UART_IER_FRAME_Pos 6 /**< (UART_IER) Enable Framing Error Interrupt Position */
#define UART_IER_FRAME_Msk (_U_(0x1) << UART_IER_FRAME_Pos) /**< (UART_IER) Enable Framing Error Interrupt Mask */
#define UART_IER_FRAME UART_IER_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_FRAME_Msk instead */
#define UART_IER_PARE_Pos 7 /**< (UART_IER) Enable Parity Error Interrupt Position */
#define UART_IER_PARE_Msk (_U_(0x1) << UART_IER_PARE_Pos) /**< (UART_IER) Enable Parity Error Interrupt Mask */
#define UART_IER_PARE UART_IER_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_PARE_Msk instead */
#define UART_IER_TXEMPTY_Pos 9 /**< (UART_IER) Enable TXEMPTY Interrupt Position */
#define UART_IER_TXEMPTY_Msk (_U_(0x1) << UART_IER_TXEMPTY_Pos) /**< (UART_IER) Enable TXEMPTY Interrupt Mask */
#define UART_IER_TXEMPTY UART_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXEMPTY_Msk instead */
#define UART_IER_CMP_Pos 15 /**< (UART_IER) Enable Comparison Interrupt Position */
#define UART_IER_CMP_Msk (_U_(0x1) << UART_IER_CMP_Pos) /**< (UART_IER) Enable Comparison Interrupt Mask */
#define UART_IER_CMP UART_IER_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_CMP_Msk instead */
#define UART_IER_MASK _U_(0x82E3) /**< \deprecated (UART_IER) Register MASK (Use UART_IER_Msk instead) */
#define UART_IER_Msk _U_(0x82E3) /**< (UART_IER) Register Mask */
/* -------- UART_IDR : (UART Offset: 0x0c) (/W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXRDY:1; /**< bit: 0 Disable RXRDY Interrupt */
uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */
uint32_t :3; /**< bit: 2..4 Reserved */
uint32_t OVRE:1; /**< bit: 5 Disable Overrun Error Interrupt */
uint32_t FRAME:1; /**< bit: 6 Disable Framing Error Interrupt */
uint32_t PARE:1; /**< bit: 7 Disable Parity Error Interrupt */
uint32_t :1; /**< bit: 8 Reserved */
uint32_t TXEMPTY:1; /**< bit: 9 Disable TXEMPTY Interrupt */
uint32_t :5; /**< bit: 10..14 Reserved */
uint32_t CMP:1; /**< bit: 15 Disable Comparison Interrupt */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_IDR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_IDR_OFFSET (0x0C) /**< (UART_IDR) Interrupt Disable Register Offset */
#define UART_IDR_RXRDY_Pos 0 /**< (UART_IDR) Disable RXRDY Interrupt Position */
#define UART_IDR_RXRDY_Msk (_U_(0x1) << UART_IDR_RXRDY_Pos) /**< (UART_IDR) Disable RXRDY Interrupt Mask */
#define UART_IDR_RXRDY UART_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_RXRDY_Msk instead */
#define UART_IDR_TXRDY_Pos 1 /**< (UART_IDR) Disable TXRDY Interrupt Position */
#define UART_IDR_TXRDY_Msk (_U_(0x1) << UART_IDR_TXRDY_Pos) /**< (UART_IDR) Disable TXRDY Interrupt Mask */
#define UART_IDR_TXRDY UART_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXRDY_Msk instead */
#define UART_IDR_OVRE_Pos 5 /**< (UART_IDR) Disable Overrun Error Interrupt Position */
#define UART_IDR_OVRE_Msk (_U_(0x1) << UART_IDR_OVRE_Pos) /**< (UART_IDR) Disable Overrun Error Interrupt Mask */
#define UART_IDR_OVRE UART_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_OVRE_Msk instead */
#define UART_IDR_FRAME_Pos 6 /**< (UART_IDR) Disable Framing Error Interrupt Position */
#define UART_IDR_FRAME_Msk (_U_(0x1) << UART_IDR_FRAME_Pos) /**< (UART_IDR) Disable Framing Error Interrupt Mask */
#define UART_IDR_FRAME UART_IDR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_FRAME_Msk instead */
#define UART_IDR_PARE_Pos 7 /**< (UART_IDR) Disable Parity Error Interrupt Position */
#define UART_IDR_PARE_Msk (_U_(0x1) << UART_IDR_PARE_Pos) /**< (UART_IDR) Disable Parity Error Interrupt Mask */
#define UART_IDR_PARE UART_IDR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_PARE_Msk instead */
#define UART_IDR_TXEMPTY_Pos 9 /**< (UART_IDR) Disable TXEMPTY Interrupt Position */
#define UART_IDR_TXEMPTY_Msk (_U_(0x1) << UART_IDR_TXEMPTY_Pos) /**< (UART_IDR) Disable TXEMPTY Interrupt Mask */
#define UART_IDR_TXEMPTY UART_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXEMPTY_Msk instead */
#define UART_IDR_CMP_Pos 15 /**< (UART_IDR) Disable Comparison Interrupt Position */
#define UART_IDR_CMP_Msk (_U_(0x1) << UART_IDR_CMP_Pos) /**< (UART_IDR) Disable Comparison Interrupt Mask */
#define UART_IDR_CMP UART_IDR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_CMP_Msk instead */
#define UART_IDR_MASK _U_(0x82E3) /**< \deprecated (UART_IDR) Register MASK (Use UART_IDR_Msk instead) */
#define UART_IDR_Msk _U_(0x82E3) /**< (UART_IDR) Register Mask */
/* -------- UART_IMR : (UART Offset: 0x10) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXRDY:1; /**< bit: 0 Mask RXRDY Interrupt */
uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */
uint32_t :3; /**< bit: 2..4 Reserved */
uint32_t OVRE:1; /**< bit: 5 Mask Overrun Error Interrupt */
uint32_t FRAME:1; /**< bit: 6 Mask Framing Error Interrupt */
uint32_t PARE:1; /**< bit: 7 Mask Parity Error Interrupt */
uint32_t :1; /**< bit: 8 Reserved */
uint32_t TXEMPTY:1; /**< bit: 9 Mask TXEMPTY Interrupt */
uint32_t :5; /**< bit: 10..14 Reserved */
uint32_t CMP:1; /**< bit: 15 Mask Comparison Interrupt */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_IMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_IMR_OFFSET (0x10) /**< (UART_IMR) Interrupt Mask Register Offset */
#define UART_IMR_RXRDY_Pos 0 /**< (UART_IMR) Mask RXRDY Interrupt Position */
#define UART_IMR_RXRDY_Msk (_U_(0x1) << UART_IMR_RXRDY_Pos) /**< (UART_IMR) Mask RXRDY Interrupt Mask */
#define UART_IMR_RXRDY UART_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_RXRDY_Msk instead */
#define UART_IMR_TXRDY_Pos 1 /**< (UART_IMR) Disable TXRDY Interrupt Position */
#define UART_IMR_TXRDY_Msk (_U_(0x1) << UART_IMR_TXRDY_Pos) /**< (UART_IMR) Disable TXRDY Interrupt Mask */
#define UART_IMR_TXRDY UART_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXRDY_Msk instead */
#define UART_IMR_OVRE_Pos 5 /**< (UART_IMR) Mask Overrun Error Interrupt Position */
#define UART_IMR_OVRE_Msk (_U_(0x1) << UART_IMR_OVRE_Pos) /**< (UART_IMR) Mask Overrun Error Interrupt Mask */
#define UART_IMR_OVRE UART_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_OVRE_Msk instead */
#define UART_IMR_FRAME_Pos 6 /**< (UART_IMR) Mask Framing Error Interrupt Position */
#define UART_IMR_FRAME_Msk (_U_(0x1) << UART_IMR_FRAME_Pos) /**< (UART_IMR) Mask Framing Error Interrupt Mask */
#define UART_IMR_FRAME UART_IMR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_FRAME_Msk instead */
#define UART_IMR_PARE_Pos 7 /**< (UART_IMR) Mask Parity Error Interrupt Position */
#define UART_IMR_PARE_Msk (_U_(0x1) << UART_IMR_PARE_Pos) /**< (UART_IMR) Mask Parity Error Interrupt Mask */
#define UART_IMR_PARE UART_IMR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_PARE_Msk instead */
#define UART_IMR_TXEMPTY_Pos 9 /**< (UART_IMR) Mask TXEMPTY Interrupt Position */
#define UART_IMR_TXEMPTY_Msk (_U_(0x1) << UART_IMR_TXEMPTY_Pos) /**< (UART_IMR) Mask TXEMPTY Interrupt Mask */
#define UART_IMR_TXEMPTY UART_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXEMPTY_Msk instead */
#define UART_IMR_CMP_Pos 15 /**< (UART_IMR) Mask Comparison Interrupt Position */
#define UART_IMR_CMP_Msk (_U_(0x1) << UART_IMR_CMP_Pos) /**< (UART_IMR) Mask Comparison Interrupt Mask */
#define UART_IMR_CMP UART_IMR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_CMP_Msk instead */
#define UART_IMR_MASK _U_(0x82E3) /**< \deprecated (UART_IMR) Register MASK (Use UART_IMR_Msk instead) */
#define UART_IMR_Msk _U_(0x82E3) /**< (UART_IMR) Register Mask */
/* -------- UART_SR : (UART Offset: 0x14) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXRDY:1; /**< bit: 0 Receiver Ready */
uint32_t TXRDY:1; /**< bit: 1 Transmitter Ready */
uint32_t :3; /**< bit: 2..4 Reserved */
uint32_t OVRE:1; /**< bit: 5 Overrun Error */
uint32_t FRAME:1; /**< bit: 6 Framing Error */
uint32_t PARE:1; /**< bit: 7 Parity Error */
uint32_t :1; /**< bit: 8 Reserved */
uint32_t TXEMPTY:1; /**< bit: 9 Transmitter Empty */
uint32_t :5; /**< bit: 10..14 Reserved */
uint32_t CMP:1; /**< bit: 15 Comparison Match */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_SR_OFFSET (0x14) /**< (UART_SR) Status Register Offset */
#define UART_SR_RXRDY_Pos 0 /**< (UART_SR) Receiver Ready Position */
#define UART_SR_RXRDY_Msk (_U_(0x1) << UART_SR_RXRDY_Pos) /**< (UART_SR) Receiver Ready Mask */
#define UART_SR_RXRDY UART_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_RXRDY_Msk instead */
#define UART_SR_TXRDY_Pos 1 /**< (UART_SR) Transmitter Ready Position */
#define UART_SR_TXRDY_Msk (_U_(0x1) << UART_SR_TXRDY_Pos) /**< (UART_SR) Transmitter Ready Mask */
#define UART_SR_TXRDY UART_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXRDY_Msk instead */
#define UART_SR_OVRE_Pos 5 /**< (UART_SR) Overrun Error Position */
#define UART_SR_OVRE_Msk (_U_(0x1) << UART_SR_OVRE_Pos) /**< (UART_SR) Overrun Error Mask */
#define UART_SR_OVRE UART_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_OVRE_Msk instead */
#define UART_SR_FRAME_Pos 6 /**< (UART_SR) Framing Error Position */
#define UART_SR_FRAME_Msk (_U_(0x1) << UART_SR_FRAME_Pos) /**< (UART_SR) Framing Error Mask */
#define UART_SR_FRAME UART_SR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_FRAME_Msk instead */
#define UART_SR_PARE_Pos 7 /**< (UART_SR) Parity Error Position */
#define UART_SR_PARE_Msk (_U_(0x1) << UART_SR_PARE_Pos) /**< (UART_SR) Parity Error Mask */
#define UART_SR_PARE UART_SR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_PARE_Msk instead */
#define UART_SR_TXEMPTY_Pos 9 /**< (UART_SR) Transmitter Empty Position */
#define UART_SR_TXEMPTY_Msk (_U_(0x1) << UART_SR_TXEMPTY_Pos) /**< (UART_SR) Transmitter Empty Mask */
#define UART_SR_TXEMPTY UART_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXEMPTY_Msk instead */
#define UART_SR_CMP_Pos 15 /**< (UART_SR) Comparison Match Position */
#define UART_SR_CMP_Msk (_U_(0x1) << UART_SR_CMP_Pos) /**< (UART_SR) Comparison Match Mask */
#define UART_SR_CMP UART_SR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_CMP_Msk instead */
#define UART_SR_MASK _U_(0x82E3) /**< \deprecated (UART_SR) Register MASK (Use UART_SR_Msk instead) */
#define UART_SR_Msk _U_(0x82E3) /**< (UART_SR) Register Mask */
/* -------- UART_RHR : (UART Offset: 0x18) (R/ 32) Receive Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXCHR:8; /**< bit: 0..7 Received Character */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_RHR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_RHR_OFFSET (0x18) /**< (UART_RHR) Receive Holding Register Offset */
#define UART_RHR_RXCHR_Pos 0 /**< (UART_RHR) Received Character Position */
#define UART_RHR_RXCHR_Msk (_U_(0xFF) << UART_RHR_RXCHR_Pos) /**< (UART_RHR) Received Character Mask */
#define UART_RHR_RXCHR(value) (UART_RHR_RXCHR_Msk & ((value) << UART_RHR_RXCHR_Pos))
#define UART_RHR_MASK _U_(0xFF) /**< \deprecated (UART_RHR) Register MASK (Use UART_RHR_Msk instead) */
#define UART_RHR_Msk _U_(0xFF) /**< (UART_RHR) Register Mask */
/* -------- UART_THR : (UART Offset: 0x1c) (/W 32) Transmit Holding Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TXCHR:8; /**< bit: 0..7 Character to be Transmitted */
uint32_t :24; /**< bit: 8..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_THR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_THR_OFFSET (0x1C) /**< (UART_THR) Transmit Holding Register Offset */
#define UART_THR_TXCHR_Pos 0 /**< (UART_THR) Character to be Transmitted Position */
#define UART_THR_TXCHR_Msk (_U_(0xFF) << UART_THR_TXCHR_Pos) /**< (UART_THR) Character to be Transmitted Mask */
#define UART_THR_TXCHR(value) (UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))
#define UART_THR_MASK _U_(0xFF) /**< \deprecated (UART_THR) Register MASK (Use UART_THR_Msk instead) */
#define UART_THR_Msk _U_(0xFF) /**< (UART_THR) Register Mask */
/* -------- UART_BRGR : (UART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CD:16; /**< bit: 0..15 Clock Divisor */
uint32_t :16; /**< bit: 16..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_BRGR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_BRGR_OFFSET (0x20) /**< (UART_BRGR) Baud Rate Generator Register Offset */
#define UART_BRGR_CD_Pos 0 /**< (UART_BRGR) Clock Divisor Position */
#define UART_BRGR_CD_Msk (_U_(0xFFFF) << UART_BRGR_CD_Pos) /**< (UART_BRGR) Clock Divisor Mask */
#define UART_BRGR_CD(value) (UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))
#define UART_BRGR_MASK _U_(0xFFFF) /**< \deprecated (UART_BRGR) Register MASK (Use UART_BRGR_Msk instead) */
#define UART_BRGR_Msk _U_(0xFFFF) /**< (UART_BRGR) Register Mask */
/* -------- UART_CMPR : (UART Offset: 0x24) (R/W 32) Comparison Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VAL1:8; /**< bit: 0..7 First Comparison Value for Received Character */
uint32_t :4; /**< bit: 8..11 Reserved */
uint32_t CMPMODE:1; /**< bit: 12 Comparison Mode */
uint32_t :1; /**< bit: 13 Reserved */
uint32_t CMPPAR:1; /**< bit: 14 Compare Parity */
uint32_t :1; /**< bit: 15 Reserved */
uint32_t VAL2:8; /**< bit: 16..23 Second Comparison Value for Received Character */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_CMPR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_CMPR_OFFSET (0x24) /**< (UART_CMPR) Comparison Register Offset */
#define UART_CMPR_VAL1_Pos 0 /**< (UART_CMPR) First Comparison Value for Received Character Position */
#define UART_CMPR_VAL1_Msk (_U_(0xFF) << UART_CMPR_VAL1_Pos) /**< (UART_CMPR) First Comparison Value for Received Character Mask */
#define UART_CMPR_VAL1(value) (UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))
#define UART_CMPR_CMPMODE_Pos 12 /**< (UART_CMPR) Comparison Mode Position */
#define UART_CMPR_CMPMODE_Msk (_U_(0x1) << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison Mode Mask */
#define UART_CMPR_CMPMODE UART_CMPR_CMPMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPMODE_Msk instead */
#define UART_CMPR_CMPMODE_FLAG_ONLY_Val _U_(0x0) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. */
#define UART_CMPR_CMPMODE_START_CONDITION_Val _U_(0x1) /**< (UART_CMPR) Comparison condition must be met to start reception. */
#define UART_CMPR_CMPMODE_FLAG_ONLY (UART_CMPR_CMPMODE_FLAG_ONLY_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. Position */
#define UART_CMPR_CMPMODE_START_CONDITION (UART_CMPR_CMPMODE_START_CONDITION_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison condition must be met to start reception. Position */
#define UART_CMPR_CMPPAR_Pos 14 /**< (UART_CMPR) Compare Parity Position */
#define UART_CMPR_CMPPAR_Msk (_U_(0x1) << UART_CMPR_CMPPAR_Pos) /**< (UART_CMPR) Compare Parity Mask */
#define UART_CMPR_CMPPAR UART_CMPR_CMPPAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPPAR_Msk instead */
#define UART_CMPR_VAL2_Pos 16 /**< (UART_CMPR) Second Comparison Value for Received Character Position */
#define UART_CMPR_VAL2_Msk (_U_(0xFF) << UART_CMPR_VAL2_Pos) /**< (UART_CMPR) Second Comparison Value for Received Character Mask */
#define UART_CMPR_VAL2(value) (UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))
#define UART_CMPR_MASK _U_(0xFF50FF) /**< \deprecated (UART_CMPR) Register MASK (Use UART_CMPR_Msk instead) */
#define UART_CMPR_Msk _U_(0xFF50FF) /**< (UART_CMPR) Register Mask */
/* -------- UART_WPMR : (UART Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
uint32_t :7; /**< bit: 1..7 Reserved */
uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UART_WPMR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UART_WPMR_OFFSET (0xE4) /**< (UART_WPMR) Write Protection Mode Register Offset */
#define UART_WPMR_WPEN_Pos 0 /**< (UART_WPMR) Write Protection Enable Position */
#define UART_WPMR_WPEN_Msk (_U_(0x1) << UART_WPMR_WPEN_Pos) /**< (UART_WPMR) Write Protection Enable Mask */
#define UART_WPMR_WPEN UART_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_WPMR_WPEN_Msk instead */
#define UART_WPMR_WPKEY_Pos 8 /**< (UART_WPMR) Write Protection Key Position */
#define UART_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Write Protection Key Mask */
#define UART_WPMR_WPKEY(value) (UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))
#define UART_WPMR_WPKEY_PASSWD_Val _U_(0x554152) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
#define UART_WPMR_WPKEY_PASSWD (UART_WPMR_WPKEY_PASSWD_Val << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
#define UART_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (UART_WPMR) Register MASK (Use UART_WPMR_Msk instead) */
#define UART_WPMR_Msk _U_(0xFFFFFF01) /**< (UART_WPMR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief UART hardware registers */
typedef struct {
__O uint32_t UART_CR; /**< (UART Offset: 0x00) Control Register */
__IO uint32_t UART_MR; /**< (UART Offset: 0x04) Mode Register */
__O uint32_t UART_IER; /**< (UART Offset: 0x08) Interrupt Enable Register */
__O uint32_t UART_IDR; /**< (UART Offset: 0x0C) Interrupt Disable Register */
__I uint32_t UART_IMR; /**< (UART Offset: 0x10) Interrupt Mask Register */
__I uint32_t UART_SR; /**< (UART Offset: 0x14) Status Register */
__I uint32_t UART_RHR; /**< (UART Offset: 0x18) Receive Holding Register */
__O uint32_t UART_THR; /**< (UART Offset: 0x1C) Transmit Holding Register */
__IO uint32_t UART_BRGR; /**< (UART Offset: 0x20) Baud Rate Generator Register */
__IO uint32_t UART_CMPR; /**< (UART Offset: 0x24) Comparison Register */
RoReg8 Reserved1[0xBC];
__IO uint32_t UART_WPMR; /**< (UART Offset: 0xE4) Write Protection Mode Register */
} Uart;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief UART hardware registers */
typedef struct {
__O UART_CR_Type UART_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO UART_MR_Type UART_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__O UART_IER_Type UART_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */
__O UART_IDR_Type UART_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */
__I UART_IMR_Type UART_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */
__I UART_SR_Type UART_SR; /**< Offset: 0x14 (R/ 32) Status Register */
__I UART_RHR_Type UART_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */
__O UART_THR_Type UART_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */
__IO UART_BRGR_Type UART_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */
__IO UART_CMPR_Type UART_CMPR; /**< Offset: 0x24 (R/W 32) Comparison Register */
__I uint32_t Reserved1[47];
__IO UART_WPMR_Type UART_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
} Uart;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Universal Asynchronous Receiver Transmitter */
#endif /* _SAME70_UART_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for UTMI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UTMI_COMPONENT_H_
#define _SAME70_UTMI_COMPONENT_H_
#define _SAME70_UTMI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 USB Transmitter Interface Macrocell
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR UTMI */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define UTMI_11300 /**< (UTMI) Module ID */
#define REV_UTMI A /**< (UTMI) Module revision */
/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RES0:1; /**< bit: 0 USB PORTx Reset */
uint32_t :3; /**< bit: 1..3 Reserved */
uint32_t ARIE:1; /**< bit: 4 OHCI Asynchronous Resume Interrupt Enable */
uint32_t APPSTART:1; /**< bit: 5 Reserved */
uint32_t :17; /**< bit: 6..22 Reserved */
uint32_t UDPPUDIS:1; /**< bit: 23 USB Device Pull-up Disable */
uint32_t :8; /**< bit: 24..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UTMI_OHCIICR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UTMI_OHCIICR_OFFSET (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */
#define UTMI_OHCIICR_RES0_Pos 0 /**< (UTMI_OHCIICR) USB PORTx Reset Position */
#define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */
#define UTMI_OHCIICR_RES0 UTMI_OHCIICR_RES0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_RES0_Msk instead */
#define UTMI_OHCIICR_ARIE_Pos 4 /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */
#define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */
#define UTMI_OHCIICR_ARIE UTMI_OHCIICR_ARIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_ARIE_Msk instead */
#define UTMI_OHCIICR_APPSTART_Pos 5 /**< (UTMI_OHCIICR) Reserved Position */
#define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */
#define UTMI_OHCIICR_APPSTART UTMI_OHCIICR_APPSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_APPSTART_Msk instead */
#define UTMI_OHCIICR_UDPPUDIS_Pos 23 /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */
#define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */
#define UTMI_OHCIICR_UDPPUDIS UTMI_OHCIICR_UDPPUDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_UDPPUDIS_Msk instead */
#define UTMI_OHCIICR_MASK _U_(0x800031) /**< \deprecated (UTMI_OHCIICR) Register MASK (Use UTMI_OHCIICR_Msk instead) */
#define UTMI_OHCIICR_Msk _U_(0x800031) /**< (UTMI_OHCIICR) Register Mask */
/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FREQ:2; /**< bit: 0..1 UTMI Reference Clock Frequency */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} UTMI_CKTRIM_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define UTMI_CKTRIM_OFFSET (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */
#define UTMI_CKTRIM_FREQ_Pos 0 /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */
#define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */
#define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))
#define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */
#define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */
#define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */
#define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */
#define UTMI_CKTRIM_MASK _U_(0x03) /**< \deprecated (UTMI_CKTRIM) Register MASK (Use UTMI_CKTRIM_Msk instead) */
#define UTMI_CKTRIM_Msk _U_(0x03) /**< (UTMI_CKTRIM) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief UTMI hardware registers */
typedef struct {
RoReg8 Reserved1[0x10];
__IO uint32_t UTMI_OHCIICR; /**< (UTMI Offset: 0x10) OHCI Interrupt Configuration Register */
RoReg8 Reserved2[0x1C];
__IO uint32_t UTMI_CKTRIM; /**< (UTMI Offset: 0x30) UTMI Clock Trimming Register */
} Utmi;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief UTMI hardware registers */
typedef struct {
__I uint32_t Reserved1[4];
__IO UTMI_OHCIICR_Type UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */
__I uint32_t Reserved2[7];
__IO UTMI_CKTRIM_Type UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */
} Utmi;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of USB Transmitter Interface Macrocell */
#endif /* _SAME70_UTMI_COMPONENT_H_ */

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/**
* \file
*
* \brief Component description for WDT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_WDT_COMPONENT_H_
#define _SAME70_WDT_COMPONENT_H_
#define _SAME70_WDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
/** \addtogroup SAME_SAME70 Watchdog Timer
* @{
*/
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR WDT */
/* ========================================================================== */
#ifndef COMPONENT_TYPEDEF_STYLE
#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
#endif
#define WDT_6080 /**< (WDT) Module ID */
#define REV_WDT N /**< (WDT) Module revision */
/* -------- WDT_CR : (WDT Offset: 0x00) (/W 32) Control Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */
uint32_t :23; /**< bit: 1..23 Reserved */
uint32_t KEY:8; /**< bit: 24..31 Password */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} WDT_CR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CR_OFFSET (0x00) /**< (WDT_CR) Control Register Offset */
#define WDT_CR_WDRSTT_Pos 0 /**< (WDT_CR) Watchdog Restart Position */
#define WDT_CR_WDRSTT_Msk (_U_(0x1) << WDT_CR_WDRSTT_Pos) /**< (WDT_CR) Watchdog Restart Mask */
#define WDT_CR_WDRSTT WDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_CR_WDRSTT_Msk instead */
#define WDT_CR_KEY_Pos 24 /**< (WDT_CR) Password Position */
#define WDT_CR_KEY_Msk (_U_(0xFF) << WDT_CR_KEY_Pos) /**< (WDT_CR) Password Mask */
#define WDT_CR_KEY(value) (WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))
#define WDT_CR_KEY_PASSWD_Val _U_(0xA5) /**< (WDT_CR) Writing any other value in this field aborts the write operation. */
#define WDT_CR_KEY_PASSWD (WDT_CR_KEY_PASSWD_Val << WDT_CR_KEY_Pos) /**< (WDT_CR) Writing any other value in this field aborts the write operation. Position */
#define WDT_CR_MASK _U_(0xFF000001) /**< \deprecated (WDT_CR) Register MASK (Use WDT_CR_Msk instead) */
#define WDT_CR_Msk _U_(0xFF000001) /**< (WDT_CR) Register Mask */
/* -------- WDT_MR : (WDT Offset: 0x04) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */
uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */
uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */
uint32_t :1; /**< bit: 14 Reserved */
uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */
uint32_t WDD:12; /**< bit: 16..27 Watchdog Delta Value */
uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */
uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */
uint32_t :2; /**< bit: 30..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} WDT_MR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_MR_OFFSET (0x04) /**< (WDT_MR) Mode Register Offset */
#define WDT_MR_WDV_Pos 0 /**< (WDT_MR) Watchdog Counter Value Position */
#define WDT_MR_WDV_Msk (_U_(0xFFF) << WDT_MR_WDV_Pos) /**< (WDT_MR) Watchdog Counter Value Mask */
#define WDT_MR_WDV(value) (WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))
#define WDT_MR_WDFIEN_Pos 12 /**< (WDT_MR) Watchdog Fault Interrupt Enable Position */
#define WDT_MR_WDFIEN_Msk (_U_(0x1) << WDT_MR_WDFIEN_Pos) /**< (WDT_MR) Watchdog Fault Interrupt Enable Mask */
#define WDT_MR_WDFIEN WDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDFIEN_Msk instead */
#define WDT_MR_WDRSTEN_Pos 13 /**< (WDT_MR) Watchdog Reset Enable Position */
#define WDT_MR_WDRSTEN_Msk (_U_(0x1) << WDT_MR_WDRSTEN_Pos) /**< (WDT_MR) Watchdog Reset Enable Mask */
#define WDT_MR_WDRSTEN WDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDRSTEN_Msk instead */
#define WDT_MR_WDDIS_Pos 15 /**< (WDT_MR) Watchdog Disable Position */
#define WDT_MR_WDDIS_Msk (_U_(0x1) << WDT_MR_WDDIS_Pos) /**< (WDT_MR) Watchdog Disable Mask */
#define WDT_MR_WDDIS WDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDIS_Msk instead */
#define WDT_MR_WDD_Pos 16 /**< (WDT_MR) Watchdog Delta Value Position */
#define WDT_MR_WDD_Msk (_U_(0xFFF) << WDT_MR_WDD_Pos) /**< (WDT_MR) Watchdog Delta Value Mask */
#define WDT_MR_WDD(value) (WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))
#define WDT_MR_WDDBGHLT_Pos 28 /**< (WDT_MR) Watchdog Debug Halt Position */
#define WDT_MR_WDDBGHLT_Msk (_U_(0x1) << WDT_MR_WDDBGHLT_Pos) /**< (WDT_MR) Watchdog Debug Halt Mask */
#define WDT_MR_WDDBGHLT WDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDBGHLT_Msk instead */
#define WDT_MR_WDIDLEHLT_Pos 29 /**< (WDT_MR) Watchdog Idle Halt Position */
#define WDT_MR_WDIDLEHLT_Msk (_U_(0x1) << WDT_MR_WDIDLEHLT_Pos) /**< (WDT_MR) Watchdog Idle Halt Mask */
#define WDT_MR_WDIDLEHLT WDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDIDLEHLT_Msk instead */
#define WDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (WDT_MR) Register MASK (Use WDT_MR_Msk instead) */
#define WDT_MR_Msk _U_(0x3FFFBFFF) /**< (WDT_MR) Register Mask */
/* -------- WDT_SR : (WDT Offset: 0x08) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow (cleared on read) */
uint32_t WDERR:1; /**< bit: 1 Watchdog Error (cleared on read) */
uint32_t :30; /**< bit: 2..31 Reserved */
} bit; /**< Structure used for bit access */
uint32_t reg; /**< Type used for register access */
} WDT_SR_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_SR_OFFSET (0x08) /**< (WDT_SR) Status Register Offset */
#define WDT_SR_WDUNF_Pos 0 /**< (WDT_SR) Watchdog Underflow (cleared on read) Position */
#define WDT_SR_WDUNF_Msk (_U_(0x1) << WDT_SR_WDUNF_Pos) /**< (WDT_SR) Watchdog Underflow (cleared on read) Mask */
#define WDT_SR_WDUNF WDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDUNF_Msk instead */
#define WDT_SR_WDERR_Pos 1 /**< (WDT_SR) Watchdog Error (cleared on read) Position */
#define WDT_SR_WDERR_Msk (_U_(0x1) << WDT_SR_WDERR_Pos) /**< (WDT_SR) Watchdog Error (cleared on read) Mask */
#define WDT_SR_WDERR WDT_SR_WDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDERR_Msk instead */
#define WDT_SR_MASK _U_(0x03) /**< \deprecated (WDT_SR) Register MASK (Use WDT_SR_Msk instead) */
#define WDT_SR_Msk _U_(0x03) /**< (WDT_SR) Register Mask */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if COMPONENT_TYPEDEF_STYLE == 'R'
/** \brief WDT hardware registers */
typedef struct {
__O uint32_t WDT_CR; /**< (WDT Offset: 0x00) Control Register */
__IO uint32_t WDT_MR; /**< (WDT Offset: 0x04) Mode Register */
__I uint32_t WDT_SR; /**< (WDT Offset: 0x08) Status Register */
} Wdt;
#elif COMPONENT_TYPEDEF_STYLE == 'N'
/** \brief WDT hardware registers */
typedef struct {
__O WDT_CR_Type WDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */
__IO WDT_MR_Type WDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
__I WDT_SR_Type WDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */
} Wdt;
#else /* COMPONENT_TYPEDEF_STYLE */
#error Unknown component typedef style
#endif /* COMPONENT_TYPEDEF_STYLE */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Watchdog Timer */
#endif /* _SAME70_WDT_COMPONENT_H_ */

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/**
* \file
*
* \brief Instance description for ACC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_ACC_INSTANCE_H_
#define _SAME70_ACC_INSTANCE_H_
/* ========== Register definition for ACC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ACC_CR (0x40044000) /**< (ACC) Control Register */
#define REG_ACC_MR (0x40044004) /**< (ACC) Mode Register */
#define REG_ACC_IER (0x40044024) /**< (ACC) Interrupt Enable Register */
#define REG_ACC_IDR (0x40044028) /**< (ACC) Interrupt Disable Register */
#define REG_ACC_IMR (0x4004402C) /**< (ACC) Interrupt Mask Register */
#define REG_ACC_ISR (0x40044030) /**< (ACC) Interrupt Status Register */
#define REG_ACC_ACR (0x40044094) /**< (ACC) Analog Control Register */
#define REG_ACC_WPMR (0x400440E4) /**< (ACC) Write Protection Mode Register */
#define REG_ACC_WPSR (0x400440E8) /**< (ACC) Write Protection Status Register */
#else
#define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< (ACC) Control Register */
#define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< (ACC) Mode Register */
#define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< (ACC) Interrupt Enable Register */
#define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< (ACC) Interrupt Disable Register */
#define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< (ACC) Interrupt Mask Register */
#define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< (ACC) Interrupt Status Register */
#define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< (ACC) Analog Control Register */
#define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< (ACC) Write Protection Mode Register */
#define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< (ACC) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for ACC peripheral ========== */
#define ACC_INSTANCE_ID 33
#define ACC_CLOCK_ID 33
#endif /* _SAME70_ACC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for AES
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_AES_INSTANCE_H_
#define _SAME70_AES_INSTANCE_H_
/* ========== Register definition for AES peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AES_CR (0x4006C000) /**< (AES) Control Register */
#define REG_AES_MR (0x4006C004) /**< (AES) Mode Register */
#define REG_AES_IER (0x4006C010) /**< (AES) Interrupt Enable Register */
#define REG_AES_IDR (0x4006C014) /**< (AES) Interrupt Disable Register */
#define REG_AES_IMR (0x4006C018) /**< (AES) Interrupt Mask Register */
#define REG_AES_ISR (0x4006C01C) /**< (AES) Interrupt Status Register */
#define REG_AES_KEYWR (0x4006C020) /**< (AES) Key Word Register 0 */
#define REG_AES_KEYWR0 (0x4006C020) /**< (AES) Key Word Register 0 */
#define REG_AES_KEYWR1 (0x4006C024) /**< (AES) Key Word Register 1 */
#define REG_AES_KEYWR2 (0x4006C028) /**< (AES) Key Word Register 2 */
#define REG_AES_KEYWR3 (0x4006C02C) /**< (AES) Key Word Register 3 */
#define REG_AES_KEYWR4 (0x4006C030) /**< (AES) Key Word Register 4 */
#define REG_AES_KEYWR5 (0x4006C034) /**< (AES) Key Word Register 5 */
#define REG_AES_KEYWR6 (0x4006C038) /**< (AES) Key Word Register 6 */
#define REG_AES_KEYWR7 (0x4006C03C) /**< (AES) Key Word Register 7 */
#define REG_AES_IDATAR (0x4006C040) /**< (AES) Input Data Register 0 */
#define REG_AES_IDATAR0 (0x4006C040) /**< (AES) Input Data Register 0 */
#define REG_AES_IDATAR1 (0x4006C044) /**< (AES) Input Data Register 1 */
#define REG_AES_IDATAR2 (0x4006C048) /**< (AES) Input Data Register 2 */
#define REG_AES_IDATAR3 (0x4006C04C) /**< (AES) Input Data Register 3 */
#define REG_AES_ODATAR (0x4006C050) /**< (AES) Output Data Register 0 */
#define REG_AES_ODATAR0 (0x4006C050) /**< (AES) Output Data Register 0 */
#define REG_AES_ODATAR1 (0x4006C054) /**< (AES) Output Data Register 1 */
#define REG_AES_ODATAR2 (0x4006C058) /**< (AES) Output Data Register 2 */
#define REG_AES_ODATAR3 (0x4006C05C) /**< (AES) Output Data Register 3 */
#define REG_AES_IVR (0x4006C060) /**< (AES) Initialization Vector Register 0 */
#define REG_AES_IVR0 (0x4006C060) /**< (AES) Initialization Vector Register 0 */
#define REG_AES_IVR1 (0x4006C064) /**< (AES) Initialization Vector Register 1 */
#define REG_AES_IVR2 (0x4006C068) /**< (AES) Initialization Vector Register 2 */
#define REG_AES_IVR3 (0x4006C06C) /**< (AES) Initialization Vector Register 3 */
#define REG_AES_AADLENR (0x4006C070) /**< (AES) Additional Authenticated Data Length Register */
#define REG_AES_CLENR (0x4006C074) /**< (AES) Plaintext/Ciphertext Length Register */
#define REG_AES_GHASHR (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */
#define REG_AES_GHASHR0 (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */
#define REG_AES_GHASHR1 (0x4006C07C) /**< (AES) GCM Intermediate Hash Word Register 1 */
#define REG_AES_GHASHR2 (0x4006C080) /**< (AES) GCM Intermediate Hash Word Register 2 */
#define REG_AES_GHASHR3 (0x4006C084) /**< (AES) GCM Intermediate Hash Word Register 3 */
#define REG_AES_TAGR (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */
#define REG_AES_TAGR0 (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */
#define REG_AES_TAGR1 (0x4006C08C) /**< (AES) GCM Authentication Tag Word Register 1 */
#define REG_AES_TAGR2 (0x4006C090) /**< (AES) GCM Authentication Tag Word Register 2 */
#define REG_AES_TAGR3 (0x4006C094) /**< (AES) GCM Authentication Tag Word Register 3 */
#define REG_AES_CTRR (0x4006C098) /**< (AES) GCM Encryption Counter Value Register */
#define REG_AES_GCMHR (0x4006C09C) /**< (AES) GCM H Word Register 0 */
#define REG_AES_GCMHR0 (0x4006C09C) /**< (AES) GCM H Word Register 0 */
#define REG_AES_GCMHR1 (0x4006C0A0) /**< (AES) GCM H Word Register 1 */
#define REG_AES_GCMHR2 (0x4006C0A4) /**< (AES) GCM H Word Register 2 */
#define REG_AES_GCMHR3 (0x4006C0A8) /**< (AES) GCM H Word Register 3 */
#else
#define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< (AES) Control Register */
#define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< (AES) Mode Register */
#define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< (AES) Interrupt Enable Register */
#define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< (AES) Interrupt Disable Register */
#define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< (AES) Interrupt Mask Register */
#define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< (AES) Interrupt Status Register */
#define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */
#define REG_AES_KEYWR0 (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */
#define REG_AES_KEYWR1 (*(__O uint32_t*)0x4006C024U) /**< (AES) Key Word Register 1 */
#define REG_AES_KEYWR2 (*(__O uint32_t*)0x4006C028U) /**< (AES) Key Word Register 2 */
#define REG_AES_KEYWR3 (*(__O uint32_t*)0x4006C02CU) /**< (AES) Key Word Register 3 */
#define REG_AES_KEYWR4 (*(__O uint32_t*)0x4006C030U) /**< (AES) Key Word Register 4 */
#define REG_AES_KEYWR5 (*(__O uint32_t*)0x4006C034U) /**< (AES) Key Word Register 5 */
#define REG_AES_KEYWR6 (*(__O uint32_t*)0x4006C038U) /**< (AES) Key Word Register 6 */
#define REG_AES_KEYWR7 (*(__O uint32_t*)0x4006C03CU) /**< (AES) Key Word Register 7 */
#define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */
#define REG_AES_IDATAR0 (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */
#define REG_AES_IDATAR1 (*(__O uint32_t*)0x4006C044U) /**< (AES) Input Data Register 1 */
#define REG_AES_IDATAR2 (*(__O uint32_t*)0x4006C048U) /**< (AES) Input Data Register 2 */
#define REG_AES_IDATAR3 (*(__O uint32_t*)0x4006C04CU) /**< (AES) Input Data Register 3 */
#define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */
#define REG_AES_ODATAR0 (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */
#define REG_AES_ODATAR1 (*(__I uint32_t*)0x4006C054U) /**< (AES) Output Data Register 1 */
#define REG_AES_ODATAR2 (*(__I uint32_t*)0x4006C058U) /**< (AES) Output Data Register 2 */
#define REG_AES_ODATAR3 (*(__I uint32_t*)0x4006C05CU) /**< (AES) Output Data Register 3 */
#define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */
#define REG_AES_IVR0 (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */
#define REG_AES_IVR1 (*(__O uint32_t*)0x4006C064U) /**< (AES) Initialization Vector Register 1 */
#define REG_AES_IVR2 (*(__O uint32_t*)0x4006C068U) /**< (AES) Initialization Vector Register 2 */
#define REG_AES_IVR3 (*(__O uint32_t*)0x4006C06CU) /**< (AES) Initialization Vector Register 3 */
#define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< (AES) Additional Authenticated Data Length Register */
#define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< (AES) Plaintext/Ciphertext Length Register */
#define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */
#define REG_AES_GHASHR0 (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */
#define REG_AES_GHASHR1 (*(__IO uint32_t*)0x4006C07CU) /**< (AES) GCM Intermediate Hash Word Register 1 */
#define REG_AES_GHASHR2 (*(__IO uint32_t*)0x4006C080U) /**< (AES) GCM Intermediate Hash Word Register 2 */
#define REG_AES_GHASHR3 (*(__IO uint32_t*)0x4006C084U) /**< (AES) GCM Intermediate Hash Word Register 3 */
#define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */
#define REG_AES_TAGR0 (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */
#define REG_AES_TAGR1 (*(__I uint32_t*)0x4006C08CU) /**< (AES) GCM Authentication Tag Word Register 1 */
#define REG_AES_TAGR2 (*(__I uint32_t*)0x4006C090U) /**< (AES) GCM Authentication Tag Word Register 2 */
#define REG_AES_TAGR3 (*(__I uint32_t*)0x4006C094U) /**< (AES) GCM Authentication Tag Word Register 3 */
#define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< (AES) GCM Encryption Counter Value Register */
#define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */
#define REG_AES_GCMHR0 (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */
#define REG_AES_GCMHR1 (*(__IO uint32_t*)0x4006C0A0U) /**< (AES) GCM H Word Register 1 */
#define REG_AES_GCMHR2 (*(__IO uint32_t*)0x4006C0A4U) /**< (AES) GCM H Word Register 2 */
#define REG_AES_GCMHR3 (*(__IO uint32_t*)0x4006C0A8U) /**< (AES) GCM H Word Register 3 */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for AES peripheral ========== */
#define AES_INSTANCE_ID 56
#define AES_CLOCK_ID 56
#define AES_DMAC_ID_TX 37
#define AES_DMAC_ID_RX 38
#endif /* _SAME70_AES_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for AFEC0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_AFEC0_INSTANCE_H_
#define _SAME70_AFEC0_INSTANCE_H_
/* ========== Register definition for AFEC0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AFEC0_CR (0x4003C000) /**< (AFEC0) AFEC Control Register */
#define REG_AFEC0_MR (0x4003C004) /**< (AFEC0) AFEC Mode Register */
#define REG_AFEC0_EMR (0x4003C008) /**< (AFEC0) AFEC Extended Mode Register */
#define REG_AFEC0_SEQ1R (0x4003C00C) /**< (AFEC0) AFEC Channel Sequence 1 Register */
#define REG_AFEC0_SEQ2R (0x4003C010) /**< (AFEC0) AFEC Channel Sequence 2 Register */
#define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */
#define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */
#define REG_AFEC0_CHSR (0x4003C01C) /**< (AFEC0) AFEC Channel Status Register */
#define REG_AFEC0_LCDR (0x4003C020) /**< (AFEC0) AFEC Last Converted Data Register */
#define REG_AFEC0_IER (0x4003C024) /**< (AFEC0) AFEC Interrupt Enable Register */
#define REG_AFEC0_IDR (0x4003C028) /**< (AFEC0) AFEC Interrupt Disable Register */
#define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */
#define REG_AFEC0_ISR (0x4003C030) /**< (AFEC0) AFEC Interrupt Status Register */
#define REG_AFEC0_OVER (0x4003C04C) /**< (AFEC0) AFEC Overrun Status Register */
#define REG_AFEC0_CWR (0x4003C050) /**< (AFEC0) AFEC Compare Window Register */
#define REG_AFEC0_CGR (0x4003C054) /**< (AFEC0) AFEC Channel Gain Register */
#define REG_AFEC0_DIFFR (0x4003C060) /**< (AFEC0) AFEC Channel Differential Register */
#define REG_AFEC0_CSELR (0x4003C064) /**< (AFEC0) AFEC Channel Selection Register */
#define REG_AFEC0_CDR (0x4003C068) /**< (AFEC0) AFEC Channel Data Register */
#define REG_AFEC0_COCR (0x4003C06C) /**< (AFEC0) AFEC Channel Offset Compensation Register */
#define REG_AFEC0_TEMPMR (0x4003C070) /**< (AFEC0) AFEC Temperature Sensor Mode Register */
#define REG_AFEC0_TEMPCWR (0x4003C074) /**< (AFEC0) AFEC Temperature Compare Window Register */
#define REG_AFEC0_ACR (0x4003C094) /**< (AFEC0) AFEC Analog Control Register */
#define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */
#define REG_AFEC0_COSR (0x4003C0D0) /**< (AFEC0) AFEC Correction Select Register */
#define REG_AFEC0_CVR (0x4003C0D4) /**< (AFEC0) AFEC Correction Values Register */
#define REG_AFEC0_CECR (0x4003C0D8) /**< (AFEC0) AFEC Channel Error Correction Register */
#define REG_AFEC0_WPMR (0x4003C0E4) /**< (AFEC0) AFEC Write Protection Mode Register */
#define REG_AFEC0_WPSR (0x4003C0E8) /**< (AFEC0) AFEC Write Protection Status Register */
#else
#define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< (AFEC0) AFEC Control Register */
#define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< (AFEC0) AFEC Mode Register */
#define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< (AFEC0) AFEC Extended Mode Register */
#define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< (AFEC0) AFEC Channel Sequence 1 Register */
#define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< (AFEC0) AFEC Channel Sequence 2 Register */
#define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Register */
#define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Register */
#define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< (AFEC0) AFEC Channel Status Register */
#define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< (AFEC0) AFEC Last Converted Data Register */
#define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< (AFEC0) AFEC Interrupt Enable Register */
#define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< (AFEC0) AFEC Interrupt Disable Register */
#define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Register */
#define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< (AFEC0) AFEC Interrupt Status Register */
#define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< (AFEC0) AFEC Overrun Status Register */
#define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< (AFEC0) AFEC Compare Window Register */
#define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< (AFEC0) AFEC Channel Gain Register */
#define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< (AFEC0) AFEC Channel Differential Register */
#define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< (AFEC0) AFEC Channel Selection Register */
#define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< (AFEC0) AFEC Channel Data Register */
#define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< (AFEC0) AFEC Channel Offset Compensation Register */
#define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< (AFEC0) AFEC Temperature Sensor Mode Register */
#define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< (AFEC0) AFEC Temperature Compare Window Register */
#define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< (AFEC0) AFEC Analog Control Register */
#define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode Register */
#define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< (AFEC0) AFEC Correction Select Register */
#define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< (AFEC0) AFEC Correction Values Register */
#define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< (AFEC0) AFEC Channel Error Correction Register */
#define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< (AFEC0) AFEC Write Protection Mode Register */
#define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< (AFEC0) AFEC Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for AFEC0 peripheral ========== */
#define AFEC0_INSTANCE_ID 29
#define AFEC0_CLOCK_ID 29
#define AFEC0_DMAC_ID_RX 35
#endif /* _SAME70_AFEC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for AFEC1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_AFEC1_INSTANCE_H_
#define _SAME70_AFEC1_INSTANCE_H_
/* ========== Register definition for AFEC1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AFEC1_CR (0x40064000) /**< (AFEC1) AFEC Control Register */
#define REG_AFEC1_MR (0x40064004) /**< (AFEC1) AFEC Mode Register */
#define REG_AFEC1_EMR (0x40064008) /**< (AFEC1) AFEC Extended Mode Register */
#define REG_AFEC1_SEQ1R (0x4006400C) /**< (AFEC1) AFEC Channel Sequence 1 Register */
#define REG_AFEC1_SEQ2R (0x40064010) /**< (AFEC1) AFEC Channel Sequence 2 Register */
#define REG_AFEC1_CHER (0x40064014) /**< (AFEC1) AFEC Channel Enable Register */
#define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */
#define REG_AFEC1_CHSR (0x4006401C) /**< (AFEC1) AFEC Channel Status Register */
#define REG_AFEC1_LCDR (0x40064020) /**< (AFEC1) AFEC Last Converted Data Register */
#define REG_AFEC1_IER (0x40064024) /**< (AFEC1) AFEC Interrupt Enable Register */
#define REG_AFEC1_IDR (0x40064028) /**< (AFEC1) AFEC Interrupt Disable Register */
#define REG_AFEC1_IMR (0x4006402C) /**< (AFEC1) AFEC Interrupt Mask Register */
#define REG_AFEC1_ISR (0x40064030) /**< (AFEC1) AFEC Interrupt Status Register */
#define REG_AFEC1_OVER (0x4006404C) /**< (AFEC1) AFEC Overrun Status Register */
#define REG_AFEC1_CWR (0x40064050) /**< (AFEC1) AFEC Compare Window Register */
#define REG_AFEC1_CGR (0x40064054) /**< (AFEC1) AFEC Channel Gain Register */
#define REG_AFEC1_DIFFR (0x40064060) /**< (AFEC1) AFEC Channel Differential Register */
#define REG_AFEC1_CSELR (0x40064064) /**< (AFEC1) AFEC Channel Selection Register */
#define REG_AFEC1_CDR (0x40064068) /**< (AFEC1) AFEC Channel Data Register */
#define REG_AFEC1_COCR (0x4006406C) /**< (AFEC1) AFEC Channel Offset Compensation Register */
#define REG_AFEC1_TEMPMR (0x40064070) /**< (AFEC1) AFEC Temperature Sensor Mode Register */
#define REG_AFEC1_TEMPCWR (0x40064074) /**< (AFEC1) AFEC Temperature Compare Window Register */
#define REG_AFEC1_ACR (0x40064094) /**< (AFEC1) AFEC Analog Control Register */
#define REG_AFEC1_SHMR (0x400640A0) /**< (AFEC1) AFEC Sample & Hold Mode Register */
#define REG_AFEC1_COSR (0x400640D0) /**< (AFEC1) AFEC Correction Select Register */
#define REG_AFEC1_CVR (0x400640D4) /**< (AFEC1) AFEC Correction Values Register */
#define REG_AFEC1_CECR (0x400640D8) /**< (AFEC1) AFEC Channel Error Correction Register */
#define REG_AFEC1_WPMR (0x400640E4) /**< (AFEC1) AFEC Write Protection Mode Register */
#define REG_AFEC1_WPSR (0x400640E8) /**< (AFEC1) AFEC Write Protection Status Register */
#else
#define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< (AFEC1) AFEC Control Register */
#define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< (AFEC1) AFEC Mode Register */
#define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< (AFEC1) AFEC Extended Mode Register */
#define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< (AFEC1) AFEC Channel Sequence 1 Register */
#define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< (AFEC1) AFEC Channel Sequence 2 Register */
#define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< (AFEC1) AFEC Channel Enable Register */
#define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Register */
#define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< (AFEC1) AFEC Channel Status Register */
#define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< (AFEC1) AFEC Last Converted Data Register */
#define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< (AFEC1) AFEC Interrupt Enable Register */
#define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< (AFEC1) AFEC Interrupt Disable Register */
#define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< (AFEC1) AFEC Interrupt Mask Register */
#define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< (AFEC1) AFEC Interrupt Status Register */
#define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< (AFEC1) AFEC Overrun Status Register */
#define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< (AFEC1) AFEC Compare Window Register */
#define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< (AFEC1) AFEC Channel Gain Register */
#define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< (AFEC1) AFEC Channel Differential Register */
#define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< (AFEC1) AFEC Channel Selection Register */
#define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< (AFEC1) AFEC Channel Data Register */
#define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< (AFEC1) AFEC Channel Offset Compensation Register */
#define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< (AFEC1) AFEC Temperature Sensor Mode Register */
#define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< (AFEC1) AFEC Temperature Compare Window Register */
#define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< (AFEC1) AFEC Analog Control Register */
#define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< (AFEC1) AFEC Sample & Hold Mode Register */
#define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< (AFEC1) AFEC Correction Select Register */
#define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< (AFEC1) AFEC Correction Values Register */
#define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< (AFEC1) AFEC Channel Error Correction Register */
#define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< (AFEC1) AFEC Write Protection Mode Register */
#define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< (AFEC1) AFEC Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for AFEC1 peripheral ========== */
#define AFEC1_INSTANCE_ID 40
#define AFEC1_CLOCK_ID 40
#define AFEC1_DMAC_ID_RX 36
#endif /* _SAME70_AFEC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CHIPID
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_CHIPID_INSTANCE_H_
#define _SAME70_CHIPID_INSTANCE_H_
/* ========== Register definition for CHIPID peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CHIPID_CIDR (0x400E0940) /**< (CHIPID) Chip ID Register */
#define REG_CHIPID_EXID (0x400E0944) /**< (CHIPID) Chip ID Extension Register */
#else
#define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< (CHIPID) Chip ID Register */
#define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< (CHIPID) Chip ID Extension Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME70_CHIPID_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DACC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_DACC_INSTANCE_H_
#define _SAME70_DACC_INSTANCE_H_
/* ========== Register definition for DACC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DACC_CR (0x40040000) /**< (DACC) Control Register */
#define REG_DACC_MR (0x40040004) /**< (DACC) Mode Register */
#define REG_DACC_TRIGR (0x40040008) /**< (DACC) Trigger Register */
#define REG_DACC_CHER (0x40040010) /**< (DACC) Channel Enable Register */
#define REG_DACC_CHDR (0x40040014) /**< (DACC) Channel Disable Register */
#define REG_DACC_CHSR (0x40040018) /**< (DACC) Channel Status Register */
#define REG_DACC_CDR (0x4004001C) /**< (DACC) Conversion Data Register 0 */
#define REG_DACC_CDR0 (0x4004001C) /**< (DACC) Conversion Data Register 0 */
#define REG_DACC_CDR1 (0x40040020) /**< (DACC) Conversion Data Register 1 */
#define REG_DACC_IER (0x40040024) /**< (DACC) Interrupt Enable Register */
#define REG_DACC_IDR (0x40040028) /**< (DACC) Interrupt Disable Register */
#define REG_DACC_IMR (0x4004002C) /**< (DACC) Interrupt Mask Register */
#define REG_DACC_ISR (0x40040030) /**< (DACC) Interrupt Status Register */
#define REG_DACC_ACR (0x40040094) /**< (DACC) Analog Current Register */
#define REG_DACC_WPMR (0x400400E4) /**< (DACC) Write Protection Mode Register */
#define REG_DACC_WPSR (0x400400E8) /**< (DACC) Write Protection Status Register */
#else
#define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< (DACC) Control Register */
#define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< (DACC) Mode Register */
#define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< (DACC) Trigger Register */
#define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< (DACC) Channel Enable Register */
#define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< (DACC) Channel Disable Register */
#define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< (DACC) Channel Status Register */
#define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */
#define REG_DACC_CDR0 (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */
#define REG_DACC_CDR1 (*(__O uint32_t*)0x40040020U) /**< (DACC) Conversion Data Register 1 */
#define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< (DACC) Interrupt Enable Register */
#define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< (DACC) Interrupt Disable Register */
#define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< (DACC) Interrupt Mask Register */
#define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< (DACC) Interrupt Status Register */
#define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< (DACC) Analog Current Register */
#define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< (DACC) Write Protection Mode Register */
#define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< (DACC) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for DACC peripheral ========== */
#define DACC_INSTANCE_ID 30
#define DACC_CLOCK_ID 30
#define DACC_DMAC_ID_TX 30
#endif /* _SAME70_DACC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for EFC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_EFC_INSTANCE_H_
#define _SAME70_EFC_INSTANCE_H_
/* ========== Register definition for EFC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EEFC_FMR (0x400E0C00) /**< (EFC) EEFC Flash Mode Register */
#define REG_EEFC_FCR (0x400E0C04) /**< (EFC) EEFC Flash Command Register */
#define REG_EEFC_FSR (0x400E0C08) /**< (EFC) EEFC Flash Status Register */
#define REG_EEFC_FRR (0x400E0C0C) /**< (EFC) EEFC Flash Result Register */
#define REG_EEFC_WPMR (0x400E0CE4) /**< (EFC) Write Protection Mode Register */
#else
#define REG_EEFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< (EFC) EEFC Flash Mode Register */
#define REG_EEFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< (EFC) EEFC Flash Command Register */
#define REG_EEFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< (EFC) EEFC Flash Status Register */
#define REG_EEFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< (EFC) EEFC Flash Result Register */
#define REG_EEFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< (EFC) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for EFC peripheral ========== */
#define EFC_FLASH_SIZE 2097152
#define EFC_INSTANCE_ID 6
#define EFC_PAGES_PR_REGION 32
#define EFC_PAGE_SIZE 512
#endif /* _SAME70_EFC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for GMAC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_GMAC_INSTANCE_H_
#define _SAME70_GMAC_INSTANCE_H_
/* ========== Register definition for GMAC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GMAC_SAB1 (0x40050088) /**< (GMAC) Specific Address 1 Bottom Register 0 */
#define REG_GMAC_SAT1 (0x4005008C) /**< (GMAC) Specific Address 1 Top Register 0 */
#define REG_GMAC_SAB2 (0x40050090) /**< (GMAC) Specific Address 1 Bottom Register 1 */
#define REG_GMAC_SAT2 (0x40050094) /**< (GMAC) Specific Address 1 Top Register 1 */
#define REG_GMAC_SAB3 (0x40050098) /**< (GMAC) Specific Address 1 Bottom Register 2 */
#define REG_GMAC_SAT3 (0x4005009C) /**< (GMAC) Specific Address 1 Top Register 2 */
#define REG_GMAC_SAB4 (0x400500A0) /**< (GMAC) Specific Address 1 Bottom Register 3 */
#define REG_GMAC_SAT4 (0x400500A4) /**< (GMAC) Specific Address 1 Top Register 3 */
#define REG_GMAC_NCR (0x40050000) /**< (GMAC) Network Control Register */
#define REG_GMAC_NCFGR (0x40050004) /**< (GMAC) Network Configuration Register */
#define REG_GMAC_NSR (0x40050008) /**< (GMAC) Network Status Register */
#define REG_GMAC_UR (0x4005000C) /**< (GMAC) User Register */
#define REG_GMAC_DCFGR (0x40050010) /**< (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR (0x40050014) /**< (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB (0x40050018) /**< (GMAC) Receive Buffer Queue Base Address Register */
#define REG_GMAC_TBQB (0x4005001C) /**< (GMAC) Transmit Buffer Queue Base Address Register */
#define REG_GMAC_RSR (0x40050020) /**< (GMAC) Receive Status Register */
#define REG_GMAC_ISR (0x40050024) /**< (GMAC) Interrupt Status Register */
#define REG_GMAC_IER (0x40050028) /**< (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR (0x4005002C) /**< (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR (0x40050030) /**< (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN (0x40050034) /**< (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ (0x40050038) /**< (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ (0x4005003C) /**< (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_TPSF (0x40050040) /**< (GMAC) TX Partial Store and Forward Register */
#define REG_GMAC_RPSF (0x40050044) /**< (GMAC) RX Partial Store and Forward Register */
#define REG_GMAC_RJFML (0x40050048) /**< (GMAC) RX Jumbo Frame Max Length Register */
#define REG_GMAC_HRB (0x40050080) /**< (GMAC) Hash Register Bottom */
#define REG_GMAC_HRT (0x40050084) /**< (GMAC) Hash Register Top */
#define REG_GMAC_TIDM1 (0x400500A8) /**< (GMAC) Type ID Match 1 Register */
#define REG_GMAC_TIDM2 (0x400500AC) /**< (GMAC) Type ID Match 2 Register */
#define REG_GMAC_TIDM3 (0x400500B0) /**< (GMAC) Type ID Match 3 Register */
#define REG_GMAC_TIDM4 (0x400500B4) /**< (GMAC) Type ID Match 4 Register */
#define REG_GMAC_WOL (0x400500B8) /**< (GMAC) Wake on LAN Register */
#define REG_GMAC_IPGS (0x400500BC) /**< (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN (0x400500C0) /**< (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP (0x400500C4) /**< (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1 (0x400500C8) /**< (GMAC) Specific Address 1 Mask Bottom Register */
#define REG_GMAC_SAMT1 (0x400500CC) /**< (GMAC) Specific Address 1 Mask Top Register */
#define REG_GMAC_NSC (0x400500DC) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */
#define REG_GMAC_SCL (0x400500E0) /**< (GMAC) 1588 Timer Second Comparison Low Register */
#define REG_GMAC_SCH (0x400500E4) /**< (GMAC) 1588 Timer Second Comparison High Register */
#define REG_GMAC_EFTSH (0x400500E8) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */
#define REG_GMAC_EFRSH (0x400500EC) /**< (GMAC) PTP Event Frame Received Seconds High Register */
#define REG_GMAC_PEFTSH (0x400500F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
#define REG_GMAC_PEFRSH (0x400500F4) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */
#define REG_GMAC_OTLO (0x40050100) /**< (GMAC) Octets Transmitted Low Register */
#define REG_GMAC_OTHI (0x40050104) /**< (GMAC) Octets Transmitted High Register */
#define REG_GMAC_FT (0x40050108) /**< (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT (0x4005010C) /**< (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT (0x40050110) /**< (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT (0x40050114) /**< (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64 (0x40050118) /**< (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127 (0x4005011C) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255 (0x40050120) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511 (0x40050124) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023 (0x40050128) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518 (0x4005012C) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518 (0x40050130) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR (0x40050134) /**< (GMAC) Transmit Underruns Register */
#define REG_GMAC_SCF (0x40050138) /**< (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF (0x4005013C) /**< (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC (0x40050140) /**< (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC (0x40050144) /**< (GMAC) Late Collisions Register */
#define REG_GMAC_DTF (0x40050148) /**< (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE (0x4005014C) /**< (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO (0x40050150) /**< (GMAC) Octets Received Low Received Register */
#define REG_GMAC_ORHI (0x40050154) /**< (GMAC) Octets Received High Received Register */
#define REG_GMAC_FR (0x40050158) /**< (GMAC) Frames Received Register */
#define REG_GMAC_BCFR (0x4005015C) /**< (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR (0x40050160) /**< (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR (0x40050164) /**< (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64 (0x40050168) /**< (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127 (0x4005016C) /**< (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255 (0x40050170) /**< (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511 (0x40050174) /**< (GMAC) 256 to 511 Byte Frames Received Register */
#define REG_GMAC_TBFR1023 (0x40050178) /**< (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518 (0x4005017C) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR (0x40050180) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR (0x40050184) /**< (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR (0x40050188) /**< (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR (0x4005018C) /**< (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE (0x40050190) /**< (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE (0x40050194) /**< (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE (0x40050198) /**< (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE (0x4005019C) /**< (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE (0x400501A0) /**< (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE (0x400501A4) /**< (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE (0x400501A8) /**< (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE (0x400501AC) /**< (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE (0x400501B0) /**< (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TISUBN (0x400501BC) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
#define REG_GMAC_TSH (0x400501C0) /**< (GMAC) 1588 Timer Seconds High Register */
#define REG_GMAC_TSL (0x400501D0) /**< (GMAC) 1588 Timer Seconds Low Register */
#define REG_GMAC_TN (0x400501D4) /**< (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA (0x400501D8) /**< (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI (0x400501DC) /**< (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTSL (0x400501E0) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */
#define REG_GMAC_EFTN (0x400501E4) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
#define REG_GMAC_EFRSL (0x400501E8) /**< (GMAC) PTP Event Frame Received Seconds Low Register */
#define REG_GMAC_EFRN (0x400501EC) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */
#define REG_GMAC_PEFTSL (0x400501F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
#define REG_GMAC_PEFTN (0x400501F4) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
#define REG_GMAC_PEFRSL (0x400501F8) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */
#define REG_GMAC_PEFRN (0x400501FC) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
#define REG_GMAC_RXLPI (0x40050270) /**< (GMAC) Received LPI Transitions */
#define REG_GMAC_RXLPITIME (0x40050274) /**< (GMAC) Received LPI Time */
#define REG_GMAC_TXLPI (0x40050278) /**< (GMAC) Transmit LPI Transitions */
#define REG_GMAC_TXLPITIME (0x4005027C) /**< (GMAC) Transmit LPI Time */
#define REG_GMAC_ISRPQ (0x400503FC) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */
#define REG_GMAC_ISRPQ0 (0x400503FC) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */
#define REG_GMAC_ISRPQ1 (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 1 */
#define REG_GMAC_ISRPQ2 (0x40050404) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 2 */
#define REG_GMAC_ISRPQ3 (0x40050408) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 3 */
#define REG_GMAC_ISRPQ4 (0x4005040C) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 4 */
#define REG_GMAC_TBQBAPQ (0x4005043C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_TBQBAPQ0 (0x4005043C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_TBQBAPQ1 (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 1 */
#define REG_GMAC_TBQBAPQ2 (0x40050444) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 2 */
#define REG_GMAC_TBQBAPQ3 (0x40050448) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 3 */
#define REG_GMAC_TBQBAPQ4 (0x4005044C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 4 */
#define REG_GMAC_RBQBAPQ (0x4005047C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBQBAPQ0 (0x4005047C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBQBAPQ1 (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 1 */
#define REG_GMAC_RBQBAPQ2 (0x40050484) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 2 */
#define REG_GMAC_RBQBAPQ3 (0x40050488) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 3 */
#define REG_GMAC_RBQBAPQ4 (0x4005048C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 4 */
#define REG_GMAC_RBSRPQ (0x4005049C) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBSRPQ0 (0x4005049C) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBSRPQ1 (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 1 */
#define REG_GMAC_RBSRPQ2 (0x400504A4) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 2 */
#define REG_GMAC_RBSRPQ3 (0x400504A8) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 3 */
#define REG_GMAC_RBSRPQ4 (0x400504AC) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 4 */
#define REG_GMAC_CBSCR (0x400504BC) /**< (GMAC) Credit-Based Shaping Control Register */
#define REG_GMAC_CBSISQA (0x400504C0) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
#define REG_GMAC_CBSISQB (0x400504C4) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
#define REG_GMAC_ST1RPQ (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST1RPQ0 (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST1RPQ1 (0x40050504) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 1 */
#define REG_GMAC_ST1RPQ2 (0x40050508) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 2 */
#define REG_GMAC_ST1RPQ3 (0x4005050C) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 3 */
#define REG_GMAC_ST2RPQ (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST2RPQ0 (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST2RPQ1 (0x40050544) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 1 */
#define REG_GMAC_ST2RPQ2 (0x40050548) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 2 */
#define REG_GMAC_ST2RPQ3 (0x4005054C) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 3 */
#define REG_GMAC_ST2RPQ4 (0x40050550) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 4 */
#define REG_GMAC_ST2RPQ5 (0x40050554) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 5 */
#define REG_GMAC_ST2RPQ6 (0x40050558) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 6 */
#define REG_GMAC_ST2RPQ7 (0x4005055C) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 7 */
#define REG_GMAC_IERPQ (0x400505FC) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IERPQ0 (0x400505FC) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IERPQ1 (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IERPQ2 (0x40050604) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IERPQ3 (0x40050608) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IERPQ4 (0x4005060C) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 4 */
#define REG_GMAC_IDRPQ (0x4005061C) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IDRPQ0 (0x4005061C) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IDRPQ1 (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IDRPQ2 (0x40050624) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IDRPQ3 (0x40050628) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IDRPQ4 (0x4005062C) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 4 */
#define REG_GMAC_IMRPQ (0x4005063C) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IMRPQ0 (0x4005063C) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IMRPQ1 (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IMRPQ2 (0x40050644) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IMRPQ3 (0x40050648) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IMRPQ4 (0x4005064C) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 4 */
#define REG_GMAC_ST2ER (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 0 */
#define REG_GMAC_ST2ER0 (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 0 */
#define REG_GMAC_ST2ER1 (0x400506E4) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 1 */
#define REG_GMAC_ST2ER2 (0x400506E8) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 2 */
#define REG_GMAC_ST2ER3 (0x400506EC) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 3 */
#define REG_GMAC_ST2CW00 (0x40050700) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */
#define REG_GMAC_ST2CW10 (0x40050704) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */
#define REG_GMAC_ST2CW01 (0x40050708) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */
#define REG_GMAC_ST2CW11 (0x4005070C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */
#define REG_GMAC_ST2CW02 (0x40050710) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */
#define REG_GMAC_ST2CW12 (0x40050714) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */
#define REG_GMAC_ST2CW03 (0x40050718) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */
#define REG_GMAC_ST2CW13 (0x4005071C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */
#define REG_GMAC_ST2CW04 (0x40050720) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */
#define REG_GMAC_ST2CW14 (0x40050724) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */
#define REG_GMAC_ST2CW05 (0x40050728) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */
#define REG_GMAC_ST2CW15 (0x4005072C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */
#define REG_GMAC_ST2CW06 (0x40050730) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */
#define REG_GMAC_ST2CW16 (0x40050734) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */
#define REG_GMAC_ST2CW07 (0x40050738) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */
#define REG_GMAC_ST2CW17 (0x4005073C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */
#define REG_GMAC_ST2CW08 (0x40050740) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */
#define REG_GMAC_ST2CW18 (0x40050744) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */
#define REG_GMAC_ST2CW09 (0x40050748) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */
#define REG_GMAC_ST2CW19 (0x4005074C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */
#define REG_GMAC_ST2CW010 (0x40050750) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */
#define REG_GMAC_ST2CW110 (0x40050754) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */
#define REG_GMAC_ST2CW011 (0x40050758) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */
#define REG_GMAC_ST2CW111 (0x4005075C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */
#define REG_GMAC_ST2CW012 (0x40050760) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */
#define REG_GMAC_ST2CW112 (0x40050764) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */
#define REG_GMAC_ST2CW013 (0x40050768) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */
#define REG_GMAC_ST2CW113 (0x4005076C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */
#define REG_GMAC_ST2CW014 (0x40050770) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */
#define REG_GMAC_ST2CW114 (0x40050774) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */
#define REG_GMAC_ST2CW015 (0x40050778) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */
#define REG_GMAC_ST2CW115 (0x4005077C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */
#define REG_GMAC_ST2CW016 (0x40050780) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */
#define REG_GMAC_ST2CW116 (0x40050784) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */
#define REG_GMAC_ST2CW017 (0x40050788) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */
#define REG_GMAC_ST2CW117 (0x4005078C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */
#define REG_GMAC_ST2CW018 (0x40050790) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */
#define REG_GMAC_ST2CW118 (0x40050794) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */
#define REG_GMAC_ST2CW019 (0x40050798) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */
#define REG_GMAC_ST2CW119 (0x4005079C) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */
#define REG_GMAC_ST2CW020 (0x400507A0) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */
#define REG_GMAC_ST2CW120 (0x400507A4) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */
#define REG_GMAC_ST2CW021 (0x400507A8) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */
#define REG_GMAC_ST2CW121 (0x400507AC) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */
#define REG_GMAC_ST2CW022 (0x400507B0) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */
#define REG_GMAC_ST2CW122 (0x400507B4) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */
#define REG_GMAC_ST2CW023 (0x400507B8) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */
#define REG_GMAC_ST2CW123 (0x400507BC) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */
#else
#define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< (GMAC) Specific Address 1 Bottom Register 0 */
#define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< (GMAC) Specific Address 1 Top Register 0 */
#define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< (GMAC) Specific Address 1 Bottom Register 1 */
#define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< (GMAC) Specific Address 1 Top Register 1 */
#define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< (GMAC) Specific Address 1 Bottom Register 2 */
#define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< (GMAC) Specific Address 1 Top Register 2 */
#define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< (GMAC) Specific Address 1 Bottom Register 3 */
#define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< (GMAC) Specific Address 1 Top Register 3 */
#define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< (GMAC) Network Control Register */
#define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< (GMAC) Network Configuration Register */
#define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< (GMAC) Network Status Register */
#define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< (GMAC) User Register */
#define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< (GMAC) Receive Buffer Queue Base Address Register */
#define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< (GMAC) Transmit Buffer Queue Base Address Register */
#define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< (GMAC) Receive Status Register */
#define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< (GMAC) Interrupt Status Register */
#define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< (GMAC) TX Partial Store and Forward Register */
#define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< (GMAC) RX Partial Store and Forward Register */
#define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< (GMAC) RX Jumbo Frame Max Length Register */
#define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< (GMAC) Hash Register Bottom */
#define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< (GMAC) Hash Register Top */
#define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< (GMAC) Type ID Match 1 Register */
#define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< (GMAC) Type ID Match 2 Register */
#define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< (GMAC) Type ID Match 3 Register */
#define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< (GMAC) Type ID Match 4 Register */
#define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< (GMAC) Wake on LAN Register */
#define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< (GMAC) Specific Address 1 Mask Bottom Register */
#define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< (GMAC) Specific Address 1 Mask Top Register */
#define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */
#define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< (GMAC) 1588 Timer Second Comparison Low Register */
#define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< (GMAC) 1588 Timer Second Comparison High Register */
#define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */
#define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< (GMAC) PTP Event Frame Received Seconds High Register */
#define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
#define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */
#define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< (GMAC) Octets Transmitted Low Register */
#define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< (GMAC) Octets Transmitted High Register */
#define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< (GMAC) Transmit Underruns Register */
#define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< (GMAC) Late Collisions Register */
#define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< (GMAC) Octets Received Low Received Register */
#define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< (GMAC) Octets Received High Received Register */
#define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< (GMAC) Frames Received Register */
#define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< (GMAC) 256 to 511 Byte Frames Received Register */
#define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
#define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< (GMAC) 1588 Timer Seconds High Register */
#define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< (GMAC) 1588 Timer Seconds Low Register */
#define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */
#define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
#define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< (GMAC) PTP Event Frame Received Seconds Low Register */
#define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */
#define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
#define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
#define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */
#define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
#define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< (GMAC) Received LPI Transitions */
#define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< (GMAC) Received LPI Time */
#define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< (GMAC) Transmit LPI Transitions */
#define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< (GMAC) Transmit LPI Time */
#define REG_GMAC_ISRPQ (*(__I uint32_t*)0x400503FCU) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */
#define REG_GMAC_ISRPQ0 (*(__I uint32_t*)0x400503FCU) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 0 */
#define REG_GMAC_ISRPQ1 (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 1 */
#define REG_GMAC_ISRPQ2 (*(__I uint32_t*)0x40050404U) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 2 */
#define REG_GMAC_ISRPQ3 (*(__I uint32_t*)0x40050408U) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 3 */
#define REG_GMAC_ISRPQ4 (*(__I uint32_t*)0x4005040CU) /**< (GMAC) Interrupt Status Register Priority Queue (index = 1) 4 */
#define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x4005043CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_TBQBAPQ0 (*(__IO uint32_t*)0x4005043CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_TBQBAPQ1 (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 1 */
#define REG_GMAC_TBQBAPQ2 (*(__IO uint32_t*)0x40050444U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 2 */
#define REG_GMAC_TBQBAPQ3 (*(__IO uint32_t*)0x40050448U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 3 */
#define REG_GMAC_TBQBAPQ4 (*(__IO uint32_t*)0x4005044CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 4 */
#define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x4005047CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBQBAPQ0 (*(__IO uint32_t*)0x4005047CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBQBAPQ1 (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 1 */
#define REG_GMAC_RBQBAPQ2 (*(__IO uint32_t*)0x40050484U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 2 */
#define REG_GMAC_RBQBAPQ3 (*(__IO uint32_t*)0x40050488U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 3 */
#define REG_GMAC_RBQBAPQ4 (*(__IO uint32_t*)0x4005048CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 4 */
#define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x4005049CU) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBSRPQ0 (*(__IO uint32_t*)0x4005049CU) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 0 */
#define REG_GMAC_RBSRPQ1 (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 1 */
#define REG_GMAC_RBSRPQ2 (*(__IO uint32_t*)0x400504A4U) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 2 */
#define REG_GMAC_RBSRPQ3 (*(__IO uint32_t*)0x400504A8U) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 3 */
#define REG_GMAC_RBSRPQ4 (*(__IO uint32_t*)0x400504ACU) /**< (GMAC) Receive Buffer Size Register Priority Queue (index = 1) 4 */
#define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< (GMAC) Credit-Based Shaping Control Register */
#define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
#define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
#define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST1RPQ0 (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST1RPQ1 (*(__IO uint32_t*)0x40050504U) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 1 */
#define REG_GMAC_ST1RPQ2 (*(__IO uint32_t*)0x40050508U) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 2 */
#define REG_GMAC_ST1RPQ3 (*(__IO uint32_t*)0x4005050CU) /**< (GMAC) Screening Type 1 Register Priority Queue (index = 0) 3 */
#define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST2RPQ0 (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 0 */
#define REG_GMAC_ST2RPQ1 (*(__IO uint32_t*)0x40050544U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 1 */
#define REG_GMAC_ST2RPQ2 (*(__IO uint32_t*)0x40050548U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 2 */
#define REG_GMAC_ST2RPQ3 (*(__IO uint32_t*)0x4005054CU) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 3 */
#define REG_GMAC_ST2RPQ4 (*(__IO uint32_t*)0x40050550U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 4 */
#define REG_GMAC_ST2RPQ5 (*(__IO uint32_t*)0x40050554U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 5 */
#define REG_GMAC_ST2RPQ6 (*(__IO uint32_t*)0x40050558U) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 6 */
#define REG_GMAC_ST2RPQ7 (*(__IO uint32_t*)0x4005055CU) /**< (GMAC) Screening Type 2 Register Priority Queue (index = 0) 7 */
#define REG_GMAC_IERPQ (*(__O uint32_t*)0x400505FCU) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IERPQ0 (*(__O uint32_t*)0x400505FCU) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IERPQ1 (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IERPQ2 (*(__O uint32_t*)0x40050604U) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IERPQ3 (*(__O uint32_t*)0x40050608U) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IERPQ4 (*(__O uint32_t*)0x4005060CU) /**< (GMAC) Interrupt Enable Register Priority Queue (index = 1) 4 */
#define REG_GMAC_IDRPQ (*(__O uint32_t*)0x4005061CU) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IDRPQ0 (*(__O uint32_t*)0x4005061CU) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IDRPQ1 (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IDRPQ2 (*(__O uint32_t*)0x40050624U) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IDRPQ3 (*(__O uint32_t*)0x40050628U) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IDRPQ4 (*(__O uint32_t*)0x4005062CU) /**< (GMAC) Interrupt Disable Register Priority Queue (index = 1) 4 */
#define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x4005063CU) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IMRPQ0 (*(__IO uint32_t*)0x4005063CU) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 0 */
#define REG_GMAC_IMRPQ1 (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 1 */
#define REG_GMAC_IMRPQ2 (*(__IO uint32_t*)0x40050644U) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 2 */
#define REG_GMAC_IMRPQ3 (*(__IO uint32_t*)0x40050648U) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 3 */
#define REG_GMAC_IMRPQ4 (*(__IO uint32_t*)0x4005064CU) /**< (GMAC) Interrupt Mask Register Priority Queue (index = 1) 4 */
#define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 0 */
#define REG_GMAC_ST2ER0 (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 0 */
#define REG_GMAC_ST2ER1 (*(__IO uint32_t*)0x400506E4U) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 1 */
#define REG_GMAC_ST2ER2 (*(__IO uint32_t*)0x400506E8U) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 2 */
#define REG_GMAC_ST2ER3 (*(__IO uint32_t*)0x400506ECU) /**< (GMAC) Screening Type 2 Ethertype Register (index = 0) 3 */
#define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */
#define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */
#define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */
#define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */
#define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */
#define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */
#define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */
#define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */
#define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */
#define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */
#define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */
#define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */
#define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */
#define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */
#define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */
#define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */
#define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */
#define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */
#define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */
#define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */
#define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */
#define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */
#define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */
#define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */
#define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */
#define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */
#define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */
#define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */
#define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */
#define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */
#define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */
#define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */
#define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */
#define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */
#define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */
#define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */
#define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */
#define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */
#define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */
#define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */
#define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */
#define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */
#define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */
#define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */
#define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */
#define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */
#define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */
#define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for GMAC peripheral ========== */
#define GMAC_INSTANCE_ID 39
#define GMAC_CLOCK_ID 39
#endif /* _SAME70_GMAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for GPBR
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_GPBR_INSTANCE_H_
#define _SAME70_GPBR_INSTANCE_H_
/* ========== Register definition for GPBR peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GPBR_SYS_GPBR (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_SYS_GPBR0 (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_SYS_GPBR1 (0x400E1894) /**< (GPBR) General Purpose Backup Register 1 */
#define REG_GPBR_SYS_GPBR2 (0x400E1898) /**< (GPBR) General Purpose Backup Register 2 */
#define REG_GPBR_SYS_GPBR3 (0x400E189C) /**< (GPBR) General Purpose Backup Register 3 */
#define REG_GPBR_SYS_GPBR4 (0x400E18A0) /**< (GPBR) General Purpose Backup Register 4 */
#define REG_GPBR_SYS_GPBR5 (0x400E18A4) /**< (GPBR) General Purpose Backup Register 5 */
#define REG_GPBR_SYS_GPBR6 (0x400E18A8) /**< (GPBR) General Purpose Backup Register 6 */
#define REG_GPBR_SYS_GPBR7 (0x400E18AC) /**< (GPBR) General Purpose Backup Register 7 */
#else
#define REG_GPBR_SYS_GPBR (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_SYS_GPBR0 (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */
#define REG_GPBR_SYS_GPBR1 (*(__IO uint32_t*)0x400E1894U) /**< (GPBR) General Purpose Backup Register 1 */
#define REG_GPBR_SYS_GPBR2 (*(__IO uint32_t*)0x400E1898U) /**< (GPBR) General Purpose Backup Register 2 */
#define REG_GPBR_SYS_GPBR3 (*(__IO uint32_t*)0x400E189CU) /**< (GPBR) General Purpose Backup Register 3 */
#define REG_GPBR_SYS_GPBR4 (*(__IO uint32_t*)0x400E18A0U) /**< (GPBR) General Purpose Backup Register 4 */
#define REG_GPBR_SYS_GPBR5 (*(__IO uint32_t*)0x400E18A4U) /**< (GPBR) General Purpose Backup Register 5 */
#define REG_GPBR_SYS_GPBR6 (*(__IO uint32_t*)0x400E18A8U) /**< (GPBR) General Purpose Backup Register 6 */
#define REG_GPBR_SYS_GPBR7 (*(__IO uint32_t*)0x400E18ACU) /**< (GPBR) General Purpose Backup Register 7 */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME70_GPBR_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for HSMCI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_HSMCI_INSTANCE_H_
#define _SAME70_HSMCI_INSTANCE_H_
/* ========== Register definition for HSMCI peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_HSMCI_CR (0x40000000) /**< (HSMCI) Control Register */
#define REG_HSMCI_MR (0x40000004) /**< (HSMCI) Mode Register */
#define REG_HSMCI_DTOR (0x40000008) /**< (HSMCI) Data Timeout Register */
#define REG_HSMCI_SDCR (0x4000000C) /**< (HSMCI) SD/SDIO Card Register */
#define REG_HSMCI_ARGR (0x40000010) /**< (HSMCI) Argument Register */
#define REG_HSMCI_CMDR (0x40000014) /**< (HSMCI) Command Register */
#define REG_HSMCI_BLKR (0x40000018) /**< (HSMCI) Block Register */
#define REG_HSMCI_CSTOR (0x4000001C) /**< (HSMCI) Completion Signal Timeout Register */
#define REG_HSMCI_RSPR (0x40000020) /**< (HSMCI) Response Register 0 */
#define REG_HSMCI_RSPR0 (0x40000020) /**< (HSMCI) Response Register 0 */
#define REG_HSMCI_RSPR1 (0x40000024) /**< (HSMCI) Response Register 1 */
#define REG_HSMCI_RSPR2 (0x40000028) /**< (HSMCI) Response Register 2 */
#define REG_HSMCI_RSPR3 (0x4000002C) /**< (HSMCI) Response Register 3 */
#define REG_HSMCI_RDR (0x40000030) /**< (HSMCI) Receive Data Register */
#define REG_HSMCI_TDR (0x40000034) /**< (HSMCI) Transmit Data Register */
#define REG_HSMCI_SR (0x40000040) /**< (HSMCI) Status Register */
#define REG_HSMCI_IER (0x40000044) /**< (HSMCI) Interrupt Enable Register */
#define REG_HSMCI_IDR (0x40000048) /**< (HSMCI) Interrupt Disable Register */
#define REG_HSMCI_IMR (0x4000004C) /**< (HSMCI) Interrupt Mask Register */
#define REG_HSMCI_DMA (0x40000050) /**< (HSMCI) DMA Configuration Register */
#define REG_HSMCI_CFG (0x40000054) /**< (HSMCI) Configuration Register */
#define REG_HSMCI_WPMR (0x400000E4) /**< (HSMCI) Write Protection Mode Register */
#define REG_HSMCI_WPSR (0x400000E8) /**< (HSMCI) Write Protection Status Register */
#define REG_HSMCI_FIFO (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */
#define REG_HSMCI_FIFO0 (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */
#define REG_HSMCI_FIFO1 (0x40000204) /**< (HSMCI) FIFO Memory Aperture0 1 */
#define REG_HSMCI_FIFO2 (0x40000208) /**< (HSMCI) FIFO Memory Aperture0 2 */
#define REG_HSMCI_FIFO3 (0x4000020C) /**< (HSMCI) FIFO Memory Aperture0 3 */
#define REG_HSMCI_FIFO4 (0x40000210) /**< (HSMCI) FIFO Memory Aperture0 4 */
#define REG_HSMCI_FIFO5 (0x40000214) /**< (HSMCI) FIFO Memory Aperture0 5 */
#define REG_HSMCI_FIFO6 (0x40000218) /**< (HSMCI) FIFO Memory Aperture0 6 */
#define REG_HSMCI_FIFO7 (0x4000021C) /**< (HSMCI) FIFO Memory Aperture0 7 */
#define REG_HSMCI_FIFO8 (0x40000220) /**< (HSMCI) FIFO Memory Aperture0 8 */
#define REG_HSMCI_FIFO9 (0x40000224) /**< (HSMCI) FIFO Memory Aperture0 9 */
#define REG_HSMCI_FIFO10 (0x40000228) /**< (HSMCI) FIFO Memory Aperture0 10 */
#define REG_HSMCI_FIFO11 (0x4000022C) /**< (HSMCI) FIFO Memory Aperture0 11 */
#define REG_HSMCI_FIFO12 (0x40000230) /**< (HSMCI) FIFO Memory Aperture0 12 */
#define REG_HSMCI_FIFO13 (0x40000234) /**< (HSMCI) FIFO Memory Aperture0 13 */
#define REG_HSMCI_FIFO14 (0x40000238) /**< (HSMCI) FIFO Memory Aperture0 14 */
#define REG_HSMCI_FIFO15 (0x4000023C) /**< (HSMCI) FIFO Memory Aperture0 15 */
#define REG_HSMCI_FIFO16 (0x40000240) /**< (HSMCI) FIFO Memory Aperture0 16 */
#define REG_HSMCI_FIFO17 (0x40000244) /**< (HSMCI) FIFO Memory Aperture0 17 */
#define REG_HSMCI_FIFO18 (0x40000248) /**< (HSMCI) FIFO Memory Aperture0 18 */
#define REG_HSMCI_FIFO19 (0x4000024C) /**< (HSMCI) FIFO Memory Aperture0 19 */
#define REG_HSMCI_FIFO20 (0x40000250) /**< (HSMCI) FIFO Memory Aperture0 20 */
#define REG_HSMCI_FIFO21 (0x40000254) /**< (HSMCI) FIFO Memory Aperture0 21 */
#define REG_HSMCI_FIFO22 (0x40000258) /**< (HSMCI) FIFO Memory Aperture0 22 */
#define REG_HSMCI_FIFO23 (0x4000025C) /**< (HSMCI) FIFO Memory Aperture0 23 */
#define REG_HSMCI_FIFO24 (0x40000260) /**< (HSMCI) FIFO Memory Aperture0 24 */
#define REG_HSMCI_FIFO25 (0x40000264) /**< (HSMCI) FIFO Memory Aperture0 25 */
#define REG_HSMCI_FIFO26 (0x40000268) /**< (HSMCI) FIFO Memory Aperture0 26 */
#define REG_HSMCI_FIFO27 (0x4000026C) /**< (HSMCI) FIFO Memory Aperture0 27 */
#define REG_HSMCI_FIFO28 (0x40000270) /**< (HSMCI) FIFO Memory Aperture0 28 */
#define REG_HSMCI_FIFO29 (0x40000274) /**< (HSMCI) FIFO Memory Aperture0 29 */
#define REG_HSMCI_FIFO30 (0x40000278) /**< (HSMCI) FIFO Memory Aperture0 30 */
#define REG_HSMCI_FIFO31 (0x4000027C) /**< (HSMCI) FIFO Memory Aperture0 31 */
#define REG_HSMCI_FIFO32 (0x40000280) /**< (HSMCI) FIFO Memory Aperture0 32 */
#define REG_HSMCI_FIFO33 (0x40000284) /**< (HSMCI) FIFO Memory Aperture0 33 */
#define REG_HSMCI_FIFO34 (0x40000288) /**< (HSMCI) FIFO Memory Aperture0 34 */
#define REG_HSMCI_FIFO35 (0x4000028C) /**< (HSMCI) FIFO Memory Aperture0 35 */
#define REG_HSMCI_FIFO36 (0x40000290) /**< (HSMCI) FIFO Memory Aperture0 36 */
#define REG_HSMCI_FIFO37 (0x40000294) /**< (HSMCI) FIFO Memory Aperture0 37 */
#define REG_HSMCI_FIFO38 (0x40000298) /**< (HSMCI) FIFO Memory Aperture0 38 */
#define REG_HSMCI_FIFO39 (0x4000029C) /**< (HSMCI) FIFO Memory Aperture0 39 */
#define REG_HSMCI_FIFO40 (0x400002A0) /**< (HSMCI) FIFO Memory Aperture0 40 */
#define REG_HSMCI_FIFO41 (0x400002A4) /**< (HSMCI) FIFO Memory Aperture0 41 */
#define REG_HSMCI_FIFO42 (0x400002A8) /**< (HSMCI) FIFO Memory Aperture0 42 */
#define REG_HSMCI_FIFO43 (0x400002AC) /**< (HSMCI) FIFO Memory Aperture0 43 */
#define REG_HSMCI_FIFO44 (0x400002B0) /**< (HSMCI) FIFO Memory Aperture0 44 */
#define REG_HSMCI_FIFO45 (0x400002B4) /**< (HSMCI) FIFO Memory Aperture0 45 */
#define REG_HSMCI_FIFO46 (0x400002B8) /**< (HSMCI) FIFO Memory Aperture0 46 */
#define REG_HSMCI_FIFO47 (0x400002BC) /**< (HSMCI) FIFO Memory Aperture0 47 */
#define REG_HSMCI_FIFO48 (0x400002C0) /**< (HSMCI) FIFO Memory Aperture0 48 */
#define REG_HSMCI_FIFO49 (0x400002C4) /**< (HSMCI) FIFO Memory Aperture0 49 */
#define REG_HSMCI_FIFO50 (0x400002C8) /**< (HSMCI) FIFO Memory Aperture0 50 */
#define REG_HSMCI_FIFO51 (0x400002CC) /**< (HSMCI) FIFO Memory Aperture0 51 */
#define REG_HSMCI_FIFO52 (0x400002D0) /**< (HSMCI) FIFO Memory Aperture0 52 */
#define REG_HSMCI_FIFO53 (0x400002D4) /**< (HSMCI) FIFO Memory Aperture0 53 */
#define REG_HSMCI_FIFO54 (0x400002D8) /**< (HSMCI) FIFO Memory Aperture0 54 */
#define REG_HSMCI_FIFO55 (0x400002DC) /**< (HSMCI) FIFO Memory Aperture0 55 */
#define REG_HSMCI_FIFO56 (0x400002E0) /**< (HSMCI) FIFO Memory Aperture0 56 */
#define REG_HSMCI_FIFO57 (0x400002E4) /**< (HSMCI) FIFO Memory Aperture0 57 */
#define REG_HSMCI_FIFO58 (0x400002E8) /**< (HSMCI) FIFO Memory Aperture0 58 */
#define REG_HSMCI_FIFO59 (0x400002EC) /**< (HSMCI) FIFO Memory Aperture0 59 */
#define REG_HSMCI_FIFO60 (0x400002F0) /**< (HSMCI) FIFO Memory Aperture0 60 */
#define REG_HSMCI_FIFO61 (0x400002F4) /**< (HSMCI) FIFO Memory Aperture0 61 */
#define REG_HSMCI_FIFO62 (0x400002F8) /**< (HSMCI) FIFO Memory Aperture0 62 */
#define REG_HSMCI_FIFO63 (0x400002FC) /**< (HSMCI) FIFO Memory Aperture0 63 */
#define REG_HSMCI_FIFO64 (0x40000300) /**< (HSMCI) FIFO Memory Aperture0 64 */
#define REG_HSMCI_FIFO65 (0x40000304) /**< (HSMCI) FIFO Memory Aperture0 65 */
#define REG_HSMCI_FIFO66 (0x40000308) /**< (HSMCI) FIFO Memory Aperture0 66 */
#define REG_HSMCI_FIFO67 (0x4000030C) /**< (HSMCI) FIFO Memory Aperture0 67 */
#define REG_HSMCI_FIFO68 (0x40000310) /**< (HSMCI) FIFO Memory Aperture0 68 */
#define REG_HSMCI_FIFO69 (0x40000314) /**< (HSMCI) FIFO Memory Aperture0 69 */
#define REG_HSMCI_FIFO70 (0x40000318) /**< (HSMCI) FIFO Memory Aperture0 70 */
#define REG_HSMCI_FIFO71 (0x4000031C) /**< (HSMCI) FIFO Memory Aperture0 71 */
#define REG_HSMCI_FIFO72 (0x40000320) /**< (HSMCI) FIFO Memory Aperture0 72 */
#define REG_HSMCI_FIFO73 (0x40000324) /**< (HSMCI) FIFO Memory Aperture0 73 */
#define REG_HSMCI_FIFO74 (0x40000328) /**< (HSMCI) FIFO Memory Aperture0 74 */
#define REG_HSMCI_FIFO75 (0x4000032C) /**< (HSMCI) FIFO Memory Aperture0 75 */
#define REG_HSMCI_FIFO76 (0x40000330) /**< (HSMCI) FIFO Memory Aperture0 76 */
#define REG_HSMCI_FIFO77 (0x40000334) /**< (HSMCI) FIFO Memory Aperture0 77 */
#define REG_HSMCI_FIFO78 (0x40000338) /**< (HSMCI) FIFO Memory Aperture0 78 */
#define REG_HSMCI_FIFO79 (0x4000033C) /**< (HSMCI) FIFO Memory Aperture0 79 */
#define REG_HSMCI_FIFO80 (0x40000340) /**< (HSMCI) FIFO Memory Aperture0 80 */
#define REG_HSMCI_FIFO81 (0x40000344) /**< (HSMCI) FIFO Memory Aperture0 81 */
#define REG_HSMCI_FIFO82 (0x40000348) /**< (HSMCI) FIFO Memory Aperture0 82 */
#define REG_HSMCI_FIFO83 (0x4000034C) /**< (HSMCI) FIFO Memory Aperture0 83 */
#define REG_HSMCI_FIFO84 (0x40000350) /**< (HSMCI) FIFO Memory Aperture0 84 */
#define REG_HSMCI_FIFO85 (0x40000354) /**< (HSMCI) FIFO Memory Aperture0 85 */
#define REG_HSMCI_FIFO86 (0x40000358) /**< (HSMCI) FIFO Memory Aperture0 86 */
#define REG_HSMCI_FIFO87 (0x4000035C) /**< (HSMCI) FIFO Memory Aperture0 87 */
#define REG_HSMCI_FIFO88 (0x40000360) /**< (HSMCI) FIFO Memory Aperture0 88 */
#define REG_HSMCI_FIFO89 (0x40000364) /**< (HSMCI) FIFO Memory Aperture0 89 */
#define REG_HSMCI_FIFO90 (0x40000368) /**< (HSMCI) FIFO Memory Aperture0 90 */
#define REG_HSMCI_FIFO91 (0x4000036C) /**< (HSMCI) FIFO Memory Aperture0 91 */
#define REG_HSMCI_FIFO92 (0x40000370) /**< (HSMCI) FIFO Memory Aperture0 92 */
#define REG_HSMCI_FIFO93 (0x40000374) /**< (HSMCI) FIFO Memory Aperture0 93 */
#define REG_HSMCI_FIFO94 (0x40000378) /**< (HSMCI) FIFO Memory Aperture0 94 */
#define REG_HSMCI_FIFO95 (0x4000037C) /**< (HSMCI) FIFO Memory Aperture0 95 */
#define REG_HSMCI_FIFO96 (0x40000380) /**< (HSMCI) FIFO Memory Aperture0 96 */
#define REG_HSMCI_FIFO97 (0x40000384) /**< (HSMCI) FIFO Memory Aperture0 97 */
#define REG_HSMCI_FIFO98 (0x40000388) /**< (HSMCI) FIFO Memory Aperture0 98 */
#define REG_HSMCI_FIFO99 (0x4000038C) /**< (HSMCI) FIFO Memory Aperture0 99 */
#define REG_HSMCI_FIFO100 (0x40000390) /**< (HSMCI) FIFO Memory Aperture0 100 */
#define REG_HSMCI_FIFO101 (0x40000394) /**< (HSMCI) FIFO Memory Aperture0 101 */
#define REG_HSMCI_FIFO102 (0x40000398) /**< (HSMCI) FIFO Memory Aperture0 102 */
#define REG_HSMCI_FIFO103 (0x4000039C) /**< (HSMCI) FIFO Memory Aperture0 103 */
#define REG_HSMCI_FIFO104 (0x400003A0) /**< (HSMCI) FIFO Memory Aperture0 104 */
#define REG_HSMCI_FIFO105 (0x400003A4) /**< (HSMCI) FIFO Memory Aperture0 105 */
#define REG_HSMCI_FIFO106 (0x400003A8) /**< (HSMCI) FIFO Memory Aperture0 106 */
#define REG_HSMCI_FIFO107 (0x400003AC) /**< (HSMCI) FIFO Memory Aperture0 107 */
#define REG_HSMCI_FIFO108 (0x400003B0) /**< (HSMCI) FIFO Memory Aperture0 108 */
#define REG_HSMCI_FIFO109 (0x400003B4) /**< (HSMCI) FIFO Memory Aperture0 109 */
#define REG_HSMCI_FIFO110 (0x400003B8) /**< (HSMCI) FIFO Memory Aperture0 110 */
#define REG_HSMCI_FIFO111 (0x400003BC) /**< (HSMCI) FIFO Memory Aperture0 111 */
#define REG_HSMCI_FIFO112 (0x400003C0) /**< (HSMCI) FIFO Memory Aperture0 112 */
#define REG_HSMCI_FIFO113 (0x400003C4) /**< (HSMCI) FIFO Memory Aperture0 113 */
#define REG_HSMCI_FIFO114 (0x400003C8) /**< (HSMCI) FIFO Memory Aperture0 114 */
#define REG_HSMCI_FIFO115 (0x400003CC) /**< (HSMCI) FIFO Memory Aperture0 115 */
#define REG_HSMCI_FIFO116 (0x400003D0) /**< (HSMCI) FIFO Memory Aperture0 116 */
#define REG_HSMCI_FIFO117 (0x400003D4) /**< (HSMCI) FIFO Memory Aperture0 117 */
#define REG_HSMCI_FIFO118 (0x400003D8) /**< (HSMCI) FIFO Memory Aperture0 118 */
#define REG_HSMCI_FIFO119 (0x400003DC) /**< (HSMCI) FIFO Memory Aperture0 119 */
#define REG_HSMCI_FIFO120 (0x400003E0) /**< (HSMCI) FIFO Memory Aperture0 120 */
#define REG_HSMCI_FIFO121 (0x400003E4) /**< (HSMCI) FIFO Memory Aperture0 121 */
#define REG_HSMCI_FIFO122 (0x400003E8) /**< (HSMCI) FIFO Memory Aperture0 122 */
#define REG_HSMCI_FIFO123 (0x400003EC) /**< (HSMCI) FIFO Memory Aperture0 123 */
#define REG_HSMCI_FIFO124 (0x400003F0) /**< (HSMCI) FIFO Memory Aperture0 124 */
#define REG_HSMCI_FIFO125 (0x400003F4) /**< (HSMCI) FIFO Memory Aperture0 125 */
#define REG_HSMCI_FIFO126 (0x400003F8) /**< (HSMCI) FIFO Memory Aperture0 126 */
#define REG_HSMCI_FIFO127 (0x400003FC) /**< (HSMCI) FIFO Memory Aperture0 127 */
#define REG_HSMCI_FIFO128 (0x40000400) /**< (HSMCI) FIFO Memory Aperture0 128 */
#define REG_HSMCI_FIFO129 (0x40000404) /**< (HSMCI) FIFO Memory Aperture0 129 */
#define REG_HSMCI_FIFO130 (0x40000408) /**< (HSMCI) FIFO Memory Aperture0 130 */
#define REG_HSMCI_FIFO131 (0x4000040C) /**< (HSMCI) FIFO Memory Aperture0 131 */
#define REG_HSMCI_FIFO132 (0x40000410) /**< (HSMCI) FIFO Memory Aperture0 132 */
#define REG_HSMCI_FIFO133 (0x40000414) /**< (HSMCI) FIFO Memory Aperture0 133 */
#define REG_HSMCI_FIFO134 (0x40000418) /**< (HSMCI) FIFO Memory Aperture0 134 */
#define REG_HSMCI_FIFO135 (0x4000041C) /**< (HSMCI) FIFO Memory Aperture0 135 */
#define REG_HSMCI_FIFO136 (0x40000420) /**< (HSMCI) FIFO Memory Aperture0 136 */
#define REG_HSMCI_FIFO137 (0x40000424) /**< (HSMCI) FIFO Memory Aperture0 137 */
#define REG_HSMCI_FIFO138 (0x40000428) /**< (HSMCI) FIFO Memory Aperture0 138 */
#define REG_HSMCI_FIFO139 (0x4000042C) /**< (HSMCI) FIFO Memory Aperture0 139 */
#define REG_HSMCI_FIFO140 (0x40000430) /**< (HSMCI) FIFO Memory Aperture0 140 */
#define REG_HSMCI_FIFO141 (0x40000434) /**< (HSMCI) FIFO Memory Aperture0 141 */
#define REG_HSMCI_FIFO142 (0x40000438) /**< (HSMCI) FIFO Memory Aperture0 142 */
#define REG_HSMCI_FIFO143 (0x4000043C) /**< (HSMCI) FIFO Memory Aperture0 143 */
#define REG_HSMCI_FIFO144 (0x40000440) /**< (HSMCI) FIFO Memory Aperture0 144 */
#define REG_HSMCI_FIFO145 (0x40000444) /**< (HSMCI) FIFO Memory Aperture0 145 */
#define REG_HSMCI_FIFO146 (0x40000448) /**< (HSMCI) FIFO Memory Aperture0 146 */
#define REG_HSMCI_FIFO147 (0x4000044C) /**< (HSMCI) FIFO Memory Aperture0 147 */
#define REG_HSMCI_FIFO148 (0x40000450) /**< (HSMCI) FIFO Memory Aperture0 148 */
#define REG_HSMCI_FIFO149 (0x40000454) /**< (HSMCI) FIFO Memory Aperture0 149 */
#define REG_HSMCI_FIFO150 (0x40000458) /**< (HSMCI) FIFO Memory Aperture0 150 */
#define REG_HSMCI_FIFO151 (0x4000045C) /**< (HSMCI) FIFO Memory Aperture0 151 */
#define REG_HSMCI_FIFO152 (0x40000460) /**< (HSMCI) FIFO Memory Aperture0 152 */
#define REG_HSMCI_FIFO153 (0x40000464) /**< (HSMCI) FIFO Memory Aperture0 153 */
#define REG_HSMCI_FIFO154 (0x40000468) /**< (HSMCI) FIFO Memory Aperture0 154 */
#define REG_HSMCI_FIFO155 (0x4000046C) /**< (HSMCI) FIFO Memory Aperture0 155 */
#define REG_HSMCI_FIFO156 (0x40000470) /**< (HSMCI) FIFO Memory Aperture0 156 */
#define REG_HSMCI_FIFO157 (0x40000474) /**< (HSMCI) FIFO Memory Aperture0 157 */
#define REG_HSMCI_FIFO158 (0x40000478) /**< (HSMCI) FIFO Memory Aperture0 158 */
#define REG_HSMCI_FIFO159 (0x4000047C) /**< (HSMCI) FIFO Memory Aperture0 159 */
#define REG_HSMCI_FIFO160 (0x40000480) /**< (HSMCI) FIFO Memory Aperture0 160 */
#define REG_HSMCI_FIFO161 (0x40000484) /**< (HSMCI) FIFO Memory Aperture0 161 */
#define REG_HSMCI_FIFO162 (0x40000488) /**< (HSMCI) FIFO Memory Aperture0 162 */
#define REG_HSMCI_FIFO163 (0x4000048C) /**< (HSMCI) FIFO Memory Aperture0 163 */
#define REG_HSMCI_FIFO164 (0x40000490) /**< (HSMCI) FIFO Memory Aperture0 164 */
#define REG_HSMCI_FIFO165 (0x40000494) /**< (HSMCI) FIFO Memory Aperture0 165 */
#define REG_HSMCI_FIFO166 (0x40000498) /**< (HSMCI) FIFO Memory Aperture0 166 */
#define REG_HSMCI_FIFO167 (0x4000049C) /**< (HSMCI) FIFO Memory Aperture0 167 */
#define REG_HSMCI_FIFO168 (0x400004A0) /**< (HSMCI) FIFO Memory Aperture0 168 */
#define REG_HSMCI_FIFO169 (0x400004A4) /**< (HSMCI) FIFO Memory Aperture0 169 */
#define REG_HSMCI_FIFO170 (0x400004A8) /**< (HSMCI) FIFO Memory Aperture0 170 */
#define REG_HSMCI_FIFO171 (0x400004AC) /**< (HSMCI) FIFO Memory Aperture0 171 */
#define REG_HSMCI_FIFO172 (0x400004B0) /**< (HSMCI) FIFO Memory Aperture0 172 */
#define REG_HSMCI_FIFO173 (0x400004B4) /**< (HSMCI) FIFO Memory Aperture0 173 */
#define REG_HSMCI_FIFO174 (0x400004B8) /**< (HSMCI) FIFO Memory Aperture0 174 */
#define REG_HSMCI_FIFO175 (0x400004BC) /**< (HSMCI) FIFO Memory Aperture0 175 */
#define REG_HSMCI_FIFO176 (0x400004C0) /**< (HSMCI) FIFO Memory Aperture0 176 */
#define REG_HSMCI_FIFO177 (0x400004C4) /**< (HSMCI) FIFO Memory Aperture0 177 */
#define REG_HSMCI_FIFO178 (0x400004C8) /**< (HSMCI) FIFO Memory Aperture0 178 */
#define REG_HSMCI_FIFO179 (0x400004CC) /**< (HSMCI) FIFO Memory Aperture0 179 */
#define REG_HSMCI_FIFO180 (0x400004D0) /**< (HSMCI) FIFO Memory Aperture0 180 */
#define REG_HSMCI_FIFO181 (0x400004D4) /**< (HSMCI) FIFO Memory Aperture0 181 */
#define REG_HSMCI_FIFO182 (0x400004D8) /**< (HSMCI) FIFO Memory Aperture0 182 */
#define REG_HSMCI_FIFO183 (0x400004DC) /**< (HSMCI) FIFO Memory Aperture0 183 */
#define REG_HSMCI_FIFO184 (0x400004E0) /**< (HSMCI) FIFO Memory Aperture0 184 */
#define REG_HSMCI_FIFO185 (0x400004E4) /**< (HSMCI) FIFO Memory Aperture0 185 */
#define REG_HSMCI_FIFO186 (0x400004E8) /**< (HSMCI) FIFO Memory Aperture0 186 */
#define REG_HSMCI_FIFO187 (0x400004EC) /**< (HSMCI) FIFO Memory Aperture0 187 */
#define REG_HSMCI_FIFO188 (0x400004F0) /**< (HSMCI) FIFO Memory Aperture0 188 */
#define REG_HSMCI_FIFO189 (0x400004F4) /**< (HSMCI) FIFO Memory Aperture0 189 */
#define REG_HSMCI_FIFO190 (0x400004F8) /**< (HSMCI) FIFO Memory Aperture0 190 */
#define REG_HSMCI_FIFO191 (0x400004FC) /**< (HSMCI) FIFO Memory Aperture0 191 */
#define REG_HSMCI_FIFO192 (0x40000500) /**< (HSMCI) FIFO Memory Aperture0 192 */
#define REG_HSMCI_FIFO193 (0x40000504) /**< (HSMCI) FIFO Memory Aperture0 193 */
#define REG_HSMCI_FIFO194 (0x40000508) /**< (HSMCI) FIFO Memory Aperture0 194 */
#define REG_HSMCI_FIFO195 (0x4000050C) /**< (HSMCI) FIFO Memory Aperture0 195 */
#define REG_HSMCI_FIFO196 (0x40000510) /**< (HSMCI) FIFO Memory Aperture0 196 */
#define REG_HSMCI_FIFO197 (0x40000514) /**< (HSMCI) FIFO Memory Aperture0 197 */
#define REG_HSMCI_FIFO198 (0x40000518) /**< (HSMCI) FIFO Memory Aperture0 198 */
#define REG_HSMCI_FIFO199 (0x4000051C) /**< (HSMCI) FIFO Memory Aperture0 199 */
#define REG_HSMCI_FIFO200 (0x40000520) /**< (HSMCI) FIFO Memory Aperture0 200 */
#define REG_HSMCI_FIFO201 (0x40000524) /**< (HSMCI) FIFO Memory Aperture0 201 */
#define REG_HSMCI_FIFO202 (0x40000528) /**< (HSMCI) FIFO Memory Aperture0 202 */
#define REG_HSMCI_FIFO203 (0x4000052C) /**< (HSMCI) FIFO Memory Aperture0 203 */
#define REG_HSMCI_FIFO204 (0x40000530) /**< (HSMCI) FIFO Memory Aperture0 204 */
#define REG_HSMCI_FIFO205 (0x40000534) /**< (HSMCI) FIFO Memory Aperture0 205 */
#define REG_HSMCI_FIFO206 (0x40000538) /**< (HSMCI) FIFO Memory Aperture0 206 */
#define REG_HSMCI_FIFO207 (0x4000053C) /**< (HSMCI) FIFO Memory Aperture0 207 */
#define REG_HSMCI_FIFO208 (0x40000540) /**< (HSMCI) FIFO Memory Aperture0 208 */
#define REG_HSMCI_FIFO209 (0x40000544) /**< (HSMCI) FIFO Memory Aperture0 209 */
#define REG_HSMCI_FIFO210 (0x40000548) /**< (HSMCI) FIFO Memory Aperture0 210 */
#define REG_HSMCI_FIFO211 (0x4000054C) /**< (HSMCI) FIFO Memory Aperture0 211 */
#define REG_HSMCI_FIFO212 (0x40000550) /**< (HSMCI) FIFO Memory Aperture0 212 */
#define REG_HSMCI_FIFO213 (0x40000554) /**< (HSMCI) FIFO Memory Aperture0 213 */
#define REG_HSMCI_FIFO214 (0x40000558) /**< (HSMCI) FIFO Memory Aperture0 214 */
#define REG_HSMCI_FIFO215 (0x4000055C) /**< (HSMCI) FIFO Memory Aperture0 215 */
#define REG_HSMCI_FIFO216 (0x40000560) /**< (HSMCI) FIFO Memory Aperture0 216 */
#define REG_HSMCI_FIFO217 (0x40000564) /**< (HSMCI) FIFO Memory Aperture0 217 */
#define REG_HSMCI_FIFO218 (0x40000568) /**< (HSMCI) FIFO Memory Aperture0 218 */
#define REG_HSMCI_FIFO219 (0x4000056C) /**< (HSMCI) FIFO Memory Aperture0 219 */
#define REG_HSMCI_FIFO220 (0x40000570) /**< (HSMCI) FIFO Memory Aperture0 220 */
#define REG_HSMCI_FIFO221 (0x40000574) /**< (HSMCI) FIFO Memory Aperture0 221 */
#define REG_HSMCI_FIFO222 (0x40000578) /**< (HSMCI) FIFO Memory Aperture0 222 */
#define REG_HSMCI_FIFO223 (0x4000057C) /**< (HSMCI) FIFO Memory Aperture0 223 */
#define REG_HSMCI_FIFO224 (0x40000580) /**< (HSMCI) FIFO Memory Aperture0 224 */
#define REG_HSMCI_FIFO225 (0x40000584) /**< (HSMCI) FIFO Memory Aperture0 225 */
#define REG_HSMCI_FIFO226 (0x40000588) /**< (HSMCI) FIFO Memory Aperture0 226 */
#define REG_HSMCI_FIFO227 (0x4000058C) /**< (HSMCI) FIFO Memory Aperture0 227 */
#define REG_HSMCI_FIFO228 (0x40000590) /**< (HSMCI) FIFO Memory Aperture0 228 */
#define REG_HSMCI_FIFO229 (0x40000594) /**< (HSMCI) FIFO Memory Aperture0 229 */
#define REG_HSMCI_FIFO230 (0x40000598) /**< (HSMCI) FIFO Memory Aperture0 230 */
#define REG_HSMCI_FIFO231 (0x4000059C) /**< (HSMCI) FIFO Memory Aperture0 231 */
#define REG_HSMCI_FIFO232 (0x400005A0) /**< (HSMCI) FIFO Memory Aperture0 232 */
#define REG_HSMCI_FIFO233 (0x400005A4) /**< (HSMCI) FIFO Memory Aperture0 233 */
#define REG_HSMCI_FIFO234 (0x400005A8) /**< (HSMCI) FIFO Memory Aperture0 234 */
#define REG_HSMCI_FIFO235 (0x400005AC) /**< (HSMCI) FIFO Memory Aperture0 235 */
#define REG_HSMCI_FIFO236 (0x400005B0) /**< (HSMCI) FIFO Memory Aperture0 236 */
#define REG_HSMCI_FIFO237 (0x400005B4) /**< (HSMCI) FIFO Memory Aperture0 237 */
#define REG_HSMCI_FIFO238 (0x400005B8) /**< (HSMCI) FIFO Memory Aperture0 238 */
#define REG_HSMCI_FIFO239 (0x400005BC) /**< (HSMCI) FIFO Memory Aperture0 239 */
#define REG_HSMCI_FIFO240 (0x400005C0) /**< (HSMCI) FIFO Memory Aperture0 240 */
#define REG_HSMCI_FIFO241 (0x400005C4) /**< (HSMCI) FIFO Memory Aperture0 241 */
#define REG_HSMCI_FIFO242 (0x400005C8) /**< (HSMCI) FIFO Memory Aperture0 242 */
#define REG_HSMCI_FIFO243 (0x400005CC) /**< (HSMCI) FIFO Memory Aperture0 243 */
#define REG_HSMCI_FIFO244 (0x400005D0) /**< (HSMCI) FIFO Memory Aperture0 244 */
#define REG_HSMCI_FIFO245 (0x400005D4) /**< (HSMCI) FIFO Memory Aperture0 245 */
#define REG_HSMCI_FIFO246 (0x400005D8) /**< (HSMCI) FIFO Memory Aperture0 246 */
#define REG_HSMCI_FIFO247 (0x400005DC) /**< (HSMCI) FIFO Memory Aperture0 247 */
#define REG_HSMCI_FIFO248 (0x400005E0) /**< (HSMCI) FIFO Memory Aperture0 248 */
#define REG_HSMCI_FIFO249 (0x400005E4) /**< (HSMCI) FIFO Memory Aperture0 249 */
#define REG_HSMCI_FIFO250 (0x400005E8) /**< (HSMCI) FIFO Memory Aperture0 250 */
#define REG_HSMCI_FIFO251 (0x400005EC) /**< (HSMCI) FIFO Memory Aperture0 251 */
#define REG_HSMCI_FIFO252 (0x400005F0) /**< (HSMCI) FIFO Memory Aperture0 252 */
#define REG_HSMCI_FIFO253 (0x400005F4) /**< (HSMCI) FIFO Memory Aperture0 253 */
#define REG_HSMCI_FIFO254 (0x400005F8) /**< (HSMCI) FIFO Memory Aperture0 254 */
#define REG_HSMCI_FIFO255 (0x400005FC) /**< (HSMCI) FIFO Memory Aperture0 255 */
#else
#define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< (HSMCI) Control Register */
#define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< (HSMCI) Mode Register */
#define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< (HSMCI) Data Timeout Register */
#define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< (HSMCI) SD/SDIO Card Register */
#define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< (HSMCI) Argument Register */
#define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< (HSMCI) Command Register */
#define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< (HSMCI) Block Register */
#define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< (HSMCI) Completion Signal Timeout Register */
#define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */
#define REG_HSMCI_RSPR0 (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */
#define REG_HSMCI_RSPR1 (*(__I uint32_t*)0x40000024U) /**< (HSMCI) Response Register 1 */
#define REG_HSMCI_RSPR2 (*(__I uint32_t*)0x40000028U) /**< (HSMCI) Response Register 2 */
#define REG_HSMCI_RSPR3 (*(__I uint32_t*)0x4000002CU) /**< (HSMCI) Response Register 3 */
#define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< (HSMCI) Receive Data Register */
#define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< (HSMCI) Transmit Data Register */
#define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< (HSMCI) Status Register */
#define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< (HSMCI) Interrupt Enable Register */
#define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< (HSMCI) Interrupt Disable Register */
#define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< (HSMCI) Interrupt Mask Register */
#define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< (HSMCI) DMA Configuration Register */
#define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< (HSMCI) Configuration Register */
#define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< (HSMCI) Write Protection Mode Register */
#define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< (HSMCI) Write Protection Status Register */
#define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */
#define REG_HSMCI_FIFO0 (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */
#define REG_HSMCI_FIFO1 (*(__IO uint32_t*)0x40000204U) /**< (HSMCI) FIFO Memory Aperture0 1 */
#define REG_HSMCI_FIFO2 (*(__IO uint32_t*)0x40000208U) /**< (HSMCI) FIFO Memory Aperture0 2 */
#define REG_HSMCI_FIFO3 (*(__IO uint32_t*)0x4000020CU) /**< (HSMCI) FIFO Memory Aperture0 3 */
#define REG_HSMCI_FIFO4 (*(__IO uint32_t*)0x40000210U) /**< (HSMCI) FIFO Memory Aperture0 4 */
#define REG_HSMCI_FIFO5 (*(__IO uint32_t*)0x40000214U) /**< (HSMCI) FIFO Memory Aperture0 5 */
#define REG_HSMCI_FIFO6 (*(__IO uint32_t*)0x40000218U) /**< (HSMCI) FIFO Memory Aperture0 6 */
#define REG_HSMCI_FIFO7 (*(__IO uint32_t*)0x4000021CU) /**< (HSMCI) FIFO Memory Aperture0 7 */
#define REG_HSMCI_FIFO8 (*(__IO uint32_t*)0x40000220U) /**< (HSMCI) FIFO Memory Aperture0 8 */
#define REG_HSMCI_FIFO9 (*(__IO uint32_t*)0x40000224U) /**< (HSMCI) FIFO Memory Aperture0 9 */
#define REG_HSMCI_FIFO10 (*(__IO uint32_t*)0x40000228U) /**< (HSMCI) FIFO Memory Aperture0 10 */
#define REG_HSMCI_FIFO11 (*(__IO uint32_t*)0x4000022CU) /**< (HSMCI) FIFO Memory Aperture0 11 */
#define REG_HSMCI_FIFO12 (*(__IO uint32_t*)0x40000230U) /**< (HSMCI) FIFO Memory Aperture0 12 */
#define REG_HSMCI_FIFO13 (*(__IO uint32_t*)0x40000234U) /**< (HSMCI) FIFO Memory Aperture0 13 */
#define REG_HSMCI_FIFO14 (*(__IO uint32_t*)0x40000238U) /**< (HSMCI) FIFO Memory Aperture0 14 */
#define REG_HSMCI_FIFO15 (*(__IO uint32_t*)0x4000023CU) /**< (HSMCI) FIFO Memory Aperture0 15 */
#define REG_HSMCI_FIFO16 (*(__IO uint32_t*)0x40000240U) /**< (HSMCI) FIFO Memory Aperture0 16 */
#define REG_HSMCI_FIFO17 (*(__IO uint32_t*)0x40000244U) /**< (HSMCI) FIFO Memory Aperture0 17 */
#define REG_HSMCI_FIFO18 (*(__IO uint32_t*)0x40000248U) /**< (HSMCI) FIFO Memory Aperture0 18 */
#define REG_HSMCI_FIFO19 (*(__IO uint32_t*)0x4000024CU) /**< (HSMCI) FIFO Memory Aperture0 19 */
#define REG_HSMCI_FIFO20 (*(__IO uint32_t*)0x40000250U) /**< (HSMCI) FIFO Memory Aperture0 20 */
#define REG_HSMCI_FIFO21 (*(__IO uint32_t*)0x40000254U) /**< (HSMCI) FIFO Memory Aperture0 21 */
#define REG_HSMCI_FIFO22 (*(__IO uint32_t*)0x40000258U) /**< (HSMCI) FIFO Memory Aperture0 22 */
#define REG_HSMCI_FIFO23 (*(__IO uint32_t*)0x4000025CU) /**< (HSMCI) FIFO Memory Aperture0 23 */
#define REG_HSMCI_FIFO24 (*(__IO uint32_t*)0x40000260U) /**< (HSMCI) FIFO Memory Aperture0 24 */
#define REG_HSMCI_FIFO25 (*(__IO uint32_t*)0x40000264U) /**< (HSMCI) FIFO Memory Aperture0 25 */
#define REG_HSMCI_FIFO26 (*(__IO uint32_t*)0x40000268U) /**< (HSMCI) FIFO Memory Aperture0 26 */
#define REG_HSMCI_FIFO27 (*(__IO uint32_t*)0x4000026CU) /**< (HSMCI) FIFO Memory Aperture0 27 */
#define REG_HSMCI_FIFO28 (*(__IO uint32_t*)0x40000270U) /**< (HSMCI) FIFO Memory Aperture0 28 */
#define REG_HSMCI_FIFO29 (*(__IO uint32_t*)0x40000274U) /**< (HSMCI) FIFO Memory Aperture0 29 */
#define REG_HSMCI_FIFO30 (*(__IO uint32_t*)0x40000278U) /**< (HSMCI) FIFO Memory Aperture0 30 */
#define REG_HSMCI_FIFO31 (*(__IO uint32_t*)0x4000027CU) /**< (HSMCI) FIFO Memory Aperture0 31 */
#define REG_HSMCI_FIFO32 (*(__IO uint32_t*)0x40000280U) /**< (HSMCI) FIFO Memory Aperture0 32 */
#define REG_HSMCI_FIFO33 (*(__IO uint32_t*)0x40000284U) /**< (HSMCI) FIFO Memory Aperture0 33 */
#define REG_HSMCI_FIFO34 (*(__IO uint32_t*)0x40000288U) /**< (HSMCI) FIFO Memory Aperture0 34 */
#define REG_HSMCI_FIFO35 (*(__IO uint32_t*)0x4000028CU) /**< (HSMCI) FIFO Memory Aperture0 35 */
#define REG_HSMCI_FIFO36 (*(__IO uint32_t*)0x40000290U) /**< (HSMCI) FIFO Memory Aperture0 36 */
#define REG_HSMCI_FIFO37 (*(__IO uint32_t*)0x40000294U) /**< (HSMCI) FIFO Memory Aperture0 37 */
#define REG_HSMCI_FIFO38 (*(__IO uint32_t*)0x40000298U) /**< (HSMCI) FIFO Memory Aperture0 38 */
#define REG_HSMCI_FIFO39 (*(__IO uint32_t*)0x4000029CU) /**< (HSMCI) FIFO Memory Aperture0 39 */
#define REG_HSMCI_FIFO40 (*(__IO uint32_t*)0x400002A0U) /**< (HSMCI) FIFO Memory Aperture0 40 */
#define REG_HSMCI_FIFO41 (*(__IO uint32_t*)0x400002A4U) /**< (HSMCI) FIFO Memory Aperture0 41 */
#define REG_HSMCI_FIFO42 (*(__IO uint32_t*)0x400002A8U) /**< (HSMCI) FIFO Memory Aperture0 42 */
#define REG_HSMCI_FIFO43 (*(__IO uint32_t*)0x400002ACU) /**< (HSMCI) FIFO Memory Aperture0 43 */
#define REG_HSMCI_FIFO44 (*(__IO uint32_t*)0x400002B0U) /**< (HSMCI) FIFO Memory Aperture0 44 */
#define REG_HSMCI_FIFO45 (*(__IO uint32_t*)0x400002B4U) /**< (HSMCI) FIFO Memory Aperture0 45 */
#define REG_HSMCI_FIFO46 (*(__IO uint32_t*)0x400002B8U) /**< (HSMCI) FIFO Memory Aperture0 46 */
#define REG_HSMCI_FIFO47 (*(__IO uint32_t*)0x400002BCU) /**< (HSMCI) FIFO Memory Aperture0 47 */
#define REG_HSMCI_FIFO48 (*(__IO uint32_t*)0x400002C0U) /**< (HSMCI) FIFO Memory Aperture0 48 */
#define REG_HSMCI_FIFO49 (*(__IO uint32_t*)0x400002C4U) /**< (HSMCI) FIFO Memory Aperture0 49 */
#define REG_HSMCI_FIFO50 (*(__IO uint32_t*)0x400002C8U) /**< (HSMCI) FIFO Memory Aperture0 50 */
#define REG_HSMCI_FIFO51 (*(__IO uint32_t*)0x400002CCU) /**< (HSMCI) FIFO Memory Aperture0 51 */
#define REG_HSMCI_FIFO52 (*(__IO uint32_t*)0x400002D0U) /**< (HSMCI) FIFO Memory Aperture0 52 */
#define REG_HSMCI_FIFO53 (*(__IO uint32_t*)0x400002D4U) /**< (HSMCI) FIFO Memory Aperture0 53 */
#define REG_HSMCI_FIFO54 (*(__IO uint32_t*)0x400002D8U) /**< (HSMCI) FIFO Memory Aperture0 54 */
#define REG_HSMCI_FIFO55 (*(__IO uint32_t*)0x400002DCU) /**< (HSMCI) FIFO Memory Aperture0 55 */
#define REG_HSMCI_FIFO56 (*(__IO uint32_t*)0x400002E0U) /**< (HSMCI) FIFO Memory Aperture0 56 */
#define REG_HSMCI_FIFO57 (*(__IO uint32_t*)0x400002E4U) /**< (HSMCI) FIFO Memory Aperture0 57 */
#define REG_HSMCI_FIFO58 (*(__IO uint32_t*)0x400002E8U) /**< (HSMCI) FIFO Memory Aperture0 58 */
#define REG_HSMCI_FIFO59 (*(__IO uint32_t*)0x400002ECU) /**< (HSMCI) FIFO Memory Aperture0 59 */
#define REG_HSMCI_FIFO60 (*(__IO uint32_t*)0x400002F0U) /**< (HSMCI) FIFO Memory Aperture0 60 */
#define REG_HSMCI_FIFO61 (*(__IO uint32_t*)0x400002F4U) /**< (HSMCI) FIFO Memory Aperture0 61 */
#define REG_HSMCI_FIFO62 (*(__IO uint32_t*)0x400002F8U) /**< (HSMCI) FIFO Memory Aperture0 62 */
#define REG_HSMCI_FIFO63 (*(__IO uint32_t*)0x400002FCU) /**< (HSMCI) FIFO Memory Aperture0 63 */
#define REG_HSMCI_FIFO64 (*(__IO uint32_t*)0x40000300U) /**< (HSMCI) FIFO Memory Aperture0 64 */
#define REG_HSMCI_FIFO65 (*(__IO uint32_t*)0x40000304U) /**< (HSMCI) FIFO Memory Aperture0 65 */
#define REG_HSMCI_FIFO66 (*(__IO uint32_t*)0x40000308U) /**< (HSMCI) FIFO Memory Aperture0 66 */
#define REG_HSMCI_FIFO67 (*(__IO uint32_t*)0x4000030CU) /**< (HSMCI) FIFO Memory Aperture0 67 */
#define REG_HSMCI_FIFO68 (*(__IO uint32_t*)0x40000310U) /**< (HSMCI) FIFO Memory Aperture0 68 */
#define REG_HSMCI_FIFO69 (*(__IO uint32_t*)0x40000314U) /**< (HSMCI) FIFO Memory Aperture0 69 */
#define REG_HSMCI_FIFO70 (*(__IO uint32_t*)0x40000318U) /**< (HSMCI) FIFO Memory Aperture0 70 */
#define REG_HSMCI_FIFO71 (*(__IO uint32_t*)0x4000031CU) /**< (HSMCI) FIFO Memory Aperture0 71 */
#define REG_HSMCI_FIFO72 (*(__IO uint32_t*)0x40000320U) /**< (HSMCI) FIFO Memory Aperture0 72 */
#define REG_HSMCI_FIFO73 (*(__IO uint32_t*)0x40000324U) /**< (HSMCI) FIFO Memory Aperture0 73 */
#define REG_HSMCI_FIFO74 (*(__IO uint32_t*)0x40000328U) /**< (HSMCI) FIFO Memory Aperture0 74 */
#define REG_HSMCI_FIFO75 (*(__IO uint32_t*)0x4000032CU) /**< (HSMCI) FIFO Memory Aperture0 75 */
#define REG_HSMCI_FIFO76 (*(__IO uint32_t*)0x40000330U) /**< (HSMCI) FIFO Memory Aperture0 76 */
#define REG_HSMCI_FIFO77 (*(__IO uint32_t*)0x40000334U) /**< (HSMCI) FIFO Memory Aperture0 77 */
#define REG_HSMCI_FIFO78 (*(__IO uint32_t*)0x40000338U) /**< (HSMCI) FIFO Memory Aperture0 78 */
#define REG_HSMCI_FIFO79 (*(__IO uint32_t*)0x4000033CU) /**< (HSMCI) FIFO Memory Aperture0 79 */
#define REG_HSMCI_FIFO80 (*(__IO uint32_t*)0x40000340U) /**< (HSMCI) FIFO Memory Aperture0 80 */
#define REG_HSMCI_FIFO81 (*(__IO uint32_t*)0x40000344U) /**< (HSMCI) FIFO Memory Aperture0 81 */
#define REG_HSMCI_FIFO82 (*(__IO uint32_t*)0x40000348U) /**< (HSMCI) FIFO Memory Aperture0 82 */
#define REG_HSMCI_FIFO83 (*(__IO uint32_t*)0x4000034CU) /**< (HSMCI) FIFO Memory Aperture0 83 */
#define REG_HSMCI_FIFO84 (*(__IO uint32_t*)0x40000350U) /**< (HSMCI) FIFO Memory Aperture0 84 */
#define REG_HSMCI_FIFO85 (*(__IO uint32_t*)0x40000354U) /**< (HSMCI) FIFO Memory Aperture0 85 */
#define REG_HSMCI_FIFO86 (*(__IO uint32_t*)0x40000358U) /**< (HSMCI) FIFO Memory Aperture0 86 */
#define REG_HSMCI_FIFO87 (*(__IO uint32_t*)0x4000035CU) /**< (HSMCI) FIFO Memory Aperture0 87 */
#define REG_HSMCI_FIFO88 (*(__IO uint32_t*)0x40000360U) /**< (HSMCI) FIFO Memory Aperture0 88 */
#define REG_HSMCI_FIFO89 (*(__IO uint32_t*)0x40000364U) /**< (HSMCI) FIFO Memory Aperture0 89 */
#define REG_HSMCI_FIFO90 (*(__IO uint32_t*)0x40000368U) /**< (HSMCI) FIFO Memory Aperture0 90 */
#define REG_HSMCI_FIFO91 (*(__IO uint32_t*)0x4000036CU) /**< (HSMCI) FIFO Memory Aperture0 91 */
#define REG_HSMCI_FIFO92 (*(__IO uint32_t*)0x40000370U) /**< (HSMCI) FIFO Memory Aperture0 92 */
#define REG_HSMCI_FIFO93 (*(__IO uint32_t*)0x40000374U) /**< (HSMCI) FIFO Memory Aperture0 93 */
#define REG_HSMCI_FIFO94 (*(__IO uint32_t*)0x40000378U) /**< (HSMCI) FIFO Memory Aperture0 94 */
#define REG_HSMCI_FIFO95 (*(__IO uint32_t*)0x4000037CU) /**< (HSMCI) FIFO Memory Aperture0 95 */
#define REG_HSMCI_FIFO96 (*(__IO uint32_t*)0x40000380U) /**< (HSMCI) FIFO Memory Aperture0 96 */
#define REG_HSMCI_FIFO97 (*(__IO uint32_t*)0x40000384U) /**< (HSMCI) FIFO Memory Aperture0 97 */
#define REG_HSMCI_FIFO98 (*(__IO uint32_t*)0x40000388U) /**< (HSMCI) FIFO Memory Aperture0 98 */
#define REG_HSMCI_FIFO99 (*(__IO uint32_t*)0x4000038CU) /**< (HSMCI) FIFO Memory Aperture0 99 */
#define REG_HSMCI_FIFO100 (*(__IO uint32_t*)0x40000390U) /**< (HSMCI) FIFO Memory Aperture0 100 */
#define REG_HSMCI_FIFO101 (*(__IO uint32_t*)0x40000394U) /**< (HSMCI) FIFO Memory Aperture0 101 */
#define REG_HSMCI_FIFO102 (*(__IO uint32_t*)0x40000398U) /**< (HSMCI) FIFO Memory Aperture0 102 */
#define REG_HSMCI_FIFO103 (*(__IO uint32_t*)0x4000039CU) /**< (HSMCI) FIFO Memory Aperture0 103 */
#define REG_HSMCI_FIFO104 (*(__IO uint32_t*)0x400003A0U) /**< (HSMCI) FIFO Memory Aperture0 104 */
#define REG_HSMCI_FIFO105 (*(__IO uint32_t*)0x400003A4U) /**< (HSMCI) FIFO Memory Aperture0 105 */
#define REG_HSMCI_FIFO106 (*(__IO uint32_t*)0x400003A8U) /**< (HSMCI) FIFO Memory Aperture0 106 */
#define REG_HSMCI_FIFO107 (*(__IO uint32_t*)0x400003ACU) /**< (HSMCI) FIFO Memory Aperture0 107 */
#define REG_HSMCI_FIFO108 (*(__IO uint32_t*)0x400003B0U) /**< (HSMCI) FIFO Memory Aperture0 108 */
#define REG_HSMCI_FIFO109 (*(__IO uint32_t*)0x400003B4U) /**< (HSMCI) FIFO Memory Aperture0 109 */
#define REG_HSMCI_FIFO110 (*(__IO uint32_t*)0x400003B8U) /**< (HSMCI) FIFO Memory Aperture0 110 */
#define REG_HSMCI_FIFO111 (*(__IO uint32_t*)0x400003BCU) /**< (HSMCI) FIFO Memory Aperture0 111 */
#define REG_HSMCI_FIFO112 (*(__IO uint32_t*)0x400003C0U) /**< (HSMCI) FIFO Memory Aperture0 112 */
#define REG_HSMCI_FIFO113 (*(__IO uint32_t*)0x400003C4U) /**< (HSMCI) FIFO Memory Aperture0 113 */
#define REG_HSMCI_FIFO114 (*(__IO uint32_t*)0x400003C8U) /**< (HSMCI) FIFO Memory Aperture0 114 */
#define REG_HSMCI_FIFO115 (*(__IO uint32_t*)0x400003CCU) /**< (HSMCI) FIFO Memory Aperture0 115 */
#define REG_HSMCI_FIFO116 (*(__IO uint32_t*)0x400003D0U) /**< (HSMCI) FIFO Memory Aperture0 116 */
#define REG_HSMCI_FIFO117 (*(__IO uint32_t*)0x400003D4U) /**< (HSMCI) FIFO Memory Aperture0 117 */
#define REG_HSMCI_FIFO118 (*(__IO uint32_t*)0x400003D8U) /**< (HSMCI) FIFO Memory Aperture0 118 */
#define REG_HSMCI_FIFO119 (*(__IO uint32_t*)0x400003DCU) /**< (HSMCI) FIFO Memory Aperture0 119 */
#define REG_HSMCI_FIFO120 (*(__IO uint32_t*)0x400003E0U) /**< (HSMCI) FIFO Memory Aperture0 120 */
#define REG_HSMCI_FIFO121 (*(__IO uint32_t*)0x400003E4U) /**< (HSMCI) FIFO Memory Aperture0 121 */
#define REG_HSMCI_FIFO122 (*(__IO uint32_t*)0x400003E8U) /**< (HSMCI) FIFO Memory Aperture0 122 */
#define REG_HSMCI_FIFO123 (*(__IO uint32_t*)0x400003ECU) /**< (HSMCI) FIFO Memory Aperture0 123 */
#define REG_HSMCI_FIFO124 (*(__IO uint32_t*)0x400003F0U) /**< (HSMCI) FIFO Memory Aperture0 124 */
#define REG_HSMCI_FIFO125 (*(__IO uint32_t*)0x400003F4U) /**< (HSMCI) FIFO Memory Aperture0 125 */
#define REG_HSMCI_FIFO126 (*(__IO uint32_t*)0x400003F8U) /**< (HSMCI) FIFO Memory Aperture0 126 */
#define REG_HSMCI_FIFO127 (*(__IO uint32_t*)0x400003FCU) /**< (HSMCI) FIFO Memory Aperture0 127 */
#define REG_HSMCI_FIFO128 (*(__IO uint32_t*)0x40000400U) /**< (HSMCI) FIFO Memory Aperture0 128 */
#define REG_HSMCI_FIFO129 (*(__IO uint32_t*)0x40000404U) /**< (HSMCI) FIFO Memory Aperture0 129 */
#define REG_HSMCI_FIFO130 (*(__IO uint32_t*)0x40000408U) /**< (HSMCI) FIFO Memory Aperture0 130 */
#define REG_HSMCI_FIFO131 (*(__IO uint32_t*)0x4000040CU) /**< (HSMCI) FIFO Memory Aperture0 131 */
#define REG_HSMCI_FIFO132 (*(__IO uint32_t*)0x40000410U) /**< (HSMCI) FIFO Memory Aperture0 132 */
#define REG_HSMCI_FIFO133 (*(__IO uint32_t*)0x40000414U) /**< (HSMCI) FIFO Memory Aperture0 133 */
#define REG_HSMCI_FIFO134 (*(__IO uint32_t*)0x40000418U) /**< (HSMCI) FIFO Memory Aperture0 134 */
#define REG_HSMCI_FIFO135 (*(__IO uint32_t*)0x4000041CU) /**< (HSMCI) FIFO Memory Aperture0 135 */
#define REG_HSMCI_FIFO136 (*(__IO uint32_t*)0x40000420U) /**< (HSMCI) FIFO Memory Aperture0 136 */
#define REG_HSMCI_FIFO137 (*(__IO uint32_t*)0x40000424U) /**< (HSMCI) FIFO Memory Aperture0 137 */
#define REG_HSMCI_FIFO138 (*(__IO uint32_t*)0x40000428U) /**< (HSMCI) FIFO Memory Aperture0 138 */
#define REG_HSMCI_FIFO139 (*(__IO uint32_t*)0x4000042CU) /**< (HSMCI) FIFO Memory Aperture0 139 */
#define REG_HSMCI_FIFO140 (*(__IO uint32_t*)0x40000430U) /**< (HSMCI) FIFO Memory Aperture0 140 */
#define REG_HSMCI_FIFO141 (*(__IO uint32_t*)0x40000434U) /**< (HSMCI) FIFO Memory Aperture0 141 */
#define REG_HSMCI_FIFO142 (*(__IO uint32_t*)0x40000438U) /**< (HSMCI) FIFO Memory Aperture0 142 */
#define REG_HSMCI_FIFO143 (*(__IO uint32_t*)0x4000043CU) /**< (HSMCI) FIFO Memory Aperture0 143 */
#define REG_HSMCI_FIFO144 (*(__IO uint32_t*)0x40000440U) /**< (HSMCI) FIFO Memory Aperture0 144 */
#define REG_HSMCI_FIFO145 (*(__IO uint32_t*)0x40000444U) /**< (HSMCI) FIFO Memory Aperture0 145 */
#define REG_HSMCI_FIFO146 (*(__IO uint32_t*)0x40000448U) /**< (HSMCI) FIFO Memory Aperture0 146 */
#define REG_HSMCI_FIFO147 (*(__IO uint32_t*)0x4000044CU) /**< (HSMCI) FIFO Memory Aperture0 147 */
#define REG_HSMCI_FIFO148 (*(__IO uint32_t*)0x40000450U) /**< (HSMCI) FIFO Memory Aperture0 148 */
#define REG_HSMCI_FIFO149 (*(__IO uint32_t*)0x40000454U) /**< (HSMCI) FIFO Memory Aperture0 149 */
#define REG_HSMCI_FIFO150 (*(__IO uint32_t*)0x40000458U) /**< (HSMCI) FIFO Memory Aperture0 150 */
#define REG_HSMCI_FIFO151 (*(__IO uint32_t*)0x4000045CU) /**< (HSMCI) FIFO Memory Aperture0 151 */
#define REG_HSMCI_FIFO152 (*(__IO uint32_t*)0x40000460U) /**< (HSMCI) FIFO Memory Aperture0 152 */
#define REG_HSMCI_FIFO153 (*(__IO uint32_t*)0x40000464U) /**< (HSMCI) FIFO Memory Aperture0 153 */
#define REG_HSMCI_FIFO154 (*(__IO uint32_t*)0x40000468U) /**< (HSMCI) FIFO Memory Aperture0 154 */
#define REG_HSMCI_FIFO155 (*(__IO uint32_t*)0x4000046CU) /**< (HSMCI) FIFO Memory Aperture0 155 */
#define REG_HSMCI_FIFO156 (*(__IO uint32_t*)0x40000470U) /**< (HSMCI) FIFO Memory Aperture0 156 */
#define REG_HSMCI_FIFO157 (*(__IO uint32_t*)0x40000474U) /**< (HSMCI) FIFO Memory Aperture0 157 */
#define REG_HSMCI_FIFO158 (*(__IO uint32_t*)0x40000478U) /**< (HSMCI) FIFO Memory Aperture0 158 */
#define REG_HSMCI_FIFO159 (*(__IO uint32_t*)0x4000047CU) /**< (HSMCI) FIFO Memory Aperture0 159 */
#define REG_HSMCI_FIFO160 (*(__IO uint32_t*)0x40000480U) /**< (HSMCI) FIFO Memory Aperture0 160 */
#define REG_HSMCI_FIFO161 (*(__IO uint32_t*)0x40000484U) /**< (HSMCI) FIFO Memory Aperture0 161 */
#define REG_HSMCI_FIFO162 (*(__IO uint32_t*)0x40000488U) /**< (HSMCI) FIFO Memory Aperture0 162 */
#define REG_HSMCI_FIFO163 (*(__IO uint32_t*)0x4000048CU) /**< (HSMCI) FIFO Memory Aperture0 163 */
#define REG_HSMCI_FIFO164 (*(__IO uint32_t*)0x40000490U) /**< (HSMCI) FIFO Memory Aperture0 164 */
#define REG_HSMCI_FIFO165 (*(__IO uint32_t*)0x40000494U) /**< (HSMCI) FIFO Memory Aperture0 165 */
#define REG_HSMCI_FIFO166 (*(__IO uint32_t*)0x40000498U) /**< (HSMCI) FIFO Memory Aperture0 166 */
#define REG_HSMCI_FIFO167 (*(__IO uint32_t*)0x4000049CU) /**< (HSMCI) FIFO Memory Aperture0 167 */
#define REG_HSMCI_FIFO168 (*(__IO uint32_t*)0x400004A0U) /**< (HSMCI) FIFO Memory Aperture0 168 */
#define REG_HSMCI_FIFO169 (*(__IO uint32_t*)0x400004A4U) /**< (HSMCI) FIFO Memory Aperture0 169 */
#define REG_HSMCI_FIFO170 (*(__IO uint32_t*)0x400004A8U) /**< (HSMCI) FIFO Memory Aperture0 170 */
#define REG_HSMCI_FIFO171 (*(__IO uint32_t*)0x400004ACU) /**< (HSMCI) FIFO Memory Aperture0 171 */
#define REG_HSMCI_FIFO172 (*(__IO uint32_t*)0x400004B0U) /**< (HSMCI) FIFO Memory Aperture0 172 */
#define REG_HSMCI_FIFO173 (*(__IO uint32_t*)0x400004B4U) /**< (HSMCI) FIFO Memory Aperture0 173 */
#define REG_HSMCI_FIFO174 (*(__IO uint32_t*)0x400004B8U) /**< (HSMCI) FIFO Memory Aperture0 174 */
#define REG_HSMCI_FIFO175 (*(__IO uint32_t*)0x400004BCU) /**< (HSMCI) FIFO Memory Aperture0 175 */
#define REG_HSMCI_FIFO176 (*(__IO uint32_t*)0x400004C0U) /**< (HSMCI) FIFO Memory Aperture0 176 */
#define REG_HSMCI_FIFO177 (*(__IO uint32_t*)0x400004C4U) /**< (HSMCI) FIFO Memory Aperture0 177 */
#define REG_HSMCI_FIFO178 (*(__IO uint32_t*)0x400004C8U) /**< (HSMCI) FIFO Memory Aperture0 178 */
#define REG_HSMCI_FIFO179 (*(__IO uint32_t*)0x400004CCU) /**< (HSMCI) FIFO Memory Aperture0 179 */
#define REG_HSMCI_FIFO180 (*(__IO uint32_t*)0x400004D0U) /**< (HSMCI) FIFO Memory Aperture0 180 */
#define REG_HSMCI_FIFO181 (*(__IO uint32_t*)0x400004D4U) /**< (HSMCI) FIFO Memory Aperture0 181 */
#define REG_HSMCI_FIFO182 (*(__IO uint32_t*)0x400004D8U) /**< (HSMCI) FIFO Memory Aperture0 182 */
#define REG_HSMCI_FIFO183 (*(__IO uint32_t*)0x400004DCU) /**< (HSMCI) FIFO Memory Aperture0 183 */
#define REG_HSMCI_FIFO184 (*(__IO uint32_t*)0x400004E0U) /**< (HSMCI) FIFO Memory Aperture0 184 */
#define REG_HSMCI_FIFO185 (*(__IO uint32_t*)0x400004E4U) /**< (HSMCI) FIFO Memory Aperture0 185 */
#define REG_HSMCI_FIFO186 (*(__IO uint32_t*)0x400004E8U) /**< (HSMCI) FIFO Memory Aperture0 186 */
#define REG_HSMCI_FIFO187 (*(__IO uint32_t*)0x400004ECU) /**< (HSMCI) FIFO Memory Aperture0 187 */
#define REG_HSMCI_FIFO188 (*(__IO uint32_t*)0x400004F0U) /**< (HSMCI) FIFO Memory Aperture0 188 */
#define REG_HSMCI_FIFO189 (*(__IO uint32_t*)0x400004F4U) /**< (HSMCI) FIFO Memory Aperture0 189 */
#define REG_HSMCI_FIFO190 (*(__IO uint32_t*)0x400004F8U) /**< (HSMCI) FIFO Memory Aperture0 190 */
#define REG_HSMCI_FIFO191 (*(__IO uint32_t*)0x400004FCU) /**< (HSMCI) FIFO Memory Aperture0 191 */
#define REG_HSMCI_FIFO192 (*(__IO uint32_t*)0x40000500U) /**< (HSMCI) FIFO Memory Aperture0 192 */
#define REG_HSMCI_FIFO193 (*(__IO uint32_t*)0x40000504U) /**< (HSMCI) FIFO Memory Aperture0 193 */
#define REG_HSMCI_FIFO194 (*(__IO uint32_t*)0x40000508U) /**< (HSMCI) FIFO Memory Aperture0 194 */
#define REG_HSMCI_FIFO195 (*(__IO uint32_t*)0x4000050CU) /**< (HSMCI) FIFO Memory Aperture0 195 */
#define REG_HSMCI_FIFO196 (*(__IO uint32_t*)0x40000510U) /**< (HSMCI) FIFO Memory Aperture0 196 */
#define REG_HSMCI_FIFO197 (*(__IO uint32_t*)0x40000514U) /**< (HSMCI) FIFO Memory Aperture0 197 */
#define REG_HSMCI_FIFO198 (*(__IO uint32_t*)0x40000518U) /**< (HSMCI) FIFO Memory Aperture0 198 */
#define REG_HSMCI_FIFO199 (*(__IO uint32_t*)0x4000051CU) /**< (HSMCI) FIFO Memory Aperture0 199 */
#define REG_HSMCI_FIFO200 (*(__IO uint32_t*)0x40000520U) /**< (HSMCI) FIFO Memory Aperture0 200 */
#define REG_HSMCI_FIFO201 (*(__IO uint32_t*)0x40000524U) /**< (HSMCI) FIFO Memory Aperture0 201 */
#define REG_HSMCI_FIFO202 (*(__IO uint32_t*)0x40000528U) /**< (HSMCI) FIFO Memory Aperture0 202 */
#define REG_HSMCI_FIFO203 (*(__IO uint32_t*)0x4000052CU) /**< (HSMCI) FIFO Memory Aperture0 203 */
#define REG_HSMCI_FIFO204 (*(__IO uint32_t*)0x40000530U) /**< (HSMCI) FIFO Memory Aperture0 204 */
#define REG_HSMCI_FIFO205 (*(__IO uint32_t*)0x40000534U) /**< (HSMCI) FIFO Memory Aperture0 205 */
#define REG_HSMCI_FIFO206 (*(__IO uint32_t*)0x40000538U) /**< (HSMCI) FIFO Memory Aperture0 206 */
#define REG_HSMCI_FIFO207 (*(__IO uint32_t*)0x4000053CU) /**< (HSMCI) FIFO Memory Aperture0 207 */
#define REG_HSMCI_FIFO208 (*(__IO uint32_t*)0x40000540U) /**< (HSMCI) FIFO Memory Aperture0 208 */
#define REG_HSMCI_FIFO209 (*(__IO uint32_t*)0x40000544U) /**< (HSMCI) FIFO Memory Aperture0 209 */
#define REG_HSMCI_FIFO210 (*(__IO uint32_t*)0x40000548U) /**< (HSMCI) FIFO Memory Aperture0 210 */
#define REG_HSMCI_FIFO211 (*(__IO uint32_t*)0x4000054CU) /**< (HSMCI) FIFO Memory Aperture0 211 */
#define REG_HSMCI_FIFO212 (*(__IO uint32_t*)0x40000550U) /**< (HSMCI) FIFO Memory Aperture0 212 */
#define REG_HSMCI_FIFO213 (*(__IO uint32_t*)0x40000554U) /**< (HSMCI) FIFO Memory Aperture0 213 */
#define REG_HSMCI_FIFO214 (*(__IO uint32_t*)0x40000558U) /**< (HSMCI) FIFO Memory Aperture0 214 */
#define REG_HSMCI_FIFO215 (*(__IO uint32_t*)0x4000055CU) /**< (HSMCI) FIFO Memory Aperture0 215 */
#define REG_HSMCI_FIFO216 (*(__IO uint32_t*)0x40000560U) /**< (HSMCI) FIFO Memory Aperture0 216 */
#define REG_HSMCI_FIFO217 (*(__IO uint32_t*)0x40000564U) /**< (HSMCI) FIFO Memory Aperture0 217 */
#define REG_HSMCI_FIFO218 (*(__IO uint32_t*)0x40000568U) /**< (HSMCI) FIFO Memory Aperture0 218 */
#define REG_HSMCI_FIFO219 (*(__IO uint32_t*)0x4000056CU) /**< (HSMCI) FIFO Memory Aperture0 219 */
#define REG_HSMCI_FIFO220 (*(__IO uint32_t*)0x40000570U) /**< (HSMCI) FIFO Memory Aperture0 220 */
#define REG_HSMCI_FIFO221 (*(__IO uint32_t*)0x40000574U) /**< (HSMCI) FIFO Memory Aperture0 221 */
#define REG_HSMCI_FIFO222 (*(__IO uint32_t*)0x40000578U) /**< (HSMCI) FIFO Memory Aperture0 222 */
#define REG_HSMCI_FIFO223 (*(__IO uint32_t*)0x4000057CU) /**< (HSMCI) FIFO Memory Aperture0 223 */
#define REG_HSMCI_FIFO224 (*(__IO uint32_t*)0x40000580U) /**< (HSMCI) FIFO Memory Aperture0 224 */
#define REG_HSMCI_FIFO225 (*(__IO uint32_t*)0x40000584U) /**< (HSMCI) FIFO Memory Aperture0 225 */
#define REG_HSMCI_FIFO226 (*(__IO uint32_t*)0x40000588U) /**< (HSMCI) FIFO Memory Aperture0 226 */
#define REG_HSMCI_FIFO227 (*(__IO uint32_t*)0x4000058CU) /**< (HSMCI) FIFO Memory Aperture0 227 */
#define REG_HSMCI_FIFO228 (*(__IO uint32_t*)0x40000590U) /**< (HSMCI) FIFO Memory Aperture0 228 */
#define REG_HSMCI_FIFO229 (*(__IO uint32_t*)0x40000594U) /**< (HSMCI) FIFO Memory Aperture0 229 */
#define REG_HSMCI_FIFO230 (*(__IO uint32_t*)0x40000598U) /**< (HSMCI) FIFO Memory Aperture0 230 */
#define REG_HSMCI_FIFO231 (*(__IO uint32_t*)0x4000059CU) /**< (HSMCI) FIFO Memory Aperture0 231 */
#define REG_HSMCI_FIFO232 (*(__IO uint32_t*)0x400005A0U) /**< (HSMCI) FIFO Memory Aperture0 232 */
#define REG_HSMCI_FIFO233 (*(__IO uint32_t*)0x400005A4U) /**< (HSMCI) FIFO Memory Aperture0 233 */
#define REG_HSMCI_FIFO234 (*(__IO uint32_t*)0x400005A8U) /**< (HSMCI) FIFO Memory Aperture0 234 */
#define REG_HSMCI_FIFO235 (*(__IO uint32_t*)0x400005ACU) /**< (HSMCI) FIFO Memory Aperture0 235 */
#define REG_HSMCI_FIFO236 (*(__IO uint32_t*)0x400005B0U) /**< (HSMCI) FIFO Memory Aperture0 236 */
#define REG_HSMCI_FIFO237 (*(__IO uint32_t*)0x400005B4U) /**< (HSMCI) FIFO Memory Aperture0 237 */
#define REG_HSMCI_FIFO238 (*(__IO uint32_t*)0x400005B8U) /**< (HSMCI) FIFO Memory Aperture0 238 */
#define REG_HSMCI_FIFO239 (*(__IO uint32_t*)0x400005BCU) /**< (HSMCI) FIFO Memory Aperture0 239 */
#define REG_HSMCI_FIFO240 (*(__IO uint32_t*)0x400005C0U) /**< (HSMCI) FIFO Memory Aperture0 240 */
#define REG_HSMCI_FIFO241 (*(__IO uint32_t*)0x400005C4U) /**< (HSMCI) FIFO Memory Aperture0 241 */
#define REG_HSMCI_FIFO242 (*(__IO uint32_t*)0x400005C8U) /**< (HSMCI) FIFO Memory Aperture0 242 */
#define REG_HSMCI_FIFO243 (*(__IO uint32_t*)0x400005CCU) /**< (HSMCI) FIFO Memory Aperture0 243 */
#define REG_HSMCI_FIFO244 (*(__IO uint32_t*)0x400005D0U) /**< (HSMCI) FIFO Memory Aperture0 244 */
#define REG_HSMCI_FIFO245 (*(__IO uint32_t*)0x400005D4U) /**< (HSMCI) FIFO Memory Aperture0 245 */
#define REG_HSMCI_FIFO246 (*(__IO uint32_t*)0x400005D8U) /**< (HSMCI) FIFO Memory Aperture0 246 */
#define REG_HSMCI_FIFO247 (*(__IO uint32_t*)0x400005DCU) /**< (HSMCI) FIFO Memory Aperture0 247 */
#define REG_HSMCI_FIFO248 (*(__IO uint32_t*)0x400005E0U) /**< (HSMCI) FIFO Memory Aperture0 248 */
#define REG_HSMCI_FIFO249 (*(__IO uint32_t*)0x400005E4U) /**< (HSMCI) FIFO Memory Aperture0 249 */
#define REG_HSMCI_FIFO250 (*(__IO uint32_t*)0x400005E8U) /**< (HSMCI) FIFO Memory Aperture0 250 */
#define REG_HSMCI_FIFO251 (*(__IO uint32_t*)0x400005ECU) /**< (HSMCI) FIFO Memory Aperture0 251 */
#define REG_HSMCI_FIFO252 (*(__IO uint32_t*)0x400005F0U) /**< (HSMCI) FIFO Memory Aperture0 252 */
#define REG_HSMCI_FIFO253 (*(__IO uint32_t*)0x400005F4U) /**< (HSMCI) FIFO Memory Aperture0 253 */
#define REG_HSMCI_FIFO254 (*(__IO uint32_t*)0x400005F8U) /**< (HSMCI) FIFO Memory Aperture0 254 */
#define REG_HSMCI_FIFO255 (*(__IO uint32_t*)0x400005FCU) /**< (HSMCI) FIFO Memory Aperture0 255 */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for HSMCI peripheral ========== */
#define HSMCI_INSTANCE_ID 18
#define HSMCI_CLOCK_ID 18
#define HSMCI_DMAC_ID_TX 0
#define HSMCI_DMAC_ID_RX 0
#endif /* _SAME70_HSMCI_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for I2SC0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_I2SC0_INSTANCE_H_
#define _SAME70_I2SC0_INSTANCE_H_
/* ========== Register definition for I2SC0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_I2SC0_CR (0x4008C000) /**< (I2SC0) Control Register */
#define REG_I2SC0_MR (0x4008C004) /**< (I2SC0) Mode Register */
#define REG_I2SC0_SR (0x4008C008) /**< (I2SC0) Status Register */
#define REG_I2SC0_SCR (0x4008C00C) /**< (I2SC0) Status Clear Register */
#define REG_I2SC0_SSR (0x4008C010) /**< (I2SC0) Status Set Register */
#define REG_I2SC0_IER (0x4008C014) /**< (I2SC0) Interrupt Enable Register */
#define REG_I2SC0_IDR (0x4008C018) /**< (I2SC0) Interrupt Disable Register */
#define REG_I2SC0_IMR (0x4008C01C) /**< (I2SC0) Interrupt Mask Register */
#define REG_I2SC0_RHR (0x4008C020) /**< (I2SC0) Receiver Holding Register */
#define REG_I2SC0_THR (0x4008C024) /**< (I2SC0) Transmitter Holding Register */
#else
#define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */
#define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< (I2SC0) Mode Register */
#define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< (I2SC0) Status Register */
#define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */
#define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */
#define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Register */
#define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Register */
#define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< (I2SC0) Interrupt Mask Register */
#define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< (I2SC0) Receiver Holding Register */
#define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for I2SC0 peripheral ========== */
#define I2SC0_INSTANCE_ID 69
#define I2SC0_CLOCK_ID 69
#endif /* _SAME70_I2SC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for I2SC1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_I2SC1_INSTANCE_H_
#define _SAME70_I2SC1_INSTANCE_H_
/* ========== Register definition for I2SC1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_I2SC1_CR (0x40090000) /**< (I2SC1) Control Register */
#define REG_I2SC1_MR (0x40090004) /**< (I2SC1) Mode Register */
#define REG_I2SC1_SR (0x40090008) /**< (I2SC1) Status Register */
#define REG_I2SC1_SCR (0x4009000C) /**< (I2SC1) Status Clear Register */
#define REG_I2SC1_SSR (0x40090010) /**< (I2SC1) Status Set Register */
#define REG_I2SC1_IER (0x40090014) /**< (I2SC1) Interrupt Enable Register */
#define REG_I2SC1_IDR (0x40090018) /**< (I2SC1) Interrupt Disable Register */
#define REG_I2SC1_IMR (0x4009001C) /**< (I2SC1) Interrupt Mask Register */
#define REG_I2SC1_RHR (0x40090020) /**< (I2SC1) Receiver Holding Register */
#define REG_I2SC1_THR (0x40090024) /**< (I2SC1) Transmitter Holding Register */
#else
#define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< (I2SC1) Control Register */
#define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< (I2SC1) Mode Register */
#define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< (I2SC1) Status Register */
#define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< (I2SC1) Status Clear Register */
#define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< (I2SC1) Status Set Register */
#define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< (I2SC1) Interrupt Enable Register */
#define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< (I2SC1) Interrupt Disable Register */
#define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< (I2SC1) Interrupt Mask Register */
#define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< (I2SC1) Receiver Holding Register */
#define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< (I2SC1) Transmitter Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for I2SC1 peripheral ========== */
#define I2SC1_INSTANCE_ID 70
#define I2SC1_CLOCK_ID 70
#endif /* _SAME70_I2SC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ICM
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_ICM_INSTANCE_H_
#define _SAME70_ICM_INSTANCE_H_
/* ========== Register definition for ICM peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ICM_CFG (0x40048000) /**< (ICM) Configuration Register */
#define REG_ICM_CTRL (0x40048004) /**< (ICM) Control Register */
#define REG_ICM_SR (0x40048008) /**< (ICM) Status Register */
#define REG_ICM_IER (0x40048010) /**< (ICM) Interrupt Enable Register */
#define REG_ICM_IDR (0x40048014) /**< (ICM) Interrupt Disable Register */
#define REG_ICM_IMR (0x40048018) /**< (ICM) Interrupt Mask Register */
#define REG_ICM_ISR (0x4004801C) /**< (ICM) Interrupt Status Register */
#define REG_ICM_UASR (0x40048020) /**< (ICM) Undefined Access Status Register */
#define REG_ICM_DSCR (0x40048030) /**< (ICM) Region Descriptor Area Start Address Register */
#define REG_ICM_HASH (0x40048034) /**< (ICM) Region Hash Area Start Address Register */
#define REG_ICM_UIHVAL (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */
#define REG_ICM_UIHVAL0 (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */
#define REG_ICM_UIHVAL1 (0x4004803C) /**< (ICM) User Initial Hash Value 0 Register 1 */
#define REG_ICM_UIHVAL2 (0x40048040) /**< (ICM) User Initial Hash Value 0 Register 2 */
#define REG_ICM_UIHVAL3 (0x40048044) /**< (ICM) User Initial Hash Value 0 Register 3 */
#define REG_ICM_UIHVAL4 (0x40048048) /**< (ICM) User Initial Hash Value 0 Register 4 */
#define REG_ICM_UIHVAL5 (0x4004804C) /**< (ICM) User Initial Hash Value 0 Register 5 */
#define REG_ICM_UIHVAL6 (0x40048050) /**< (ICM) User Initial Hash Value 0 Register 6 */
#define REG_ICM_UIHVAL7 (0x40048054) /**< (ICM) User Initial Hash Value 0 Register 7 */
#else
#define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< (ICM) Configuration Register */
#define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< (ICM) Control Register */
#define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< (ICM) Status Register */
#define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< (ICM) Interrupt Enable Register */
#define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< (ICM) Interrupt Disable Register */
#define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< (ICM) Interrupt Mask Register */
#define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< (ICM) Interrupt Status Register */
#define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< (ICM) Undefined Access Status Register */
#define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< (ICM) Region Descriptor Area Start Address Register */
#define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< (ICM) Region Hash Area Start Address Register */
#define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */
#define REG_ICM_UIHVAL0 (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */
#define REG_ICM_UIHVAL1 (*(__O uint32_t*)0x4004803CU) /**< (ICM) User Initial Hash Value 0 Register 1 */
#define REG_ICM_UIHVAL2 (*(__O uint32_t*)0x40048040U) /**< (ICM) User Initial Hash Value 0 Register 2 */
#define REG_ICM_UIHVAL3 (*(__O uint32_t*)0x40048044U) /**< (ICM) User Initial Hash Value 0 Register 3 */
#define REG_ICM_UIHVAL4 (*(__O uint32_t*)0x40048048U) /**< (ICM) User Initial Hash Value 0 Register 4 */
#define REG_ICM_UIHVAL5 (*(__O uint32_t*)0x4004804CU) /**< (ICM) User Initial Hash Value 0 Register 5 */
#define REG_ICM_UIHVAL6 (*(__O uint32_t*)0x40048050U) /**< (ICM) User Initial Hash Value 0 Register 6 */
#define REG_ICM_UIHVAL7 (*(__O uint32_t*)0x40048054U) /**< (ICM) User Initial Hash Value 0 Register 7 */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for ICM peripheral ========== */
#define ICM_INSTANCE_ID 32
#define ICM_CLOCK_ID 32
#endif /* _SAME70_ICM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ISI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_ISI_INSTANCE_H_
#define _SAME70_ISI_INSTANCE_H_
/* ========== Register definition for ISI peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ISI_CFG1 (0x4004C000) /**< (ISI) ISI Configuration 1 Register */
#define REG_ISI_CFG2 (0x4004C004) /**< (ISI) ISI Configuration 2 Register */
#define REG_ISI_PSIZE (0x4004C008) /**< (ISI) ISI Preview Size Register */
#define REG_ISI_PDECF (0x4004C00C) /**< (ISI) ISI Preview Decimation Factor Register */
#define REG_ISI_Y2R_SET0 (0x4004C010) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
#define REG_ISI_Y2R_SET1 (0x4004C014) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
#define REG_ISI_R2Y_SET0 (0x4004C018) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
#define REG_ISI_R2Y_SET1 (0x4004C01C) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
#define REG_ISI_R2Y_SET2 (0x4004C020) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
#define REG_ISI_CR (0x4004C024) /**< (ISI) ISI Control Register */
#define REG_ISI_SR (0x4004C028) /**< (ISI) ISI Status Register */
#define REG_ISI_IER (0x4004C02C) /**< (ISI) ISI Interrupt Enable Register */
#define REG_ISI_IDR (0x4004C030) /**< (ISI) ISI Interrupt Disable Register */
#define REG_ISI_IMR (0x4004C034) /**< (ISI) ISI Interrupt Mask Register */
#define REG_ISI_DMA_CHER (0x4004C038) /**< (ISI) DMA Channel Enable Register */
#define REG_ISI_DMA_CHDR (0x4004C03C) /**< (ISI) DMA Channel Disable Register */
#define REG_ISI_DMA_CHSR (0x4004C040) /**< (ISI) DMA Channel Status Register */
#define REG_ISI_DMA_P_ADDR (0x4004C044) /**< (ISI) DMA Preview Base Address Register */
#define REG_ISI_DMA_P_CTRL (0x4004C048) /**< (ISI) DMA Preview Control Register */
#define REG_ISI_DMA_P_DSCR (0x4004C04C) /**< (ISI) DMA Preview Descriptor Address Register */
#define REG_ISI_DMA_C_ADDR (0x4004C050) /**< (ISI) DMA Codec Base Address Register */
#define REG_ISI_DMA_C_CTRL (0x4004C054) /**< (ISI) DMA Codec Control Register */
#define REG_ISI_DMA_C_DSCR (0x4004C058) /**< (ISI) DMA Codec Descriptor Address Register */
#define REG_ISI_WPMR (0x4004C0E4) /**< (ISI) Write Protection Mode Register */
#define REG_ISI_WPSR (0x4004C0E8) /**< (ISI) Write Protection Status Register */
#else
#define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< (ISI) ISI Configuration 1 Register */
#define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< (ISI) ISI Configuration 2 Register */
#define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< (ISI) ISI Preview Size Register */
#define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< (ISI) ISI Preview Decimation Factor Register */
#define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
#define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
#define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
#define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
#define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
#define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< (ISI) ISI Control Register */
#define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< (ISI) ISI Status Register */
#define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< (ISI) ISI Interrupt Enable Register */
#define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< (ISI) ISI Interrupt Disable Register */
#define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< (ISI) ISI Interrupt Mask Register */
#define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< (ISI) DMA Channel Enable Register */
#define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< (ISI) DMA Channel Disable Register */
#define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< (ISI) DMA Channel Status Register */
#define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< (ISI) DMA Preview Base Address Register */
#define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< (ISI) DMA Preview Control Register */
#define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< (ISI) DMA Preview Descriptor Address Register */
#define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< (ISI) DMA Codec Base Address Register */
#define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< (ISI) DMA Codec Control Register */
#define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< (ISI) DMA Codec Descriptor Address Register */
#define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< (ISI) Write Protection Mode Register */
#define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< (ISI) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for ISI peripheral ========== */
#define ISI_INSTANCE_ID 59
#define ISI_CLOCK_ID 59
#endif /* _SAME70_ISI_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MATRIX
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_MATRIX_INSTANCE_H_
#define _SAME70_MATRIX_INSTANCE_H_
/* ========== Register definition for MATRIX peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MATRIX_PRAS0 (0x40088080) /**< (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0 (0x40088084) /**< (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1 (0x40088088) /**< (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1 (0x4008808C) /**< (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2 (0x40088090) /**< (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2 (0x40088094) /**< (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3 (0x40088098) /**< (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3 (0x4008809C) /**< (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4 (0x400880A0) /**< (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4 (0x400880A4) /**< (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5 (0x400880A8) /**< (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5 (0x400880AC) /**< (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6 (0x400880B0) /**< (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6 (0x400880B4) /**< (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7 (0x400880B8) /**< (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7 (0x400880BC) /**< (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8 (0x400880C0) /**< (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8 (0x400880C4) /**< (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_MCFG (0x40088000) /**< (MATRIX) Master Configuration Register 0 */
#define REG_MATRIX_MCFG0 (0x40088000) /**< (MATRIX) Master Configuration Register 0 */
#define REG_MATRIX_MCFG1 (0x40088004) /**< (MATRIX) Master Configuration Register 1 */
#define REG_MATRIX_MCFG2 (0x40088008) /**< (MATRIX) Master Configuration Register 2 */
#define REG_MATRIX_MCFG3 (0x4008800C) /**< (MATRIX) Master Configuration Register 3 */
#define REG_MATRIX_MCFG4 (0x40088010) /**< (MATRIX) Master Configuration Register 4 */
#define REG_MATRIX_MCFG5 (0x40088014) /**< (MATRIX) Master Configuration Register 5 */
#define REG_MATRIX_MCFG6 (0x40088018) /**< (MATRIX) Master Configuration Register 6 */
#define REG_MATRIX_MCFG7 (0x4008801C) /**< (MATRIX) Master Configuration Register 7 */
#define REG_MATRIX_MCFG8 (0x40088020) /**< (MATRIX) Master Configuration Register 8 */
#define REG_MATRIX_MCFG9 (0x40088024) /**< (MATRIX) Master Configuration Register 9 */
#define REG_MATRIX_MCFG10 (0x40088028) /**< (MATRIX) Master Configuration Register 10 */
#define REG_MATRIX_MCFG11 (0x4008802C) /**< (MATRIX) Master Configuration Register 11 */
#define REG_MATRIX_MCFG12 (0x40088030) /**< (MATRIX) Master Configuration Register 12 */
#define REG_MATRIX_SCFG (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */
#define REG_MATRIX_SCFG0 (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */
#define REG_MATRIX_SCFG1 (0x40088044) /**< (MATRIX) Slave Configuration Register 1 */
#define REG_MATRIX_SCFG2 (0x40088048) /**< (MATRIX) Slave Configuration Register 2 */
#define REG_MATRIX_SCFG3 (0x4008804C) /**< (MATRIX) Slave Configuration Register 3 */
#define REG_MATRIX_SCFG4 (0x40088050) /**< (MATRIX) Slave Configuration Register 4 */
#define REG_MATRIX_SCFG5 (0x40088054) /**< (MATRIX) Slave Configuration Register 5 */
#define REG_MATRIX_SCFG6 (0x40088058) /**< (MATRIX) Slave Configuration Register 6 */
#define REG_MATRIX_SCFG7 (0x4008805C) /**< (MATRIX) Slave Configuration Register 7 */
#define REG_MATRIX_SCFG8 (0x40088060) /**< (MATRIX) Slave Configuration Register 8 */
#define REG_MATRIX_MRCR (0x40088100) /**< (MATRIX) Master Remap Control Register */
#define REG_CCFG_CAN0 (0x40088110) /**< (MATRIX) CAN0 Configuration Register */
#define REG_CCFG_SYSIO (0x40088114) /**< (MATRIX) System I/O and CAN1 Configuration Register */
#define REG_CCFG_PCCR (0x40088118) /**< (MATRIX) Peripheral Clock Configuration Register */
#define REG_CCFG_DYNCKG (0x4008811C) /**< (MATRIX) Dynamic Clock Gating Register */
#define REG_CCFG_SMCNFCS (0x40088124) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */
#define REG_MATRIX_WPMR (0x400881E4) /**< (MATRIX) Write Protection Mode Register */
#define REG_MATRIX_WPSR (0x400881E8) /**< (MATRIX) Write Protection Status Register */
#else
#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */
#define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */
#define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< (MATRIX) Master Configuration Register 1 */
#define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< (MATRIX) Master Configuration Register 2 */
#define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< (MATRIX) Master Configuration Register 3 */
#define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< (MATRIX) Master Configuration Register 4 */
#define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< (MATRIX) Master Configuration Register 5 */
#define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< (MATRIX) Master Configuration Register 6 */
#define REG_MATRIX_MCFG7 (*(__IO uint32_t*)0x4008801CU) /**< (MATRIX) Master Configuration Register 7 */
#define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< (MATRIX) Master Configuration Register 8 */
#define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) /**< (MATRIX) Master Configuration Register 9 */
#define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) /**< (MATRIX) Master Configuration Register 10 */
#define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) /**< (MATRIX) Master Configuration Register 11 */
#define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) /**< (MATRIX) Master Configuration Register 12 */
#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */
#define REG_MATRIX_SCFG0 (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */
#define REG_MATRIX_SCFG1 (*(__IO uint32_t*)0x40088044U) /**< (MATRIX) Slave Configuration Register 1 */
#define REG_MATRIX_SCFG2 (*(__IO uint32_t*)0x40088048U) /**< (MATRIX) Slave Configuration Register 2 */
#define REG_MATRIX_SCFG3 (*(__IO uint32_t*)0x4008804CU) /**< (MATRIX) Slave Configuration Register 3 */
#define REG_MATRIX_SCFG4 (*(__IO uint32_t*)0x40088050U) /**< (MATRIX) Slave Configuration Register 4 */
#define REG_MATRIX_SCFG5 (*(__IO uint32_t*)0x40088054U) /**< (MATRIX) Slave Configuration Register 5 */
#define REG_MATRIX_SCFG6 (*(__IO uint32_t*)0x40088058U) /**< (MATRIX) Slave Configuration Register 6 */
#define REG_MATRIX_SCFG7 (*(__IO uint32_t*)0x4008805CU) /**< (MATRIX) Slave Configuration Register 7 */
#define REG_MATRIX_SCFG8 (*(__IO uint32_t*)0x40088060U) /**< (MATRIX) Slave Configuration Register 8 */
#define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< (MATRIX) Master Remap Control Register */
#define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< (MATRIX) CAN0 Configuration Register */
#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< (MATRIX) System I/O and CAN1 Configuration Register */
#define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) /**< (MATRIX) Peripheral Clock Configuration Register */
#define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) /**< (MATRIX) Dynamic Clock Gating Register */
#define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */
#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< (MATRIX) Write Protection Mode Register */
#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< (MATRIX) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME70_MATRIX_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MCAN0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_MCAN0_INSTANCE_H_
#define _SAME70_MCAN0_INSTANCE_H_
/* ========== Register definition for MCAN0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MCAN0_CREL (0x40030000) /**< (MCAN0) Core Release Register */
#define REG_MCAN0_ENDN (0x40030004) /**< (MCAN0) Endian Register */
#define REG_MCAN0_CUST (0x40030008) /**< (MCAN0) Customer Register */
#define REG_MCAN0_DBTP (0x4003000C) /**< (MCAN0) Data Bit Timing and Prescaler Register */
#define REG_MCAN0_TEST (0x40030010) /**< (MCAN0) Test Register */
#define REG_MCAN0_RWD (0x40030014) /**< (MCAN0) RAM Watchdog Register */
#define REG_MCAN0_CCCR (0x40030018) /**< (MCAN0) CC Control Register */
#define REG_MCAN0_NBTP (0x4003001C) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */
#define REG_MCAN0_TSCC (0x40030020) /**< (MCAN0) Timestamp Counter Configuration Register */
#define REG_MCAN0_TSCV (0x40030024) /**< (MCAN0) Timestamp Counter Value Register */
#define REG_MCAN0_TOCC (0x40030028) /**< (MCAN0) Timeout Counter Configuration Register */
#define REG_MCAN0_TOCV (0x4003002C) /**< (MCAN0) Timeout Counter Value Register */
#define REG_MCAN0_ECR (0x40030040) /**< (MCAN0) Error Counter Register */
#define REG_MCAN0_PSR (0x40030044) /**< (MCAN0) Protocol Status Register */
#define REG_MCAN0_TDCR (0x40030048) /**< (MCAN0) Transmit Delay Compensation Register */
#define REG_MCAN0_IR (0x40030050) /**< (MCAN0) Interrupt Register */
#define REG_MCAN0_IE (0x40030054) /**< (MCAN0) Interrupt Enable Register */
#define REG_MCAN0_ILS (0x40030058) /**< (MCAN0) Interrupt Line Select Register */
#define REG_MCAN0_ILE (0x4003005C) /**< (MCAN0) Interrupt Line Enable Register */
#define REG_MCAN0_GFC (0x40030080) /**< (MCAN0) Global Filter Configuration Register */
#define REG_MCAN0_SIDFC (0x40030084) /**< (MCAN0) Standard ID Filter Configuration Register */
#define REG_MCAN0_XIDFC (0x40030088) /**< (MCAN0) Extended ID Filter Configuration Register */
#define REG_MCAN0_XIDAM (0x40030090) /**< (MCAN0) Extended ID AND Mask Register */
#define REG_MCAN0_HPMS (0x40030094) /**< (MCAN0) High Priority Message Status Register */
#define REG_MCAN0_NDAT1 (0x40030098) /**< (MCAN0) New Data 1 Register */
#define REG_MCAN0_NDAT2 (0x4003009C) /**< (MCAN0) New Data 2 Register */
#define REG_MCAN0_RXF0C (0x400300A0) /**< (MCAN0) Receive FIFO 0 Configuration Register */
#define REG_MCAN0_RXF0S (0x400300A4) /**< (MCAN0) Receive FIFO 0 Status Register */
#define REG_MCAN0_RXF0A (0x400300A8) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */
#define REG_MCAN0_RXBC (0x400300AC) /**< (MCAN0) Receive Rx Buffer Configuration Register */
#define REG_MCAN0_RXF1C (0x400300B0) /**< (MCAN0) Receive FIFO 1 Configuration Register */
#define REG_MCAN0_RXF1S (0x400300B4) /**< (MCAN0) Receive FIFO 1 Status Register */
#define REG_MCAN0_RXF1A (0x400300B8) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */
#define REG_MCAN0_RXESC (0x400300BC) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
#define REG_MCAN0_TXBC (0x400300C0) /**< (MCAN0) Transmit Buffer Configuration Register */
#define REG_MCAN0_TXFQS (0x400300C4) /**< (MCAN0) Transmit FIFO/Queue Status Register */
#define REG_MCAN0_TXESC (0x400300C8) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */
#define REG_MCAN0_TXBRP (0x400300CC) /**< (MCAN0) Transmit Buffer Request Pending Register */
#define REG_MCAN0_TXBAR (0x400300D0) /**< (MCAN0) Transmit Buffer Add Request Register */
#define REG_MCAN0_TXBCR (0x400300D4) /**< (MCAN0) Transmit Buffer Cancellation Request Register */
#define REG_MCAN0_TXBTO (0x400300D8) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */
#define REG_MCAN0_TXBCF (0x400300DC) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */
#define REG_MCAN0_TXBTIE (0x400300E0) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
#define REG_MCAN0_TXBCIE (0x400300E4) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
#define REG_MCAN0_TXEFC (0x400300F0) /**< (MCAN0) Transmit Event FIFO Configuration Register */
#define REG_MCAN0_TXEFS (0x400300F4) /**< (MCAN0) Transmit Event FIFO Status Register */
#define REG_MCAN0_TXEFA (0x400300F8) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */
#else
#define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U) /**< (MCAN0) Core Release Register */
#define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U) /**< (MCAN0) Endian Register */
#define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< (MCAN0) Customer Register */
#define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU) /**< (MCAN0) Data Bit Timing and Prescaler Register */
#define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< (MCAN0) Test Register */
#define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< (MCAN0) RAM Watchdog Register */
#define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< (MCAN0) CC Control Register */
#define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */
#define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< (MCAN0) Timestamp Counter Configuration Register */
#define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< (MCAN0) Timestamp Counter Value Register */
#define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< (MCAN0) Timeout Counter Configuration Register */
#define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< (MCAN0) Timeout Counter Value Register */
#define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< (MCAN0) Error Counter Register */
#define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< (MCAN0) Protocol Status Register */
#define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U) /**< (MCAN0) Transmit Delay Compensation Register */
#define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< (MCAN0) Interrupt Register */
#define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< (MCAN0) Interrupt Enable Register */
#define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< (MCAN0) Interrupt Line Select Register */
#define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< (MCAN0) Interrupt Line Enable Register */
#define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< (MCAN0) Global Filter Configuration Register */
#define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< (MCAN0) Standard ID Filter Configuration Register */
#define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< (MCAN0) Extended ID Filter Configuration Register */
#define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< (MCAN0) Extended ID AND Mask Register */
#define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< (MCAN0) High Priority Message Status Register */
#define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< (MCAN0) New Data 1 Register */
#define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< (MCAN0) New Data 2 Register */
#define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< (MCAN0) Receive FIFO 0 Configuration Register */
#define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< (MCAN0) Receive FIFO 0 Status Register */
#define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */
#define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< (MCAN0) Receive Rx Buffer Configuration Register */
#define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< (MCAN0) Receive FIFO 1 Configuration Register */
#define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< (MCAN0) Receive FIFO 1 Status Register */
#define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */
#define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
#define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< (MCAN0) Transmit Buffer Configuration Register */
#define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< (MCAN0) Transmit FIFO/Queue Status Register */
#define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */
#define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< (MCAN0) Transmit Buffer Request Pending Register */
#define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< (MCAN0) Transmit Buffer Add Request Register */
#define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< (MCAN0) Transmit Buffer Cancellation Request Register */
#define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */
#define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */
#define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
#define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
#define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< (MCAN0) Transmit Event FIFO Configuration Register */
#define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< (MCAN0) Transmit Event FIFO Status Register */
#define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for MCAN0 peripheral ========== */
#define MCAN0_INSTANCE_ID 35
#define MCAN0_CLOCK_ID 35
#endif /* _SAME70_MCAN0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MCAN1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_MCAN1_INSTANCE_H_
#define _SAME70_MCAN1_INSTANCE_H_
/* ========== Register definition for MCAN1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MCAN1_CREL (0x40034000) /**< (MCAN1) Core Release Register */
#define REG_MCAN1_ENDN (0x40034004) /**< (MCAN1) Endian Register */
#define REG_MCAN1_CUST (0x40034008) /**< (MCAN1) Customer Register */
#define REG_MCAN1_DBTP (0x4003400C) /**< (MCAN1) Data Bit Timing and Prescaler Register */
#define REG_MCAN1_TEST (0x40034010) /**< (MCAN1) Test Register */
#define REG_MCAN1_RWD (0x40034014) /**< (MCAN1) RAM Watchdog Register */
#define REG_MCAN1_CCCR (0x40034018) /**< (MCAN1) CC Control Register */
#define REG_MCAN1_NBTP (0x4003401C) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */
#define REG_MCAN1_TSCC (0x40034020) /**< (MCAN1) Timestamp Counter Configuration Register */
#define REG_MCAN1_TSCV (0x40034024) /**< (MCAN1) Timestamp Counter Value Register */
#define REG_MCAN1_TOCC (0x40034028) /**< (MCAN1) Timeout Counter Configuration Register */
#define REG_MCAN1_TOCV (0x4003402C) /**< (MCAN1) Timeout Counter Value Register */
#define REG_MCAN1_ECR (0x40034040) /**< (MCAN1) Error Counter Register */
#define REG_MCAN1_PSR (0x40034044) /**< (MCAN1) Protocol Status Register */
#define REG_MCAN1_TDCR (0x40034048) /**< (MCAN1) Transmit Delay Compensation Register */
#define REG_MCAN1_IR (0x40034050) /**< (MCAN1) Interrupt Register */
#define REG_MCAN1_IE (0x40034054) /**< (MCAN1) Interrupt Enable Register */
#define REG_MCAN1_ILS (0x40034058) /**< (MCAN1) Interrupt Line Select Register */
#define REG_MCAN1_ILE (0x4003405C) /**< (MCAN1) Interrupt Line Enable Register */
#define REG_MCAN1_GFC (0x40034080) /**< (MCAN1) Global Filter Configuration Register */
#define REG_MCAN1_SIDFC (0x40034084) /**< (MCAN1) Standard ID Filter Configuration Register */
#define REG_MCAN1_XIDFC (0x40034088) /**< (MCAN1) Extended ID Filter Configuration Register */
#define REG_MCAN1_XIDAM (0x40034090) /**< (MCAN1) Extended ID AND Mask Register */
#define REG_MCAN1_HPMS (0x40034094) /**< (MCAN1) High Priority Message Status Register */
#define REG_MCAN1_NDAT1 (0x40034098) /**< (MCAN1) New Data 1 Register */
#define REG_MCAN1_NDAT2 (0x4003409C) /**< (MCAN1) New Data 2 Register */
#define REG_MCAN1_RXF0C (0x400340A0) /**< (MCAN1) Receive FIFO 0 Configuration Register */
#define REG_MCAN1_RXF0S (0x400340A4) /**< (MCAN1) Receive FIFO 0 Status Register */
#define REG_MCAN1_RXF0A (0x400340A8) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */
#define REG_MCAN1_RXBC (0x400340AC) /**< (MCAN1) Receive Rx Buffer Configuration Register */
#define REG_MCAN1_RXF1C (0x400340B0) /**< (MCAN1) Receive FIFO 1 Configuration Register */
#define REG_MCAN1_RXF1S (0x400340B4) /**< (MCAN1) Receive FIFO 1 Status Register */
#define REG_MCAN1_RXF1A (0x400340B8) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */
#define REG_MCAN1_RXESC (0x400340BC) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */
#define REG_MCAN1_TXBC (0x400340C0) /**< (MCAN1) Transmit Buffer Configuration Register */
#define REG_MCAN1_TXFQS (0x400340C4) /**< (MCAN1) Transmit FIFO/Queue Status Register */
#define REG_MCAN1_TXESC (0x400340C8) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */
#define REG_MCAN1_TXBRP (0x400340CC) /**< (MCAN1) Transmit Buffer Request Pending Register */
#define REG_MCAN1_TXBAR (0x400340D0) /**< (MCAN1) Transmit Buffer Add Request Register */
#define REG_MCAN1_TXBCR (0x400340D4) /**< (MCAN1) Transmit Buffer Cancellation Request Register */
#define REG_MCAN1_TXBTO (0x400340D8) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */
#define REG_MCAN1_TXBCF (0x400340DC) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */
#define REG_MCAN1_TXBTIE (0x400340E0) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */
#define REG_MCAN1_TXBCIE (0x400340E4) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */
#define REG_MCAN1_TXEFC (0x400340F0) /**< (MCAN1) Transmit Event FIFO Configuration Register */
#define REG_MCAN1_TXEFS (0x400340F4) /**< (MCAN1) Transmit Event FIFO Status Register */
#define REG_MCAN1_TXEFA (0x400340F8) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */
#else
#define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< (MCAN1) Core Release Register */
#define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< (MCAN1) Endian Register */
#define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< (MCAN1) Customer Register */
#define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< (MCAN1) Data Bit Timing and Prescaler Register */
#define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< (MCAN1) Test Register */
#define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< (MCAN1) RAM Watchdog Register */
#define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< (MCAN1) CC Control Register */
#define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */
#define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< (MCAN1) Timestamp Counter Configuration Register */
#define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< (MCAN1) Timestamp Counter Value Register */
#define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< (MCAN1) Timeout Counter Configuration Register */
#define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< (MCAN1) Timeout Counter Value Register */
#define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< (MCAN1) Error Counter Register */
#define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< (MCAN1) Protocol Status Register */
#define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< (MCAN1) Transmit Delay Compensation Register */
#define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< (MCAN1) Interrupt Register */
#define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< (MCAN1) Interrupt Enable Register */
#define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< (MCAN1) Interrupt Line Select Register */
#define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< (MCAN1) Interrupt Line Enable Register */
#define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< (MCAN1) Global Filter Configuration Register */
#define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< (MCAN1) Standard ID Filter Configuration Register */
#define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< (MCAN1) Extended ID Filter Configuration Register */
#define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< (MCAN1) Extended ID AND Mask Register */
#define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< (MCAN1) High Priority Message Status Register */
#define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< (MCAN1) New Data 1 Register */
#define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< (MCAN1) New Data 2 Register */
#define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< (MCAN1) Receive FIFO 0 Configuration Register */
#define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< (MCAN1) Receive FIFO 0 Status Register */
#define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */
#define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< (MCAN1) Receive Rx Buffer Configuration Register */
#define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< (MCAN1) Receive FIFO 1 Configuration Register */
#define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< (MCAN1) Receive FIFO 1 Status Register */
#define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */
#define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */
#define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< (MCAN1) Transmit Buffer Configuration Register */
#define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< (MCAN1) Transmit FIFO/Queue Status Register */
#define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */
#define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< (MCAN1) Transmit Buffer Request Pending Register */
#define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< (MCAN1) Transmit Buffer Add Request Register */
#define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< (MCAN1) Transmit Buffer Cancellation Request Register */
#define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */
#define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */
#define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */
#define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */
#define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< (MCAN1) Transmit Event FIFO Configuration Register */
#define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< (MCAN1) Transmit Event FIFO Status Register */
#define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for MCAN1 peripheral ========== */
#define MCAN1_INSTANCE_ID 37
#define MCAN1_CLOCK_ID 37
#endif /* _SAME70_MCAN1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PIOA
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PIOA_INSTANCE_H_
#define _SAME70_PIOA_INSTANCE_H_
/* ========== Register definition for PIOA peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOA_PER (0x400E0E00) /**< (PIOA) PIO Enable Register */
#define REG_PIOA_PDR (0x400E0E04) /**< (PIOA) PIO Disable Register */
#define REG_PIOA_PSR (0x400E0E08) /**< (PIOA) PIO Status Register */
#define REG_PIOA_OER (0x400E0E10) /**< (PIOA) Output Enable Register */
#define REG_PIOA_ODR (0x400E0E14) /**< (PIOA) Output Disable Register */
#define REG_PIOA_OSR (0x400E0E18) /**< (PIOA) Output Status Register */
#define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR (0x400E0E24) /**< (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR (0x400E0E28) /**< (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR (0x400E0E30) /**< (PIOA) Set Output Data Register */
#define REG_PIOA_CODR (0x400E0E34) /**< (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR (0x400E0E38) /**< (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR (0x400E0E3C) /**< (PIOA) Pin Data Status Register */
#define REG_PIOA_IER (0x400E0E40) /**< (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR (0x400E0E44) /**< (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR (0x400E0E48) /**< (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR (0x400E0E4C) /**< (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER (0x400E0E50) /**< (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR (0x400E0E54) /**< (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR (0x400E0E58) /**< (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR (0x400E0E60) /**< (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER (0x400E0E64) /**< (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR (0x400E0E68) /**< (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */
#define REG_PIOA_ABCDSR0 (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */
#define REG_PIOA_ABCDSR1 (0x400E0E74) /**< (PIOA) Peripheral ABCD Select Register 1 */
#define REG_PIOA_IFSCDR (0x400E0E80) /**< (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER (0x400E0E84) /**< (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR (0x400E0E88) /**< (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR (0x400E0E8C) /**< (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR (0x400E0E90) /**< (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER (0x400E0E94) /**< (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR (0x400E0E98) /**< (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER (0x400E0EA0) /**< (PIOA) Output Write Enable */
#define REG_PIOA_OWDR (0x400E0EA4) /**< (PIOA) Output Write Disable */
#define REG_PIOA_OWSR (0x400E0EA8) /**< (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER (0x400E0EB0) /**< (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR (0x400E0EB4) /**< (PIOA) Additional Interrupt Modes Disable Register */
#define REG_PIOA_AIMMR (0x400E0EB8) /**< (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR (0x400E0EC0) /**< (PIOA) Edge Select Register */
#define REG_PIOA_LSR (0x400E0EC4) /**< (PIOA) Level Select Register */
#define REG_PIOA_ELSR (0x400E0EC8) /**< (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR (0x400E0ED0) /**< (PIOA) Falling Edge/Low-Level Select Register */
#define REG_PIOA_REHLSR (0x400E0ED4) /**< (PIOA) Rising Edge/High-Level Select Register */
#define REG_PIOA_FRLHSR (0x400E0ED8) /**< (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR (0x400E0EE0) /**< (PIOA) Lock Status */
#define REG_PIOA_WPMR (0x400E0EE4) /**< (PIOA) Write Protection Mode Register */
#define REG_PIOA_WPSR (0x400E0EE8) /**< (PIOA) Write Protection Status Register */
#define REG_PIOA_SCHMITT (0x400E0F00) /**< (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DRIVER (0x400E0F18) /**< (PIOA) I/O Drive Register */
#define REG_PIOA_PCMR (0x400E0F50) /**< (PIOA) Parallel Capture Mode Register */
#define REG_PIOA_PCIER (0x400E0F54) /**< (PIOA) Parallel Capture Interrupt Enable Register */
#define REG_PIOA_PCIDR (0x400E0F58) /**< (PIOA) Parallel Capture Interrupt Disable Register */
#define REG_PIOA_PCIMR (0x400E0F5C) /**< (PIOA) Parallel Capture Interrupt Mask Register */
#define REG_PIOA_PCISR (0x400E0F60) /**< (PIOA) Parallel Capture Interrupt Status Register */
#define REG_PIOA_PCRHR (0x400E0F64) /**< (PIOA) Parallel Capture Reception Holding Register */
#else
#define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< (PIOA) PIO Enable Register */
#define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< (PIOA) PIO Disable Register */
#define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< (PIOA) PIO Status Register */
#define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< (PIOA) Output Enable Register */
#define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< (PIOA) Output Disable Register */
#define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< (PIOA) Output Status Register */
#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< (PIOA) Set Output Data Register */
#define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< (PIOA) Pin Data Status Register */
#define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */
#define REG_PIOA_ABCDSR0 (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */
#define REG_PIOA_ABCDSR1 (*(__IO uint32_t*)0x400E0E74U) /**< (PIOA) Peripheral ABCD Select Register 1 */
#define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< (PIOA) Output Write Enable */
#define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< (PIOA) Output Write Disable */
#define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< (PIOA) Additional Interrupt Modes Disable Register */
#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< (PIOA) Edge Select Register */
#define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< (PIOA) Level Select Register */
#define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< (PIOA) Falling Edge/Low-Level Select Register */
#define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< (PIOA) Rising Edge/High-Level Select Register */
#define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< (PIOA) Lock Status */
#define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< (PIOA) Write Protection Mode Register */
#define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< (PIOA) Write Protection Status Register */
#define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< (PIOA) I/O Drive Register */
#define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< (PIOA) Parallel Capture Mode Register */
#define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< (PIOA) Parallel Capture Interrupt Enable Register */
#define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< (PIOA) Parallel Capture Interrupt Disable Register */
#define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< (PIOA) Parallel Capture Interrupt Mask Register */
#define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< (PIOA) Parallel Capture Interrupt Status Register */
#define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< (PIOA) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PIOA peripheral ========== */
#define PIOA_INSTANCE_ID 10
#define PIOA_CLOCK_ID 10
#define PIOA_DMAC_ID_RX 34
#endif /* _SAME70_PIOA_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PIOB
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PIOB_INSTANCE_H_
#define _SAME70_PIOB_INSTANCE_H_
/* ========== Register definition for PIOB peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOB_PER (0x400E1000) /**< (PIOB) PIO Enable Register */
#define REG_PIOB_PDR (0x400E1004) /**< (PIOB) PIO Disable Register */
#define REG_PIOB_PSR (0x400E1008) /**< (PIOB) PIO Status Register */
#define REG_PIOB_OER (0x400E1010) /**< (PIOB) Output Enable Register */
#define REG_PIOB_ODR (0x400E1014) /**< (PIOB) Output Disable Register */
#define REG_PIOB_OSR (0x400E1018) /**< (PIOB) Output Status Register */
#define REG_PIOB_IFER (0x400E1020) /**< (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR (0x400E1024) /**< (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR (0x400E1028) /**< (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR (0x400E1030) /**< (PIOB) Set Output Data Register */
#define REG_PIOB_CODR (0x400E1034) /**< (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR (0x400E1038) /**< (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR (0x400E103C) /**< (PIOB) Pin Data Status Register */
#define REG_PIOB_IER (0x400E1040) /**< (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR (0x400E1044) /**< (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR (0x400E1048) /**< (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR (0x400E104C) /**< (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER (0x400E1050) /**< (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR (0x400E1054) /**< (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR (0x400E1058) /**< (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR (0x400E1060) /**< (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER (0x400E1064) /**< (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR (0x400E1068) /**< (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */
#define REG_PIOB_ABCDSR0 (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */
#define REG_PIOB_ABCDSR1 (0x400E1074) /**< (PIOB) Peripheral ABCD Select Register 1 */
#define REG_PIOB_IFSCDR (0x400E1080) /**< (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER (0x400E1084) /**< (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR (0x400E1088) /**< (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR (0x400E108C) /**< (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR (0x400E1090) /**< (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER (0x400E1094) /**< (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR (0x400E1098) /**< (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER (0x400E10A0) /**< (PIOB) Output Write Enable */
#define REG_PIOB_OWDR (0x400E10A4) /**< (PIOB) Output Write Disable */
#define REG_PIOB_OWSR (0x400E10A8) /**< (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER (0x400E10B0) /**< (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR (0x400E10B4) /**< (PIOB) Additional Interrupt Modes Disable Register */
#define REG_PIOB_AIMMR (0x400E10B8) /**< (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR (0x400E10C0) /**< (PIOB) Edge Select Register */
#define REG_PIOB_LSR (0x400E10C4) /**< (PIOB) Level Select Register */
#define REG_PIOB_ELSR (0x400E10C8) /**< (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR (0x400E10D0) /**< (PIOB) Falling Edge/Low-Level Select Register */
#define REG_PIOB_REHLSR (0x400E10D4) /**< (PIOB) Rising Edge/High-Level Select Register */
#define REG_PIOB_FRLHSR (0x400E10D8) /**< (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR (0x400E10E0) /**< (PIOB) Lock Status */
#define REG_PIOB_WPMR (0x400E10E4) /**< (PIOB) Write Protection Mode Register */
#define REG_PIOB_WPSR (0x400E10E8) /**< (PIOB) Write Protection Status Register */
#define REG_PIOB_SCHMITT (0x400E1100) /**< (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DRIVER (0x400E1118) /**< (PIOB) I/O Drive Register */
#define REG_PIOB_PCMR (0x400E1150) /**< (PIOB) Parallel Capture Mode Register */
#define REG_PIOB_PCIER (0x400E1154) /**< (PIOB) Parallel Capture Interrupt Enable Register */
#define REG_PIOB_PCIDR (0x400E1158) /**< (PIOB) Parallel Capture Interrupt Disable Register */
#define REG_PIOB_PCIMR (0x400E115C) /**< (PIOB) Parallel Capture Interrupt Mask Register */
#define REG_PIOB_PCISR (0x400E1160) /**< (PIOB) Parallel Capture Interrupt Status Register */
#define REG_PIOB_PCRHR (0x400E1164) /**< (PIOB) Parallel Capture Reception Holding Register */
#else
#define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< (PIOB) PIO Enable Register */
#define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< (PIOB) PIO Disable Register */
#define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< (PIOB) PIO Status Register */
#define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< (PIOB) Output Enable Register */
#define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< (PIOB) Output Disable Register */
#define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< (PIOB) Output Status Register */
#define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< (PIOB) Set Output Data Register */
#define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< (PIOB) Pin Data Status Register */
#define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */
#define REG_PIOB_ABCDSR0 (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */
#define REG_PIOB_ABCDSR1 (*(__IO uint32_t*)0x400E1074U) /**< (PIOB) Peripheral ABCD Select Register 1 */
#define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< (PIOB) Output Write Enable */
#define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< (PIOB) Output Write Disable */
#define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< (PIOB) Additional Interrupt Modes Disable Register */
#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< (PIOB) Edge Select Register */
#define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< (PIOB) Level Select Register */
#define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< (PIOB) Falling Edge/Low-Level Select Register */
#define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< (PIOB) Rising Edge/High-Level Select Register */
#define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< (PIOB) Lock Status */
#define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< (PIOB) Write Protection Mode Register */
#define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< (PIOB) Write Protection Status Register */
#define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< (PIOB) I/O Drive Register */
#define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< (PIOB) Parallel Capture Mode Register */
#define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< (PIOB) Parallel Capture Interrupt Enable Register */
#define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< (PIOB) Parallel Capture Interrupt Disable Register */
#define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< (PIOB) Parallel Capture Interrupt Mask Register */
#define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< (PIOB) Parallel Capture Interrupt Status Register */
#define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< (PIOB) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PIOB peripheral ========== */
#define PIOB_INSTANCE_ID 11
#define PIOB_CLOCK_ID 11
#endif /* _SAME70_PIOB_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PIOC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PIOC_INSTANCE_H_
#define _SAME70_PIOC_INSTANCE_H_
/* ========== Register definition for PIOC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOC_PER (0x400E1200) /**< (PIOC) PIO Enable Register */
#define REG_PIOC_PDR (0x400E1204) /**< (PIOC) PIO Disable Register */
#define REG_PIOC_PSR (0x400E1208) /**< (PIOC) PIO Status Register */
#define REG_PIOC_OER (0x400E1210) /**< (PIOC) Output Enable Register */
#define REG_PIOC_ODR (0x400E1214) /**< (PIOC) Output Disable Register */
#define REG_PIOC_OSR (0x400E1218) /**< (PIOC) Output Status Register */
#define REG_PIOC_IFER (0x400E1220) /**< (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR (0x400E1224) /**< (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR (0x400E1228) /**< (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR (0x400E1230) /**< (PIOC) Set Output Data Register */
#define REG_PIOC_CODR (0x400E1234) /**< (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR (0x400E1238) /**< (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR (0x400E123C) /**< (PIOC) Pin Data Status Register */
#define REG_PIOC_IER (0x400E1240) /**< (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR (0x400E1244) /**< (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR (0x400E1248) /**< (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR (0x400E124C) /**< (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER (0x400E1250) /**< (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR (0x400E1254) /**< (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR (0x400E1258) /**< (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR (0x400E1260) /**< (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER (0x400E1264) /**< (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR (0x400E1268) /**< (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */
#define REG_PIOC_ABCDSR0 (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */
#define REG_PIOC_ABCDSR1 (0x400E1274) /**< (PIOC) Peripheral ABCD Select Register 1 */
#define REG_PIOC_IFSCDR (0x400E1280) /**< (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER (0x400E1284) /**< (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR (0x400E1288) /**< (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR (0x400E128C) /**< (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR (0x400E1290) /**< (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER (0x400E1294) /**< (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR (0x400E1298) /**< (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER (0x400E12A0) /**< (PIOC) Output Write Enable */
#define REG_PIOC_OWDR (0x400E12A4) /**< (PIOC) Output Write Disable */
#define REG_PIOC_OWSR (0x400E12A8) /**< (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER (0x400E12B0) /**< (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR (0x400E12B4) /**< (PIOC) Additional Interrupt Modes Disable Register */
#define REG_PIOC_AIMMR (0x400E12B8) /**< (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR (0x400E12C0) /**< (PIOC) Edge Select Register */
#define REG_PIOC_LSR (0x400E12C4) /**< (PIOC) Level Select Register */
#define REG_PIOC_ELSR (0x400E12C8) /**< (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR (0x400E12D0) /**< (PIOC) Falling Edge/Low-Level Select Register */
#define REG_PIOC_REHLSR (0x400E12D4) /**< (PIOC) Rising Edge/High-Level Select Register */
#define REG_PIOC_FRLHSR (0x400E12D8) /**< (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR (0x400E12E0) /**< (PIOC) Lock Status */
#define REG_PIOC_WPMR (0x400E12E4) /**< (PIOC) Write Protection Mode Register */
#define REG_PIOC_WPSR (0x400E12E8) /**< (PIOC) Write Protection Status Register */
#define REG_PIOC_SCHMITT (0x400E1300) /**< (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DRIVER (0x400E1318) /**< (PIOC) I/O Drive Register */
#define REG_PIOC_PCMR (0x400E1350) /**< (PIOC) Parallel Capture Mode Register */
#define REG_PIOC_PCIER (0x400E1354) /**< (PIOC) Parallel Capture Interrupt Enable Register */
#define REG_PIOC_PCIDR (0x400E1358) /**< (PIOC) Parallel Capture Interrupt Disable Register */
#define REG_PIOC_PCIMR (0x400E135C) /**< (PIOC) Parallel Capture Interrupt Mask Register */
#define REG_PIOC_PCISR (0x400E1360) /**< (PIOC) Parallel Capture Interrupt Status Register */
#define REG_PIOC_PCRHR (0x400E1364) /**< (PIOC) Parallel Capture Reception Holding Register */
#else
#define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< (PIOC) PIO Enable Register */
#define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< (PIOC) PIO Disable Register */
#define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< (PIOC) PIO Status Register */
#define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< (PIOC) Output Enable Register */
#define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< (PIOC) Output Disable Register */
#define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< (PIOC) Output Status Register */
#define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< (PIOC) Set Output Data Register */
#define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< (PIOC) Pin Data Status Register */
#define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */
#define REG_PIOC_ABCDSR0 (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */
#define REG_PIOC_ABCDSR1 (*(__IO uint32_t*)0x400E1274U) /**< (PIOC) Peripheral ABCD Select Register 1 */
#define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< (PIOC) Output Write Enable */
#define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< (PIOC) Output Write Disable */
#define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< (PIOC) Additional Interrupt Modes Disable Register */
#define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< (PIOC) Edge Select Register */
#define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< (PIOC) Level Select Register */
#define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< (PIOC) Falling Edge/Low-Level Select Register */
#define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< (PIOC) Rising Edge/High-Level Select Register */
#define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< (PIOC) Lock Status */
#define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< (PIOC) Write Protection Mode Register */
#define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< (PIOC) Write Protection Status Register */
#define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< (PIOC) I/O Drive Register */
#define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< (PIOC) Parallel Capture Mode Register */
#define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< (PIOC) Parallel Capture Interrupt Enable Register */
#define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< (PIOC) Parallel Capture Interrupt Disable Register */
#define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< (PIOC) Parallel Capture Interrupt Mask Register */
#define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< (PIOC) Parallel Capture Interrupt Status Register */
#define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< (PIOC) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PIOC peripheral ========== */
#define PIOC_INSTANCE_ID 12
#define PIOC_CLOCK_ID 12
#endif /* _SAME70_PIOC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PIOD
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PIOD_INSTANCE_H_
#define _SAME70_PIOD_INSTANCE_H_
/* ========== Register definition for PIOD peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOD_PER (0x400E1400) /**< (PIOD) PIO Enable Register */
#define REG_PIOD_PDR (0x400E1404) /**< (PIOD) PIO Disable Register */
#define REG_PIOD_PSR (0x400E1408) /**< (PIOD) PIO Status Register */
#define REG_PIOD_OER (0x400E1410) /**< (PIOD) Output Enable Register */
#define REG_PIOD_ODR (0x400E1414) /**< (PIOD) Output Disable Register */
#define REG_PIOD_OSR (0x400E1418) /**< (PIOD) Output Status Register */
#define REG_PIOD_IFER (0x400E1420) /**< (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR (0x400E1424) /**< (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR (0x400E1428) /**< (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR (0x400E1430) /**< (PIOD) Set Output Data Register */
#define REG_PIOD_CODR (0x400E1434) /**< (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR (0x400E1438) /**< (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR (0x400E143C) /**< (PIOD) Pin Data Status Register */
#define REG_PIOD_IER (0x400E1440) /**< (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR (0x400E1444) /**< (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR (0x400E1448) /**< (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR (0x400E144C) /**< (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER (0x400E1450) /**< (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR (0x400E1454) /**< (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR (0x400E1458) /**< (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR (0x400E1460) /**< (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER (0x400E1464) /**< (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR (0x400E1468) /**< (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */
#define REG_PIOD_ABCDSR0 (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */
#define REG_PIOD_ABCDSR1 (0x400E1474) /**< (PIOD) Peripheral ABCD Select Register 1 */
#define REG_PIOD_IFSCDR (0x400E1480) /**< (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER (0x400E1484) /**< (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR (0x400E1488) /**< (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR (0x400E148C) /**< (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR (0x400E1490) /**< (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER (0x400E1494) /**< (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR (0x400E1498) /**< (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER (0x400E14A0) /**< (PIOD) Output Write Enable */
#define REG_PIOD_OWDR (0x400E14A4) /**< (PIOD) Output Write Disable */
#define REG_PIOD_OWSR (0x400E14A8) /**< (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER (0x400E14B0) /**< (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR (0x400E14B4) /**< (PIOD) Additional Interrupt Modes Disable Register */
#define REG_PIOD_AIMMR (0x400E14B8) /**< (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR (0x400E14C0) /**< (PIOD) Edge Select Register */
#define REG_PIOD_LSR (0x400E14C4) /**< (PIOD) Level Select Register */
#define REG_PIOD_ELSR (0x400E14C8) /**< (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR (0x400E14D0) /**< (PIOD) Falling Edge/Low-Level Select Register */
#define REG_PIOD_REHLSR (0x400E14D4) /**< (PIOD) Rising Edge/High-Level Select Register */
#define REG_PIOD_FRLHSR (0x400E14D8) /**< (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR (0x400E14E0) /**< (PIOD) Lock Status */
#define REG_PIOD_WPMR (0x400E14E4) /**< (PIOD) Write Protection Mode Register */
#define REG_PIOD_WPSR (0x400E14E8) /**< (PIOD) Write Protection Status Register */
#define REG_PIOD_SCHMITT (0x400E1500) /**< (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DRIVER (0x400E1518) /**< (PIOD) I/O Drive Register */
#define REG_PIOD_PCMR (0x400E1550) /**< (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER (0x400E1554) /**< (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR (0x400E1558) /**< (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR (0x400E155C) /**< (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR (0x400E1560) /**< (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR (0x400E1564) /**< (PIOD) Parallel Capture Reception Holding Register */
#else
#define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< (PIOD) PIO Enable Register */
#define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< (PIOD) PIO Disable Register */
#define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< (PIOD) PIO Status Register */
#define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< (PIOD) Output Enable Register */
#define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< (PIOD) Output Disable Register */
#define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< (PIOD) Output Status Register */
#define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< (PIOD) Set Output Data Register */
#define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< (PIOD) Pin Data Status Register */
#define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */
#define REG_PIOD_ABCDSR0 (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */
#define REG_PIOD_ABCDSR1 (*(__IO uint32_t*)0x400E1474U) /**< (PIOD) Peripheral ABCD Select Register 1 */
#define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< (PIOD) Output Write Enable */
#define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< (PIOD) Output Write Disable */
#define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< (PIOD) Additional Interrupt Modes Disable Register */
#define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< (PIOD) Edge Select Register */
#define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< (PIOD) Level Select Register */
#define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< (PIOD) Falling Edge/Low-Level Select Register */
#define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< (PIOD) Rising Edge/High-Level Select Register */
#define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< (PIOD) Lock Status */
#define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< (PIOD) Write Protection Mode Register */
#define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< (PIOD) Write Protection Status Register */
#define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< (PIOD) I/O Drive Register */
#define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< (PIOD) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PIOD peripheral ========== */
#define PIOD_INSTANCE_ID 16
#define PIOD_CLOCK_ID 16
#endif /* _SAME70_PIOD_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PIOE
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PIOE_INSTANCE_H_
#define _SAME70_PIOE_INSTANCE_H_
/* ========== Register definition for PIOE peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOE_PER (0x400E1600) /**< (PIOE) PIO Enable Register */
#define REG_PIOE_PDR (0x400E1604) /**< (PIOE) PIO Disable Register */
#define REG_PIOE_PSR (0x400E1608) /**< (PIOE) PIO Status Register */
#define REG_PIOE_OER (0x400E1610) /**< (PIOE) Output Enable Register */
#define REG_PIOE_ODR (0x400E1614) /**< (PIOE) Output Disable Register */
#define REG_PIOE_OSR (0x400E1618) /**< (PIOE) Output Status Register */
#define REG_PIOE_IFER (0x400E1620) /**< (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR (0x400E1624) /**< (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR (0x400E1628) /**< (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR (0x400E1630) /**< (PIOE) Set Output Data Register */
#define REG_PIOE_CODR (0x400E1634) /**< (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR (0x400E1638) /**< (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR (0x400E163C) /**< (PIOE) Pin Data Status Register */
#define REG_PIOE_IER (0x400E1640) /**< (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR (0x400E1644) /**< (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR (0x400E1648) /**< (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR (0x400E164C) /**< (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER (0x400E1650) /**< (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR (0x400E1654) /**< (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR (0x400E1658) /**< (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR (0x400E1660) /**< (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER (0x400E1664) /**< (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR (0x400E1668) /**< (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */
#define REG_PIOE_ABCDSR0 (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */
#define REG_PIOE_ABCDSR1 (0x400E1674) /**< (PIOE) Peripheral ABCD Select Register 1 */
#define REG_PIOE_IFSCDR (0x400E1680) /**< (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER (0x400E1684) /**< (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR (0x400E1688) /**< (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR (0x400E168C) /**< (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR (0x400E1690) /**< (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER (0x400E1694) /**< (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR (0x400E1698) /**< (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER (0x400E16A0) /**< (PIOE) Output Write Enable */
#define REG_PIOE_OWDR (0x400E16A4) /**< (PIOE) Output Write Disable */
#define REG_PIOE_OWSR (0x400E16A8) /**< (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Register */
#define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR (0x400E16C0) /**< (PIOE) Edge Select Register */
#define REG_PIOE_LSR (0x400E16C4) /**< (PIOE) Level Select Register */
#define REG_PIOE_ELSR (0x400E16C8) /**< (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR (0x400E16D0) /**< (PIOE) Falling Edge/Low-Level Select Register */
#define REG_PIOE_REHLSR (0x400E16D4) /**< (PIOE) Rising Edge/High-Level Select Register */
#define REG_PIOE_FRLHSR (0x400E16D8) /**< (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR (0x400E16E0) /**< (PIOE) Lock Status */
#define REG_PIOE_WPMR (0x400E16E4) /**< (PIOE) Write Protection Mode Register */
#define REG_PIOE_WPSR (0x400E16E8) /**< (PIOE) Write Protection Status Register */
#define REG_PIOE_SCHMITT (0x400E1700) /**< (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DRIVER (0x400E1718) /**< (PIOE) I/O Drive Register */
#define REG_PIOE_PCMR (0x400E1750) /**< (PIOE) Parallel Capture Mode Register */
#define REG_PIOE_PCIER (0x400E1754) /**< (PIOE) Parallel Capture Interrupt Enable Register */
#define REG_PIOE_PCIDR (0x400E1758) /**< (PIOE) Parallel Capture Interrupt Disable Register */
#define REG_PIOE_PCIMR (0x400E175C) /**< (PIOE) Parallel Capture Interrupt Mask Register */
#define REG_PIOE_PCISR (0x400E1760) /**< (PIOE) Parallel Capture Interrupt Status Register */
#define REG_PIOE_PCRHR (0x400E1764) /**< (PIOE) Parallel Capture Reception Holding Register */
#else
#define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< (PIOE) PIO Enable Register */
#define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< (PIOE) PIO Disable Register */
#define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< (PIOE) PIO Status Register */
#define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< (PIOE) Output Enable Register */
#define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< (PIOE) Output Disable Register */
#define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< (PIOE) Output Status Register */
#define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< (PIOE) Set Output Data Register */
#define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< (PIOE) Pin Data Status Register */
#define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */
#define REG_PIOE_ABCDSR0 (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */
#define REG_PIOE_ABCDSR1 (*(__IO uint32_t*)0x400E1674U) /**< (PIOE) Peripheral ABCD Select Register 1 */
#define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< (PIOE) Output Write Enable */
#define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< (PIOE) Output Write Disable */
#define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Modes Disable Register */
#define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< (PIOE) Edge Select Register */
#define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< (PIOE) Level Select Register */
#define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< (PIOE) Falling Edge/Low-Level Select Register */
#define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< (PIOE) Rising Edge/High-Level Select Register */
#define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< (PIOE) Lock Status */
#define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< (PIOE) Write Protection Mode Register */
#define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< (PIOE) Write Protection Status Register */
#define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< (PIOE) I/O Drive Register */
#define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< (PIOE) Parallel Capture Mode Register */
#define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< (PIOE) Parallel Capture Interrupt Enable Register */
#define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< (PIOE) Parallel Capture Interrupt Disable Register */
#define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< (PIOE) Parallel Capture Interrupt Mask Register */
#define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< (PIOE) Parallel Capture Interrupt Status Register */
#define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< (PIOE) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PIOE peripheral ========== */
#define PIOE_INSTANCE_ID 17
#define PIOE_CLOCK_ID 17
#endif /* _SAME70_PIOE_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PMC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PMC_INSTANCE_H_
#define _SAME70_PMC_INSTANCE_H_
/* ========== Register definition for PMC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PMC_SCER (0x400E0600) /**< (PMC) System Clock Enable Register */
#define REG_PMC_SCDR (0x400E0604) /**< (PMC) System Clock Disable Register */
#define REG_PMC_SCSR (0x400E0608) /**< (PMC) System Clock Status Register */
#define REG_PMC_PCER0 (0x400E0610) /**< (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0 (0x400E0614) /**< (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0 (0x400E0618) /**< (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_UCKR (0x400E061C) /**< (PMC) UTMI Clock Register */
#define REG_CKGR_MOR (0x400E0620) /**< (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR (0x400E0624) /**< (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR (0x400E0628) /**< (PMC) PLLA Register */
#define REG_PMC_MCKR (0x400E0630) /**< (PMC) Master Clock Register */
#define REG_PMC_USB (0x400E0638) /**< (PMC) USB Clock Register */
#define REG_PMC_PCK (0x400E0640) /**< (PMC) Programmable Clock Register */
#define REG_PMC_PCK0 (0x400E0640) /**< (PMC) Programmable Clock Register 0 */
#define REG_PMC_PCK1 (0x400E0644) /**< (PMC) Programmable Clock Register 1 */
#define REG_PMC_PCK2 (0x400E0648) /**< (PMC) Programmable Clock Register 2 */
#define REG_PMC_PCK3 (0x400E064C) /**< (PMC) Programmable Clock Register 3 */
#define REG_PMC_PCK4 (0x400E0650) /**< (PMC) Programmable Clock Register 4 */
#define REG_PMC_PCK5 (0x400E0654) /**< (PMC) Programmable Clock Register 5 */
#define REG_PMC_PCK6 (0x400E0658) /**< (PMC) Programmable Clock Register 6 */
#define REG_PMC_PCK7 (0x400E065C) /**< (PMC) Programmable Clock Register 7 */
#define REG_PMC_IER (0x400E0660) /**< (PMC) Interrupt Enable Register */
#define REG_PMC_IDR (0x400E0664) /**< (PMC) Interrupt Disable Register */
#define REG_PMC_SR (0x400E0668) /**< (PMC) Status Register */
#define REG_PMC_IMR (0x400E066C) /**< (PMC) Interrupt Mask Register */
#define REG_PMC_FSMR (0x400E0670) /**< (PMC) Fast Startup Mode Register */
#define REG_PMC_FSPR (0x400E0674) /**< (PMC) Fast Startup Polarity Register */
#define REG_PMC_FOCR (0x400E0678) /**< (PMC) Fault Output Clear Register */
#define REG_PMC_WPMR (0x400E06E4) /**< (PMC) Write Protection Mode Register */
#define REG_PMC_WPSR (0x400E06E8) /**< (PMC) Write Protection Status Register */
#define REG_PMC_PCER1 (0x400E0700) /**< (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1 (0x400E0704) /**< (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1 (0x400E0708) /**< (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_PCR (0x400E070C) /**< (PMC) Peripheral Control Register */
#define REG_PMC_OCR (0x400E0710) /**< (PMC) Oscillator Calibration Register */
#define REG_PMC_SLPWK_ER0 (0x400E0714) /**< (PMC) SleepWalking Enable Register 0 */
#define REG_PMC_SLPWK_DR0 (0x400E0718) /**< (PMC) SleepWalking Disable Register 0 */
#define REG_PMC_SLPWK_SR0 (0x400E071C) /**< (PMC) SleepWalking Status Register 0 */
#define REG_PMC_SLPWK_ASR0 (0x400E0720) /**< (PMC) SleepWalking Activity Status Register 0 */
#define REG_PMC_PMMR (0x400E0730) /**< (PMC) PLL Maximum Multiplier Value Register */
#define REG_PMC_SLPWK_ER1 (0x400E0734) /**< (PMC) SleepWalking Enable Register 1 */
#define REG_PMC_SLPWK_DR1 (0x400E0738) /**< (PMC) SleepWalking Disable Register 1 */
#define REG_PMC_SLPWK_SR1 (0x400E073C) /**< (PMC) SleepWalking Status Register 1 */
#define REG_PMC_SLPWK_ASR1 (0x400E0740) /**< (PMC) SleepWalking Activity Status Register 1 */
#define REG_PMC_SLPWK_AIPR (0x400E0744) /**< (PMC) SleepWalking Activity In Progress Register */
#else
#define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< (PMC) System Clock Enable Register */
#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< (PMC) System Clock Disable Register */
#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< (PMC) System Clock Status Register */
#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< (PMC) UTMI Clock Register */
#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< (PMC) PLLA Register */
#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< (PMC) Master Clock Register */
#define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< (PMC) USB Clock Register */
#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register */
#define REG_PMC_PCK0 (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register 0 */
#define REG_PMC_PCK1 (*(__IO uint32_t*)0x400E0644U) /**< (PMC) Programmable Clock Register 1 */
#define REG_PMC_PCK2 (*(__IO uint32_t*)0x400E0648U) /**< (PMC) Programmable Clock Register 2 */
#define REG_PMC_PCK3 (*(__IO uint32_t*)0x400E064CU) /**< (PMC) Programmable Clock Register 3 */
#define REG_PMC_PCK4 (*(__IO uint32_t*)0x400E0650U) /**< (PMC) Programmable Clock Register 4 */
#define REG_PMC_PCK5 (*(__IO uint32_t*)0x400E0654U) /**< (PMC) Programmable Clock Register 5 */
#define REG_PMC_PCK6 (*(__IO uint32_t*)0x400E0658U) /**< (PMC) Programmable Clock Register 6 */
#define REG_PMC_PCK7 (*(__IO uint32_t*)0x400E065CU) /**< (PMC) Programmable Clock Register 7 */
#define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< (PMC) Interrupt Enable Register */
#define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< (PMC) Interrupt Disable Register */
#define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< (PMC) Status Register */
#define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< (PMC) Interrupt Mask Register */
#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< (PMC) Fast Startup Mode Register */
#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< (PMC) Fast Startup Polarity Register */
#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< (PMC) Fault Output Clear Register */
#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< (PMC) Write Protection Mode Register */
#define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< (PMC) Write Protection Status Register */
#define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< (PMC) Peripheral Control Register */
#define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< (PMC) Oscillator Calibration Register */
#define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< (PMC) SleepWalking Enable Register 0 */
#define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< (PMC) SleepWalking Disable Register 0 */
#define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< (PMC) SleepWalking Status Register 0 */
#define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< (PMC) SleepWalking Activity Status Register 0 */
#define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< (PMC) PLL Maximum Multiplier Value Register */
#define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< (PMC) SleepWalking Enable Register 1 */
#define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< (PMC) SleepWalking Disable Register 1 */
#define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< (PMC) SleepWalking Status Register 1 */
#define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< (PMC) SleepWalking Activity Status Register 1 */
#define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< (PMC) SleepWalking Activity In Progress Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PMC peripheral ========== */
#define PMC_INSTANCE_ID 5
#endif /* _SAME70_PMC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PWM0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PWM0_INSTANCE_H_
#define _SAME70_PWM0_INSTANCE_H_
/* ========== Register definition for PWM0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PWM0_CMPV0 (0x40020130) /**< (PWM0) PWM Comparison 0 Value Register 0 */
#define REG_PWM0_CMPVUPD0 (0x40020134) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */
#define REG_PWM0_CMPM0 (0x40020138) /**< (PWM0) PWM Comparison 0 Mode Register 0 */
#define REG_PWM0_CMPMUPD0 (0x4002013C) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */
#define REG_PWM0_CMPV1 (0x40020140) /**< (PWM0) PWM Comparison 0 Value Register 1 */
#define REG_PWM0_CMPVUPD1 (0x40020144) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */
#define REG_PWM0_CMPM1 (0x40020148) /**< (PWM0) PWM Comparison 0 Mode Register 1 */
#define REG_PWM0_CMPMUPD1 (0x4002014C) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */
#define REG_PWM0_CMPV2 (0x40020150) /**< (PWM0) PWM Comparison 0 Value Register 2 */
#define REG_PWM0_CMPVUPD2 (0x40020154) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */
#define REG_PWM0_CMPM2 (0x40020158) /**< (PWM0) PWM Comparison 0 Mode Register 2 */
#define REG_PWM0_CMPMUPD2 (0x4002015C) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */
#define REG_PWM0_CMPV3 (0x40020160) /**< (PWM0) PWM Comparison 0 Value Register 3 */
#define REG_PWM0_CMPVUPD3 (0x40020164) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */
#define REG_PWM0_CMPM3 (0x40020168) /**< (PWM0) PWM Comparison 0 Mode Register 3 */
#define REG_PWM0_CMPMUPD3 (0x4002016C) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */
#define REG_PWM0_CMPV4 (0x40020170) /**< (PWM0) PWM Comparison 0 Value Register 4 */
#define REG_PWM0_CMPVUPD4 (0x40020174) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */
#define REG_PWM0_CMPM4 (0x40020178) /**< (PWM0) PWM Comparison 0 Mode Register 4 */
#define REG_PWM0_CMPMUPD4 (0x4002017C) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */
#define REG_PWM0_CMPV5 (0x40020180) /**< (PWM0) PWM Comparison 0 Value Register 5 */
#define REG_PWM0_CMPVUPD5 (0x40020184) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */
#define REG_PWM0_CMPM5 (0x40020188) /**< (PWM0) PWM Comparison 0 Mode Register 5 */
#define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */
#define REG_PWM0_CMPV6 (0x40020190) /**< (PWM0) PWM Comparison 0 Value Register 6 */
#define REG_PWM0_CMPVUPD6 (0x40020194) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */
#define REG_PWM0_CMPM6 (0x40020198) /**< (PWM0) PWM Comparison 0 Mode Register 6 */
#define REG_PWM0_CMPMUPD6 (0x4002019C) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */
#define REG_PWM0_CMPV7 (0x400201A0) /**< (PWM0) PWM Comparison 0 Value Register 7 */
#define REG_PWM0_CMPVUPD7 (0x400201A4) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */
#define REG_PWM0_CMPM7 (0x400201A8) /**< (PWM0) PWM Comparison 0 Mode Register 7 */
#define REG_PWM0_CMPMUPD7 (0x400201AC) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */
#define REG_PWM0_CMR0 (0x40020200) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 0 */
#define REG_PWM0_CDTY0 (0x40020204) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 0 */
#define REG_PWM0_CDTYUPD0 (0x40020208) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */
#define REG_PWM0_CPRD0 (0x4002020C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 0 */
#define REG_PWM0_CPRDUPD0 (0x40020210) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 0 */
#define REG_PWM0_CCNT0 (0x40020214) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 0 */
#define REG_PWM0_DT0 (0x40020218) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 0 */
#define REG_PWM0_DTUPD0 (0x4002021C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 0 */
#define REG_PWM0_CMR1 (0x40020220) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 1 */
#define REG_PWM0_CDTY1 (0x40020224) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 1 */
#define REG_PWM0_CDTYUPD1 (0x40020228) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */
#define REG_PWM0_CPRD1 (0x4002022C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 1 */
#define REG_PWM0_CPRDUPD1 (0x40020230) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 1 */
#define REG_PWM0_CCNT1 (0x40020234) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 1 */
#define REG_PWM0_DT1 (0x40020238) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 1 */
#define REG_PWM0_DTUPD1 (0x4002023C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 1 */
#define REG_PWM0_CMR2 (0x40020240) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 2 */
#define REG_PWM0_CDTY2 (0x40020244) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 2 */
#define REG_PWM0_CDTYUPD2 (0x40020248) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */
#define REG_PWM0_CPRD2 (0x4002024C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 2 */
#define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 2 */
#define REG_PWM0_CCNT2 (0x40020254) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 2 */
#define REG_PWM0_DT2 (0x40020258) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 2 */
#define REG_PWM0_DTUPD2 (0x4002025C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 2 */
#define REG_PWM0_CMR3 (0x40020260) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 3 */
#define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 3 */
#define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */
#define REG_PWM0_CPRD3 (0x4002026C) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 3 */
#define REG_PWM0_CPRDUPD3 (0x40020270) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 3 */
#define REG_PWM0_CCNT3 (0x40020274) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 3 */
#define REG_PWM0_DT3 (0x40020278) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 3 */
#define REG_PWM0_DTUPD3 (0x4002027C) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 3 */
#define REG_PWM0_CLK (0x40020000) /**< (PWM0) PWM Clock Register */
#define REG_PWM0_ENA (0x40020004) /**< (PWM0) PWM Enable Register */
#define REG_PWM0_DIS (0x40020008) /**< (PWM0) PWM Disable Register */
#define REG_PWM0_SR (0x4002000C) /**< (PWM0) PWM Status Register */
#define REG_PWM0_IER1 (0x40020010) /**< (PWM0) PWM Interrupt Enable Register 1 */
#define REG_PWM0_IDR1 (0x40020014) /**< (PWM0) PWM Interrupt Disable Register 1 */
#define REG_PWM0_IMR1 (0x40020018) /**< (PWM0) PWM Interrupt Mask Register 1 */
#define REG_PWM0_ISR1 (0x4002001C) /**< (PWM0) PWM Interrupt Status Register 1 */
#define REG_PWM0_SCM (0x40020020) /**< (PWM0) PWM Sync Channels Mode Register */
#define REG_PWM0_DMAR (0x40020024) /**< (PWM0) PWM DMA Register */
#define REG_PWM0_SCUC (0x40020028) /**< (PWM0) PWM Sync Channels Update Control Register */
#define REG_PWM0_SCUP (0x4002002C) /**< (PWM0) PWM Sync Channels Update Period Register */
#define REG_PWM0_SCUPUPD (0x40020030) /**< (PWM0) PWM Sync Channels Update Period Update Register */
#define REG_PWM0_IER2 (0x40020034) /**< (PWM0) PWM Interrupt Enable Register 2 */
#define REG_PWM0_IDR2 (0x40020038) /**< (PWM0) PWM Interrupt Disable Register 2 */
#define REG_PWM0_IMR2 (0x4002003C) /**< (PWM0) PWM Interrupt Mask Register 2 */
#define REG_PWM0_ISR2 (0x40020040) /**< (PWM0) PWM Interrupt Status Register 2 */
#define REG_PWM0_OOV (0x40020044) /**< (PWM0) PWM Output Override Value Register */
#define REG_PWM0_OS (0x40020048) /**< (PWM0) PWM Output Selection Register */
#define REG_PWM0_OSS (0x4002004C) /**< (PWM0) PWM Output Selection Set Register */
#define REG_PWM0_OSC (0x40020050) /**< (PWM0) PWM Output Selection Clear Register */
#define REG_PWM0_OSSUPD (0x40020054) /**< (PWM0) PWM Output Selection Set Update Register */
#define REG_PWM0_OSCUPD (0x40020058) /**< (PWM0) PWM Output Selection Clear Update Register */
#define REG_PWM0_FMR (0x4002005C) /**< (PWM0) PWM Fault Mode Register */
#define REG_PWM0_FSR (0x40020060) /**< (PWM0) PWM Fault Status Register */
#define REG_PWM0_FCR (0x40020064) /**< (PWM0) PWM Fault Clear Register */
#define REG_PWM0_FPV1 (0x40020068) /**< (PWM0) PWM Fault Protection Value Register 1 */
#define REG_PWM0_FPE (0x4002006C) /**< (PWM0) PWM Fault Protection Enable Register */
#define REG_PWM0_ELMR (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
#define REG_PWM0_ELMR0 (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
#define REG_PWM0_ELMR1 (0x40020080) /**< (PWM0) PWM Event Line 0 Mode Register 1 */
#define REG_PWM0_SSPR (0x400200A0) /**< (PWM0) PWM Spread Spectrum Register */
#define REG_PWM0_SSPUP (0x400200A4) /**< (PWM0) PWM Spread Spectrum Update Register */
#define REG_PWM0_SMMR (0x400200B0) /**< (PWM0) PWM Stepper Motor Mode Register */
#define REG_PWM0_FPV2 (0x400200C0) /**< (PWM0) PWM Fault Protection Value 2 Register */
#define REG_PWM0_WPCR (0x400200E4) /**< (PWM0) PWM Write Protection Control Register */
#define REG_PWM0_WPSR (0x400200E8) /**< (PWM0) PWM Write Protection Status Register */
#define REG_PWM0_CMUPD0 (0x40020400) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM0_CMUPD1 (0x40020420) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM0_ETRG1 (0x4002042C) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */
#define REG_PWM0_LEBR1 (0x40020430) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
#define REG_PWM0_CMUPD2 (0x40020440) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM0_ETRG2 (0x4002044C) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */
#define REG_PWM0_LEBR2 (0x40020450) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
#define REG_PWM0_CMUPD3 (0x40020460) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
#else
#define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< (PWM0) PWM Comparison 0 Value Register 0 */
#define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */
#define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< (PWM0) PWM Comparison 0 Mode Register 0 */
#define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */
#define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< (PWM0) PWM Comparison 0 Value Register 1 */
#define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */
#define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< (PWM0) PWM Comparison 0 Mode Register 1 */
#define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */
#define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< (PWM0) PWM Comparison 0 Value Register 2 */
#define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */
#define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< (PWM0) PWM Comparison 0 Mode Register 2 */
#define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */
#define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< (PWM0) PWM Comparison 0 Value Register 3 */
#define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */
#define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< (PWM0) PWM Comparison 0 Mode Register 3 */
#define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */
#define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< (PWM0) PWM Comparison 0 Value Register 4 */
#define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */
#define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< (PWM0) PWM Comparison 0 Mode Register 4 */
#define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */
#define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< (PWM0) PWM Comparison 0 Value Register 5 */
#define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */
#define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< (PWM0) PWM Comparison 0 Mode Register 5 */
#define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */
#define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< (PWM0) PWM Comparison 0 Value Register 6 */
#define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */
#define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< (PWM0) PWM Comparison 0 Mode Register 6 */
#define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */
#define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< (PWM0) PWM Comparison 0 Value Register 7 */
#define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */
#define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< (PWM0) PWM Comparison 0 Mode Register 7 */
#define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */
#define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 0 */
#define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 0 */
#define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */
#define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 0 */
#define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 0 */
#define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 0 */
#define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 0 */
#define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 0 */
#define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 1 */
#define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 1 */
#define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */
#define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 1 */
#define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 1 */
#define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 1 */
#define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 1 */
#define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 1 */
#define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 2 */
#define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 2 */
#define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */
#define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 2 */
#define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 2 */
#define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 2 */
#define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 2 */
#define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 2 */
#define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< (PWM0) PWM Channel Mode Register (ch_num = 0) 3 */
#define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) 3 */
#define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */
#define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< (PWM0) PWM Channel Period Register (ch_num = 0) 3 */
#define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< (PWM0) PWM Channel Period Update Register (ch_num = 0) 3 */
#define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< (PWM0) PWM Channel Counter Register (ch_num = 0) 3 */
#define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< (PWM0) PWM Channel Dead Time Register (ch_num = 0) 3 */
#define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) 3 */
#define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< (PWM0) PWM Clock Register */
#define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< (PWM0) PWM Enable Register */
#define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< (PWM0) PWM Disable Register */
#define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< (PWM0) PWM Status Register */
#define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< (PWM0) PWM Interrupt Enable Register 1 */
#define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< (PWM0) PWM Interrupt Disable Register 1 */
#define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< (PWM0) PWM Interrupt Mask Register 1 */
#define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< (PWM0) PWM Interrupt Status Register 1 */
#define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< (PWM0) PWM Sync Channels Mode Register */
#define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< (PWM0) PWM DMA Register */
#define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< (PWM0) PWM Sync Channels Update Control Register */
#define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< (PWM0) PWM Sync Channels Update Period Register */
#define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< (PWM0) PWM Sync Channels Update Period Update Register */
#define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< (PWM0) PWM Interrupt Enable Register 2 */
#define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< (PWM0) PWM Interrupt Disable Register 2 */
#define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< (PWM0) PWM Interrupt Mask Register 2 */
#define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< (PWM0) PWM Interrupt Status Register 2 */
#define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< (PWM0) PWM Output Override Value Register */
#define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< (PWM0) PWM Output Selection Register */
#define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< (PWM0) PWM Output Selection Set Register */
#define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< (PWM0) PWM Output Selection Clear Register */
#define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< (PWM0) PWM Output Selection Set Update Register */
#define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< (PWM0) PWM Output Selection Clear Update Register */
#define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< (PWM0) PWM Fault Mode Register */
#define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< (PWM0) PWM Fault Status Register */
#define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< (PWM0) PWM Fault Clear Register */
#define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< (PWM0) PWM Fault Protection Value Register 1 */
#define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< (PWM0) PWM Fault Protection Enable Register */
#define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
#define REG_PWM0_ELMR0 (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
#define REG_PWM0_ELMR1 (*(__IO uint32_t*)0x40020080U) /**< (PWM0) PWM Event Line 0 Mode Register 1 */
#define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< (PWM0) PWM Spread Spectrum Register */
#define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< (PWM0) PWM Spread Spectrum Update Register */
#define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< (PWM0) PWM Stepper Motor Mode Register */
#define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< (PWM0) PWM Fault Protection Value 2 Register */
#define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< (PWM0) PWM Write Protection Control Register */
#define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< (PWM0) PWM Write Protection Status Register */
#define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */
#define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
#define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */
#define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
#define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PWM0 peripheral ========== */
#define PWM0_INSTANCE_ID 31
#define PWM0_CLOCK_ID 31
#define PWM0_DMAC_ID_TX 13
#endif /* _SAME70_PWM0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PWM1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_PWM1_INSTANCE_H_
#define _SAME70_PWM1_INSTANCE_H_
/* ========== Register definition for PWM1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PWM1_CMPV0 (0x4005C130) /**< (PWM1) PWM Comparison 0 Value Register 0 */
#define REG_PWM1_CMPVUPD0 (0x4005C134) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */
#define REG_PWM1_CMPM0 (0x4005C138) /**< (PWM1) PWM Comparison 0 Mode Register 0 */
#define REG_PWM1_CMPMUPD0 (0x4005C13C) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */
#define REG_PWM1_CMPV1 (0x4005C140) /**< (PWM1) PWM Comparison 0 Value Register 1 */
#define REG_PWM1_CMPVUPD1 (0x4005C144) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */
#define REG_PWM1_CMPM1 (0x4005C148) /**< (PWM1) PWM Comparison 0 Mode Register 1 */
#define REG_PWM1_CMPMUPD1 (0x4005C14C) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */
#define REG_PWM1_CMPV2 (0x4005C150) /**< (PWM1) PWM Comparison 0 Value Register 2 */
#define REG_PWM1_CMPVUPD2 (0x4005C154) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */
#define REG_PWM1_CMPM2 (0x4005C158) /**< (PWM1) PWM Comparison 0 Mode Register 2 */
#define REG_PWM1_CMPMUPD2 (0x4005C15C) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */
#define REG_PWM1_CMPV3 (0x4005C160) /**< (PWM1) PWM Comparison 0 Value Register 3 */
#define REG_PWM1_CMPVUPD3 (0x4005C164) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */
#define REG_PWM1_CMPM3 (0x4005C168) /**< (PWM1) PWM Comparison 0 Mode Register 3 */
#define REG_PWM1_CMPMUPD3 (0x4005C16C) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */
#define REG_PWM1_CMPV4 (0x4005C170) /**< (PWM1) PWM Comparison 0 Value Register 4 */
#define REG_PWM1_CMPVUPD4 (0x4005C174) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */
#define REG_PWM1_CMPM4 (0x4005C178) /**< (PWM1) PWM Comparison 0 Mode Register 4 */
#define REG_PWM1_CMPMUPD4 (0x4005C17C) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */
#define REG_PWM1_CMPV5 (0x4005C180) /**< (PWM1) PWM Comparison 0 Value Register 5 */
#define REG_PWM1_CMPVUPD5 (0x4005C184) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */
#define REG_PWM1_CMPM5 (0x4005C188) /**< (PWM1) PWM Comparison 0 Mode Register 5 */
#define REG_PWM1_CMPMUPD5 (0x4005C18C) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */
#define REG_PWM1_CMPV6 (0x4005C190) /**< (PWM1) PWM Comparison 0 Value Register 6 */
#define REG_PWM1_CMPVUPD6 (0x4005C194) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */
#define REG_PWM1_CMPM6 (0x4005C198) /**< (PWM1) PWM Comparison 0 Mode Register 6 */
#define REG_PWM1_CMPMUPD6 (0x4005C19C) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */
#define REG_PWM1_CMPV7 (0x4005C1A0) /**< (PWM1) PWM Comparison 0 Value Register 7 */
#define REG_PWM1_CMPVUPD7 (0x4005C1A4) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */
#define REG_PWM1_CMPM7 (0x4005C1A8) /**< (PWM1) PWM Comparison 0 Mode Register 7 */
#define REG_PWM1_CMPMUPD7 (0x4005C1AC) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */
#define REG_PWM1_CMR0 (0x4005C200) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 0 */
#define REG_PWM1_CDTY0 (0x4005C204) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 0 */
#define REG_PWM1_CDTYUPD0 (0x4005C208) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */
#define REG_PWM1_CPRD0 (0x4005C20C) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 0 */
#define REG_PWM1_CPRDUPD0 (0x4005C210) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 0 */
#define REG_PWM1_CCNT0 (0x4005C214) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 0 */
#define REG_PWM1_DT0 (0x4005C218) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 0 */
#define REG_PWM1_DTUPD0 (0x4005C21C) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 0 */
#define REG_PWM1_CMR1 (0x4005C220) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 1 */
#define REG_PWM1_CDTY1 (0x4005C224) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 1 */
#define REG_PWM1_CDTYUPD1 (0x4005C228) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */
#define REG_PWM1_CPRD1 (0x4005C22C) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 1 */
#define REG_PWM1_CPRDUPD1 (0x4005C230) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 1 */
#define REG_PWM1_CCNT1 (0x4005C234) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 1 */
#define REG_PWM1_DT1 (0x4005C238) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 1 */
#define REG_PWM1_DTUPD1 (0x4005C23C) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 1 */
#define REG_PWM1_CMR2 (0x4005C240) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 2 */
#define REG_PWM1_CDTY2 (0x4005C244) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 2 */
#define REG_PWM1_CDTYUPD2 (0x4005C248) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */
#define REG_PWM1_CPRD2 (0x4005C24C) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 2 */
#define REG_PWM1_CPRDUPD2 (0x4005C250) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 2 */
#define REG_PWM1_CCNT2 (0x4005C254) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 2 */
#define REG_PWM1_DT2 (0x4005C258) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 2 */
#define REG_PWM1_DTUPD2 (0x4005C25C) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 2 */
#define REG_PWM1_CMR3 (0x4005C260) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 3 */
#define REG_PWM1_CDTY3 (0x4005C264) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 3 */
#define REG_PWM1_CDTYUPD3 (0x4005C268) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */
#define REG_PWM1_CPRD3 (0x4005C26C) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 3 */
#define REG_PWM1_CPRDUPD3 (0x4005C270) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 3 */
#define REG_PWM1_CCNT3 (0x4005C274) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 3 */
#define REG_PWM1_DT3 (0x4005C278) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 3 */
#define REG_PWM1_DTUPD3 (0x4005C27C) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 3 */
#define REG_PWM1_CLK (0x4005C000) /**< (PWM1) PWM Clock Register */
#define REG_PWM1_ENA (0x4005C004) /**< (PWM1) PWM Enable Register */
#define REG_PWM1_DIS (0x4005C008) /**< (PWM1) PWM Disable Register */
#define REG_PWM1_SR (0x4005C00C) /**< (PWM1) PWM Status Register */
#define REG_PWM1_IER1 (0x4005C010) /**< (PWM1) PWM Interrupt Enable Register 1 */
#define REG_PWM1_IDR1 (0x4005C014) /**< (PWM1) PWM Interrupt Disable Register 1 */
#define REG_PWM1_IMR1 (0x4005C018) /**< (PWM1) PWM Interrupt Mask Register 1 */
#define REG_PWM1_ISR1 (0x4005C01C) /**< (PWM1) PWM Interrupt Status Register 1 */
#define REG_PWM1_SCM (0x4005C020) /**< (PWM1) PWM Sync Channels Mode Register */
#define REG_PWM1_DMAR (0x4005C024) /**< (PWM1) PWM DMA Register */
#define REG_PWM1_SCUC (0x4005C028) /**< (PWM1) PWM Sync Channels Update Control Register */
#define REG_PWM1_SCUP (0x4005C02C) /**< (PWM1) PWM Sync Channels Update Period Register */
#define REG_PWM1_SCUPUPD (0x4005C030) /**< (PWM1) PWM Sync Channels Update Period Update Register */
#define REG_PWM1_IER2 (0x4005C034) /**< (PWM1) PWM Interrupt Enable Register 2 */
#define REG_PWM1_IDR2 (0x4005C038) /**< (PWM1) PWM Interrupt Disable Register 2 */
#define REG_PWM1_IMR2 (0x4005C03C) /**< (PWM1) PWM Interrupt Mask Register 2 */
#define REG_PWM1_ISR2 (0x4005C040) /**< (PWM1) PWM Interrupt Status Register 2 */
#define REG_PWM1_OOV (0x4005C044) /**< (PWM1) PWM Output Override Value Register */
#define REG_PWM1_OS (0x4005C048) /**< (PWM1) PWM Output Selection Register */
#define REG_PWM1_OSS (0x4005C04C) /**< (PWM1) PWM Output Selection Set Register */
#define REG_PWM1_OSC (0x4005C050) /**< (PWM1) PWM Output Selection Clear Register */
#define REG_PWM1_OSSUPD (0x4005C054) /**< (PWM1) PWM Output Selection Set Update Register */
#define REG_PWM1_OSCUPD (0x4005C058) /**< (PWM1) PWM Output Selection Clear Update Register */
#define REG_PWM1_FMR (0x4005C05C) /**< (PWM1) PWM Fault Mode Register */
#define REG_PWM1_FSR (0x4005C060) /**< (PWM1) PWM Fault Status Register */
#define REG_PWM1_FCR (0x4005C064) /**< (PWM1) PWM Fault Clear Register */
#define REG_PWM1_FPV1 (0x4005C068) /**< (PWM1) PWM Fault Protection Value Register 1 */
#define REG_PWM1_FPE (0x4005C06C) /**< (PWM1) PWM Fault Protection Enable Register */
#define REG_PWM1_ELMR (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
#define REG_PWM1_ELMR0 (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
#define REG_PWM1_ELMR1 (0x4005C080) /**< (PWM1) PWM Event Line 0 Mode Register 1 */
#define REG_PWM1_SSPR (0x4005C0A0) /**< (PWM1) PWM Spread Spectrum Register */
#define REG_PWM1_SSPUP (0x4005C0A4) /**< (PWM1) PWM Spread Spectrum Update Register */
#define REG_PWM1_SMMR (0x4005C0B0) /**< (PWM1) PWM Stepper Motor Mode Register */
#define REG_PWM1_FPV2 (0x4005C0C0) /**< (PWM1) PWM Fault Protection Value 2 Register */
#define REG_PWM1_WPCR (0x4005C0E4) /**< (PWM1) PWM Write Protection Control Register */
#define REG_PWM1_WPSR (0x4005C0E8) /**< (PWM1) PWM Write Protection Status Register */
#define REG_PWM1_CMUPD0 (0x4005C400) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM1_CMUPD1 (0x4005C420) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM1_ETRG1 (0x4005C42C) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */
#define REG_PWM1_LEBR1 (0x4005C430) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
#define REG_PWM1_CMUPD2 (0x4005C440) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM1_ETRG2 (0x4005C44C) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */
#define REG_PWM1_LEBR2 (0x4005C450) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
#define REG_PWM1_CMUPD3 (0x4005C460) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
#else
#define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< (PWM1) PWM Comparison 0 Value Register 0 */
#define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */
#define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< (PWM1) PWM Comparison 0 Mode Register 0 */
#define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */
#define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< (PWM1) PWM Comparison 0 Value Register 1 */
#define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */
#define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< (PWM1) PWM Comparison 0 Mode Register 1 */
#define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */
#define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< (PWM1) PWM Comparison 0 Value Register 2 */
#define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */
#define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< (PWM1) PWM Comparison 0 Mode Register 2 */
#define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */
#define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< (PWM1) PWM Comparison 0 Value Register 3 */
#define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */
#define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< (PWM1) PWM Comparison 0 Mode Register 3 */
#define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */
#define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< (PWM1) PWM Comparison 0 Value Register 4 */
#define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */
#define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< (PWM1) PWM Comparison 0 Mode Register 4 */
#define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */
#define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< (PWM1) PWM Comparison 0 Value Register 5 */
#define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */
#define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< (PWM1) PWM Comparison 0 Mode Register 5 */
#define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */
#define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< (PWM1) PWM Comparison 0 Value Register 6 */
#define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */
#define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< (PWM1) PWM Comparison 0 Mode Register 6 */
#define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */
#define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< (PWM1) PWM Comparison 0 Value Register 7 */
#define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */
#define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< (PWM1) PWM Comparison 0 Mode Register 7 */
#define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */
#define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 0 */
#define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 0 */
#define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 0 */
#define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 0 */
#define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 0 */
#define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 0 */
#define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 0 */
#define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 0 */
#define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 1 */
#define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 1 */
#define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 1 */
#define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 1 */
#define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 1 */
#define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 1 */
#define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 1 */
#define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 1 */
#define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 2 */
#define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 2 */
#define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 2 */
#define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 2 */
#define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 2 */
#define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 2 */
#define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 2 */
#define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 2 */
#define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< (PWM1) PWM Channel Mode Register (ch_num = 0) 3 */
#define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) 3 */
#define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) 3 */
#define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< (PWM1) PWM Channel Period Register (ch_num = 0) 3 */
#define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< (PWM1) PWM Channel Period Update Register (ch_num = 0) 3 */
#define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< (PWM1) PWM Channel Counter Register (ch_num = 0) 3 */
#define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< (PWM1) PWM Channel Dead Time Register (ch_num = 0) 3 */
#define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) 3 */
#define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< (PWM1) PWM Clock Register */
#define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< (PWM1) PWM Enable Register */
#define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< (PWM1) PWM Disable Register */
#define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< (PWM1) PWM Status Register */
#define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< (PWM1) PWM Interrupt Enable Register 1 */
#define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< (PWM1) PWM Interrupt Disable Register 1 */
#define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< (PWM1) PWM Interrupt Mask Register 1 */
#define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< (PWM1) PWM Interrupt Status Register 1 */
#define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< (PWM1) PWM Sync Channels Mode Register */
#define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< (PWM1) PWM DMA Register */
#define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< (PWM1) PWM Sync Channels Update Control Register */
#define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< (PWM1) PWM Sync Channels Update Period Register */
#define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< (PWM1) PWM Sync Channels Update Period Update Register */
#define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< (PWM1) PWM Interrupt Enable Register 2 */
#define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< (PWM1) PWM Interrupt Disable Register 2 */
#define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< (PWM1) PWM Interrupt Mask Register 2 */
#define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< (PWM1) PWM Interrupt Status Register 2 */
#define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< (PWM1) PWM Output Override Value Register */
#define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< (PWM1) PWM Output Selection Register */
#define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< (PWM1) PWM Output Selection Set Register */
#define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< (PWM1) PWM Output Selection Clear Register */
#define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< (PWM1) PWM Output Selection Set Update Register */
#define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< (PWM1) PWM Output Selection Clear Update Register */
#define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< (PWM1) PWM Fault Mode Register */
#define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< (PWM1) PWM Fault Status Register */
#define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< (PWM1) PWM Fault Clear Register */
#define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< (PWM1) PWM Fault Protection Value Register 1 */
#define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< (PWM1) PWM Fault Protection Enable Register */
#define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
#define REG_PWM1_ELMR0 (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
#define REG_PWM1_ELMR1 (*(__IO uint32_t*)0x4005C080U) /**< (PWM1) PWM Event Line 0 Mode Register 1 */
#define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< (PWM1) PWM Spread Spectrum Register */
#define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< (PWM1) PWM Spread Spectrum Update Register */
#define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< (PWM1) PWM Stepper Motor Mode Register */
#define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< (PWM1) PWM Fault Protection Value 2 Register */
#define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< (PWM1) PWM Write Protection Control Register */
#define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< (PWM1) PWM Write Protection Status Register */
#define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */
#define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
#define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */
#define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
#define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for PWM1 peripheral ========== */
#define PWM1_INSTANCE_ID 60
#define PWM1_CLOCK_ID 60
#define PWM1_DMAC_ID_TX 39
#endif /* _SAME70_PWM1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for QSPI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_QSPI_INSTANCE_H_
#define _SAME70_QSPI_INSTANCE_H_
/* ========== Register definition for QSPI peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_QSPI_CR (0x4007C000) /**< (QSPI) Control Register */
#define REG_QSPI_MR (0x4007C004) /**< (QSPI) Mode Register */
#define REG_QSPI_RDR (0x4007C008) /**< (QSPI) Receive Data Register */
#define REG_QSPI_TDR (0x4007C00C) /**< (QSPI) Transmit Data Register */
#define REG_QSPI_SR (0x4007C010) /**< (QSPI) Status Register */
#define REG_QSPI_IER (0x4007C014) /**< (QSPI) Interrupt Enable Register */
#define REG_QSPI_IDR (0x4007C018) /**< (QSPI) Interrupt Disable Register */
#define REG_QSPI_IMR (0x4007C01C) /**< (QSPI) Interrupt Mask Register */
#define REG_QSPI_SCR (0x4007C020) /**< (QSPI) Serial Clock Register */
#define REG_QSPI_IAR (0x4007C030) /**< (QSPI) Instruction Address Register */
#define REG_QSPI_ICR (0x4007C034) /**< (QSPI) Instruction Code Register */
#define REG_QSPI_IFR (0x4007C038) /**< (QSPI) Instruction Frame Register */
#define REG_QSPI_SMR (0x4007C040) /**< (QSPI) Scrambling Mode Register */
#define REG_QSPI_SKR (0x4007C044) /**< (QSPI) Scrambling Key Register */
#define REG_QSPI_WPMR (0x4007C0E4) /**< (QSPI) Write Protection Mode Register */
#define REG_QSPI_WPSR (0x4007C0E8) /**< (QSPI) Write Protection Status Register */
#else
#define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */
#define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< (QSPI) Mode Register */
#define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< (QSPI) Receive Data Register */
#define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */
#define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< (QSPI) Status Register */
#define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Register */
#define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Register */
#define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< (QSPI) Interrupt Mask Register */
#define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< (QSPI) Serial Clock Register */
#define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< (QSPI) Instruction Address Register */
#define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< (QSPI) Instruction Code Register */
#define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< (QSPI) Instruction Frame Register */
#define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< (QSPI) Scrambling Mode Register */
#define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register */
#define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< (QSPI) Write Protection Mode Register */
#define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< (QSPI) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for QSPI peripheral ========== */
#define QSPI_INSTANCE_ID 43
#define QSPI_CLOCK_ID 43
#define QSPI_DMAC_ID_TX 5
#define QSPI_DMAC_ID_RX 6
#endif /* _SAME70_QSPI_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RSTC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RSTC_INSTANCE_H_
#define _SAME70_RSTC_INSTANCE_H_
/* ========== Register definition for RSTC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSTC_CR (0x400E1800) /**< (RSTC) Control Register */
#define REG_RSTC_SR (0x400E1804) /**< (RSTC) Status Register */
#define REG_RSTC_MR (0x400E1808) /**< (RSTC) Mode Register */
#else
#define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< (RSTC) Control Register */
#define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< (RSTC) Status Register */
#define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< (RSTC) Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for RSTC peripheral ========== */
#define RSTC_INSTANCE_ID 1
#endif /* _SAME70_RSTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RSWDT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RSWDT_INSTANCE_H_
#define _SAME70_RSWDT_INSTANCE_H_
/* ========== Register definition for RSWDT peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSWDT_CR (0x400E1900) /**< (RSWDT) Control Register */
#define REG_RSWDT_MR (0x400E1904) /**< (RSWDT) Mode Register */
#define REG_RSWDT_SR (0x400E1908) /**< (RSWDT) Status Register */
#else
#define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< (RSWDT) Control Register */
#define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< (RSWDT) Mode Register */
#define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< (RSWDT) Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for RSWDT peripheral ========== */
#define RSWDT_INSTANCE_ID 63
#endif /* _SAME70_RSWDT_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RTC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RTC_INSTANCE_H_
#define _SAME70_RTC_INSTANCE_H_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_CR (0x400E1860) /**< (RTC) Control Register */
#define REG_RTC_MR (0x400E1864) /**< (RTC) Mode Register */
#define REG_RTC_TIMR (0x400E1868) /**< (RTC) Time Register */
#define REG_RTC_CALR (0x400E186C) /**< (RTC) Calendar Register */
#define REG_RTC_TIMALR (0x400E1870) /**< (RTC) Time Alarm Register */
#define REG_RTC_CALALR (0x400E1874) /**< (RTC) Calendar Alarm Register */
#define REG_RTC_SR (0x400E1878) /**< (RTC) Status Register */
#define REG_RTC_SCCR (0x400E187C) /**< (RTC) Status Clear Command Register */
#define REG_RTC_IER (0x400E1880) /**< (RTC) Interrupt Enable Register */
#define REG_RTC_IDR (0x400E1884) /**< (RTC) Interrupt Disable Register */
#define REG_RTC_IMR (0x400E1888) /**< (RTC) Interrupt Mask Register */
#define REG_RTC_VER (0x400E188C) /**< (RTC) Valid Entry Register */
#define REG_RTC_WPMR (0x400E1944) /**< (RTC) Write Protection Mode Register */
#else
#define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< (RTC) Control Register */
#define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< (RTC) Mode Register */
#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< (RTC) Time Register */
#define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< (RTC) Calendar Register */
#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< (RTC) Time Alarm Register */
#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< (RTC) Calendar Alarm Register */
#define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< (RTC) Status Register */
#define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< (RTC) Status Clear Command Register */
#define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< (RTC) Interrupt Enable Register */
#define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< (RTC) Interrupt Disable Register */
#define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< (RTC) Interrupt Mask Register */
#define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< (RTC) Valid Entry Register */
#define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< (RTC) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for RTC peripheral ========== */
#define RTC_INSTANCE_ID 2
#endif /* _SAME70_RTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RTT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_RTT_INSTANCE_H_
#define _SAME70_RTT_INSTANCE_H_
/* ========== Register definition for RTT peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTT_MR (0x400E1830) /**< (RTT) Mode Register */
#define REG_RTT_AR (0x400E1834) /**< (RTT) Alarm Register */
#define REG_RTT_VR (0x400E1838) /**< (RTT) Value Register */
#define REG_RTT_SR (0x400E183C) /**< (RTT) Status Register */
#else
#define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< (RTT) Mode Register */
#define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< (RTT) Alarm Register */
#define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< (RTT) Value Register */
#define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< (RTT) Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for RTT peripheral ========== */
#define RTT_INSTANCE_ID 3
#endif /* _SAME70_RTT_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SDRAMC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SDRAMC_INSTANCE_H_
#define _SAME70_SDRAMC_INSTANCE_H_
/* ========== Register definition for SDRAMC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SDRAMC_MR (0x40084000) /**< (SDRAMC) SDRAMC Mode Register */
#define REG_SDRAMC_TR (0x40084004) /**< (SDRAMC) SDRAMC Refresh Timer Register */
#define REG_SDRAMC_CR (0x40084008) /**< (SDRAMC) SDRAMC Configuration Register */
#define REG_SDRAMC_LPR (0x40084010) /**< (SDRAMC) SDRAMC Low Power Register */
#define REG_SDRAMC_IER (0x40084014) /**< (SDRAMC) SDRAMC Interrupt Enable Register */
#define REG_SDRAMC_IDR (0x40084018) /**< (SDRAMC) SDRAMC Interrupt Disable Register */
#define REG_SDRAMC_IMR (0x4008401C) /**< (SDRAMC) SDRAMC Interrupt Mask Register */
#define REG_SDRAMC_ISR (0x40084020) /**< (SDRAMC) SDRAMC Interrupt Status Register */
#define REG_SDRAMC_MDR (0x40084024) /**< (SDRAMC) SDRAMC Memory Device Register */
#define REG_SDRAMC_CFR1 (0x40084028) /**< (SDRAMC) SDRAMC Configuration Register 1 */
#define REG_SDRAMC_OCMS (0x4008402C) /**< (SDRAMC) SDRAMC OCMS Register */
#define REG_SDRAMC_OCMS_KEY1 (0x40084030) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */
#define REG_SDRAMC_OCMS_KEY2 (0x40084034) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */
#else
#define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< (SDRAMC) SDRAMC Mode Register */
#define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< (SDRAMC) SDRAMC Refresh Timer Register */
#define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< (SDRAMC) SDRAMC Configuration Register */
#define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< (SDRAMC) SDRAMC Low Power Register */
#define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< (SDRAMC) SDRAMC Interrupt Enable Register */
#define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< (SDRAMC) SDRAMC Interrupt Disable Register */
#define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< (SDRAMC) SDRAMC Interrupt Mask Register */
#define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< (SDRAMC) SDRAMC Interrupt Status Register */
#define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< (SDRAMC) SDRAMC Memory Device Register */
#define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< (SDRAMC) SDRAMC Configuration Register 1 */
#define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< (SDRAMC) SDRAMC OCMS Register */
#define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */
#define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SDRAMC peripheral ========== */
#define SDRAMC_INSTANCE_ID 62
#define SDRAMC_CLOCK_ID 62
#endif /* _SAME70_SDRAMC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SMC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SMC_INSTANCE_H_
#define _SAME70_SMC_INSTANCE_H_
/* ========== Register definition for SMC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SMC_SETUP0 (0x40080000) /**< (SMC) SMC Setup Register (CS_number = 0) 0 */
#define REG_SMC_PULSE0 (0x40080004) /**< (SMC) SMC Pulse Register (CS_number = 0) 0 */
#define REG_SMC_CYCLE0 (0x40080008) /**< (SMC) SMC Cycle Register (CS_number = 0) 0 */
#define REG_SMC_MODE0 (0x4008000C) /**< (SMC) SMC MODE Register (CS_number = 0) 0 */
#define REG_SMC_SETUP1 (0x40080010) /**< (SMC) SMC Setup Register (CS_number = 0) 1 */
#define REG_SMC_PULSE1 (0x40080014) /**< (SMC) SMC Pulse Register (CS_number = 0) 1 */
#define REG_SMC_CYCLE1 (0x40080018) /**< (SMC) SMC Cycle Register (CS_number = 0) 1 */
#define REG_SMC_MODE1 (0x4008001C) /**< (SMC) SMC MODE Register (CS_number = 0) 1 */
#define REG_SMC_SETUP2 (0x40080020) /**< (SMC) SMC Setup Register (CS_number = 0) 2 */
#define REG_SMC_PULSE2 (0x40080024) /**< (SMC) SMC Pulse Register (CS_number = 0) 2 */
#define REG_SMC_CYCLE2 (0x40080028) /**< (SMC) SMC Cycle Register (CS_number = 0) 2 */
#define REG_SMC_MODE2 (0x4008002C) /**< (SMC) SMC MODE Register (CS_number = 0) 2 */
#define REG_SMC_SETUP3 (0x40080030) /**< (SMC) SMC Setup Register (CS_number = 0) 3 */
#define REG_SMC_PULSE3 (0x40080034) /**< (SMC) SMC Pulse Register (CS_number = 0) 3 */
#define REG_SMC_CYCLE3 (0x40080038) /**< (SMC) SMC Cycle Register (CS_number = 0) 3 */
#define REG_SMC_MODE3 (0x4008003C) /**< (SMC) SMC MODE Register (CS_number = 0) 3 */
#define REG_SMC_OCMS (0x40080080) /**< (SMC) SMC OCMS MODE Register */
#define REG_SMC_KEY1 (0x40080084) /**< (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2 (0x40080088) /**< (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPMR (0x400800E4) /**< (SMC) SMC Write Protection Mode Register */
#define REG_SMC_WPSR (0x400800E8) /**< (SMC) SMC Write Protection Status Register */
#else
#define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< (SMC) SMC Setup Register (CS_number = 0) 0 */
#define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< (SMC) SMC Pulse Register (CS_number = 0) 0 */
#define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< (SMC) SMC Cycle Register (CS_number = 0) 0 */
#define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< (SMC) SMC MODE Register (CS_number = 0) 0 */
#define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< (SMC) SMC Setup Register (CS_number = 0) 1 */
#define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< (SMC) SMC Pulse Register (CS_number = 0) 1 */
#define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< (SMC) SMC Cycle Register (CS_number = 0) 1 */
#define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< (SMC) SMC MODE Register (CS_number = 0) 1 */
#define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< (SMC) SMC Setup Register (CS_number = 0) 2 */
#define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< (SMC) SMC Pulse Register (CS_number = 0) 2 */
#define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< (SMC) SMC Cycle Register (CS_number = 0) 2 */
#define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< (SMC) SMC MODE Register (CS_number = 0) 2 */
#define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< (SMC) SMC Setup Register (CS_number = 0) 3 */
#define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< (SMC) SMC Pulse Register (CS_number = 0) 3 */
#define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< (SMC) SMC Cycle Register (CS_number = 0) 3 */
#define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< (SMC) SMC MODE Register (CS_number = 0) 3 */
#define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< (SMC) SMC OCMS MODE Register */
#define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< (SMC) SMC Write Protection Mode Register */
#define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< (SMC) SMC Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SMC peripheral ========== */
#define SMC_INSTANCE_ID 9
#define SMC_CLOCK_ID 9
#endif /* _SAME70_SMC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SPI0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SPI0_INSTANCE_H_
#define _SAME70_SPI0_INSTANCE_H_
/* ========== Register definition for SPI0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SPI0_CR (0x40008000) /**< (SPI0) Control Register */
#define REG_SPI0_MR (0x40008004) /**< (SPI0) Mode Register */
#define REG_SPI0_RDR (0x40008008) /**< (SPI0) Receive Data Register */
#define REG_SPI0_TDR (0x4000800C) /**< (SPI0) Transmit Data Register */
#define REG_SPI0_SR (0x40008010) /**< (SPI0) Status Register */
#define REG_SPI0_IER (0x40008014) /**< (SPI0) Interrupt Enable Register */
#define REG_SPI0_IDR (0x40008018) /**< (SPI0) Interrupt Disable Register */
#define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */
#define REG_SPI0_CSR (0x40008030) /**< (SPI0) Chip Select Register 0 */
#define REG_SPI0_CSR0 (0x40008030) /**< (SPI0) Chip Select Register 0 */
#define REG_SPI0_CSR1 (0x40008034) /**< (SPI0) Chip Select Register 1 */
#define REG_SPI0_CSR2 (0x40008038) /**< (SPI0) Chip Select Register 2 */
#define REG_SPI0_CSR3 (0x4000803C) /**< (SPI0) Chip Select Register 3 */
#define REG_SPI0_WPMR (0x400080E4) /**< (SPI0) Write Protection Mode Register */
#define REG_SPI0_WPSR (0x400080E8) /**< (SPI0) Write Protection Status Register */
#else
#define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< (SPI0) Control Register */
#define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< (SPI0) Mode Register */
#define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< (SPI0) Receive Data Register */
#define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< (SPI0) Transmit Data Register */
#define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< (SPI0) Status Register */
#define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< (SPI0) Interrupt Enable Register */
#define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< (SPI0) Interrupt Disable Register */
#define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register */
#define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register 0 */
#define REG_SPI0_CSR0 (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register 0 */
#define REG_SPI0_CSR1 (*(__IO uint32_t*)0x40008034U) /**< (SPI0) Chip Select Register 1 */
#define REG_SPI0_CSR2 (*(__IO uint32_t*)0x40008038U) /**< (SPI0) Chip Select Register 2 */
#define REG_SPI0_CSR3 (*(__IO uint32_t*)0x4000803CU) /**< (SPI0) Chip Select Register 3 */
#define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< (SPI0) Write Protection Mode Register */
#define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< (SPI0) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SPI0 peripheral ========== */
#define SPI0_INSTANCE_ID 21
#define SPI0_CLOCK_ID 21
#define SPI0_DMAC_ID_TX 1
#define SPI0_DMAC_ID_RX 2
#endif /* _SAME70_SPI0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SPI1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SPI1_INSTANCE_H_
#define _SAME70_SPI1_INSTANCE_H_
/* ========== Register definition for SPI1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SPI1_CR (0x40058000) /**< (SPI1) Control Register */
#define REG_SPI1_MR (0x40058004) /**< (SPI1) Mode Register */
#define REG_SPI1_RDR (0x40058008) /**< (SPI1) Receive Data Register */
#define REG_SPI1_TDR (0x4005800C) /**< (SPI1) Transmit Data Register */
#define REG_SPI1_SR (0x40058010) /**< (SPI1) Status Register */
#define REG_SPI1_IER (0x40058014) /**< (SPI1) Interrupt Enable Register */
#define REG_SPI1_IDR (0x40058018) /**< (SPI1) Interrupt Disable Register */
#define REG_SPI1_IMR (0x4005801C) /**< (SPI1) Interrupt Mask Register */
#define REG_SPI1_CSR (0x40058030) /**< (SPI1) Chip Select Register 0 */
#define REG_SPI1_CSR0 (0x40058030) /**< (SPI1) Chip Select Register 0 */
#define REG_SPI1_CSR1 (0x40058034) /**< (SPI1) Chip Select Register 1 */
#define REG_SPI1_CSR2 (0x40058038) /**< (SPI1) Chip Select Register 2 */
#define REG_SPI1_CSR3 (0x4005803C) /**< (SPI1) Chip Select Register 3 */
#define REG_SPI1_WPMR (0x400580E4) /**< (SPI1) Write Protection Mode Register */
#define REG_SPI1_WPSR (0x400580E8) /**< (SPI1) Write Protection Status Register */
#else
#define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< (SPI1) Control Register */
#define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< (SPI1) Mode Register */
#define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< (SPI1) Receive Data Register */
#define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< (SPI1) Transmit Data Register */
#define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< (SPI1) Status Register */
#define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< (SPI1) Interrupt Enable Register */
#define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< (SPI1) Interrupt Disable Register */
#define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< (SPI1) Interrupt Mask Register */
#define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */
#define REG_SPI1_CSR0 (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */
#define REG_SPI1_CSR1 (*(__IO uint32_t*)0x40058034U) /**< (SPI1) Chip Select Register 1 */
#define REG_SPI1_CSR2 (*(__IO uint32_t*)0x40058038U) /**< (SPI1) Chip Select Register 2 */
#define REG_SPI1_CSR3 (*(__IO uint32_t*)0x4005803CU) /**< (SPI1) Chip Select Register 3 */
#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< (SPI1) Write Protection Mode Register */
#define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< (SPI1) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SPI1 peripheral ========== */
#define SPI1_INSTANCE_ID 42
#define SPI1_CLOCK_ID 42
#define SPI1_DMAC_ID_TX 3
#define SPI1_DMAC_ID_RX 4
#endif /* _SAME70_SPI1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SSC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SSC_INSTANCE_H_
#define _SAME70_SSC_INSTANCE_H_
/* ========== Register definition for SSC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SSC_CR (0x40004000) /**< (SSC) Control Register */
#define REG_SSC_CMR (0x40004004) /**< (SSC) Clock Mode Register */
#define REG_SSC_RCMR (0x40004010) /**< (SSC) Receive Clock Mode Register */
#define REG_SSC_RFMR (0x40004014) /**< (SSC) Receive Frame Mode Register */
#define REG_SSC_TCMR (0x40004018) /**< (SSC) Transmit Clock Mode Register */
#define REG_SSC_TFMR (0x4000401C) /**< (SSC) Transmit Frame Mode Register */
#define REG_SSC_RHR (0x40004020) /**< (SSC) Receive Holding Register */
#define REG_SSC_THR (0x40004024) /**< (SSC) Transmit Holding Register */
#define REG_SSC_RSHR (0x40004030) /**< (SSC) Receive Sync. Holding Register */
#define REG_SSC_TSHR (0x40004034) /**< (SSC) Transmit Sync. Holding Register */
#define REG_SSC_RC0R (0x40004038) /**< (SSC) Receive Compare 0 Register */
#define REG_SSC_RC1R (0x4000403C) /**< (SSC) Receive Compare 1 Register */
#define REG_SSC_SR (0x40004040) /**< (SSC) Status Register */
#define REG_SSC_IER (0x40004044) /**< (SSC) Interrupt Enable Register */
#define REG_SSC_IDR (0x40004048) /**< (SSC) Interrupt Disable Register */
#define REG_SSC_IMR (0x4000404C) /**< (SSC) Interrupt Mask Register */
#define REG_SSC_WPMR (0x400040E4) /**< (SSC) Write Protection Mode Register */
#define REG_SSC_WPSR (0x400040E8) /**< (SSC) Write Protection Status Register */
#else
#define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< (SSC) Control Register */
#define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< (SSC) Clock Mode Register */
#define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< (SSC) Receive Clock Mode Register */
#define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< (SSC) Receive Frame Mode Register */
#define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< (SSC) Transmit Clock Mode Register */
#define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< (SSC) Transmit Frame Mode Register */
#define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< (SSC) Receive Holding Register */
#define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< (SSC) Transmit Holding Register */
#define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< (SSC) Receive Sync. Holding Register */
#define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< (SSC) Transmit Sync. Holding Register */
#define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< (SSC) Receive Compare 0 Register */
#define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< (SSC) Receive Compare 1 Register */
#define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< (SSC) Status Register */
#define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< (SSC) Interrupt Enable Register */
#define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< (SSC) Interrupt Disable Register */
#define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< (SSC) Interrupt Mask Register */
#define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< (SSC) Write Protection Mode Register */
#define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< (SSC) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SSC peripheral ========== */
#define SSC_INSTANCE_ID 22
#define SSC_CLOCK_ID 22
#define SSC_DMAC_ID_TX 32
#define SSC_DMAC_ID_RX 33
#endif /* _SAME70_SSC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SUPC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_SUPC_INSTANCE_H_
#define _SAME70_SUPC_INSTANCE_H_
/* ========== Register definition for SUPC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SUPC_CR (0x400E1810) /**< (SUPC) Supply Controller Control Register */
#define REG_SUPC_SMMR (0x400E1814) /**< (SUPC) Supply Controller Supply Monitor Mode Register */
#define REG_SUPC_MR (0x400E1818) /**< (SUPC) Supply Controller Mode Register */
#define REG_SUPC_WUMR (0x400E181C) /**< (SUPC) Supply Controller Wake-up Mode Register */
#define REG_SUPC_WUIR (0x400E1820) /**< (SUPC) Supply Controller Wake-up Inputs Register */
#define REG_SUPC_SR (0x400E1824) /**< (SUPC) Supply Controller Status Register */
#else
#define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< (SUPC) Supply Controller Control Register */
#define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< (SUPC) Supply Controller Supply Monitor Mode Register */
#define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< (SUPC) Supply Controller Mode Register */
#define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< (SUPC) Supply Controller Wake-up Mode Register */
#define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< (SUPC) Supply Controller Wake-up Inputs Register */
#define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< (SUPC) Supply Controller Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for SUPC peripheral ========== */
#define SUPC_INSTANCE_ID 0
#endif /* _SAME70_SUPC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TC0_INSTANCE_H_
#define _SAME70_TC0_INSTANCE_H_
/* ========== Register definition for TC0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC0_CCR0 (0x4000C000) /**< (TC0) Channel Control Register (channel = 0) 0 */
#define REG_TC0_CMR0 (0x4000C004) /**< (TC0) Channel Mode Register (channel = 0) 0 */
#define REG_TC0_SMMR0 (0x4000C008) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC0_RAB0 (0x4000C00C) /**< (TC0) Register AB (channel = 0) 0 */
#define REG_TC0_CV0 (0x4000C010) /**< (TC0) Counter Value (channel = 0) 0 */
#define REG_TC0_RA0 (0x4000C014) /**< (TC0) Register A (channel = 0) 0 */
#define REG_TC0_RB0 (0x4000C018) /**< (TC0) Register B (channel = 0) 0 */
#define REG_TC0_RC0 (0x4000C01C) /**< (TC0) Register C (channel = 0) 0 */
#define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */
#define REG_TC0_IER0 (0x4000C024) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC0_IDR0 (0x4000C028) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC0_IMR0 (0x4000C02C) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC0_EMR0 (0x4000C030) /**< (TC0) Extended Mode Register (channel = 0) 0 */
#define REG_TC0_CCR1 (0x4000C040) /**< (TC0) Channel Control Register (channel = 0) 1 */
#define REG_TC0_CMR1 (0x4000C044) /**< (TC0) Channel Mode Register (channel = 0) 1 */
#define REG_TC0_SMMR1 (0x4000C048) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC0_RAB1 (0x4000C04C) /**< (TC0) Register AB (channel = 0) 1 */
#define REG_TC0_CV1 (0x4000C050) /**< (TC0) Counter Value (channel = 0) 1 */
#define REG_TC0_RA1 (0x4000C054) /**< (TC0) Register A (channel = 0) 1 */
#define REG_TC0_RB1 (0x4000C058) /**< (TC0) Register B (channel = 0) 1 */
#define REG_TC0_RC1 (0x4000C05C) /**< (TC0) Register C (channel = 0) 1 */
#define REG_TC0_SR1 (0x4000C060) /**< (TC0) Status Register (channel = 0) 1 */
#define REG_TC0_IER1 (0x4000C064) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC0_IDR1 (0x4000C068) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC0_EMR1 (0x4000C070) /**< (TC0) Extended Mode Register (channel = 0) 1 */
#define REG_TC0_CCR2 (0x4000C080) /**< (TC0) Channel Control Register (channel = 0) 2 */
#define REG_TC0_CMR2 (0x4000C084) /**< (TC0) Channel Mode Register (channel = 0) 2 */
#define REG_TC0_SMMR2 (0x4000C088) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC0_RAB2 (0x4000C08C) /**< (TC0) Register AB (channel = 0) 2 */
#define REG_TC0_CV2 (0x4000C090) /**< (TC0) Counter Value (channel = 0) 2 */
#define REG_TC0_RA2 (0x4000C094) /**< (TC0) Register A (channel = 0) 2 */
#define REG_TC0_RB2 (0x4000C098) /**< (TC0) Register B (channel = 0) 2 */
#define REG_TC0_RC2 (0x4000C09C) /**< (TC0) Register C (channel = 0) 2 */
#define REG_TC0_SR2 (0x4000C0A0) /**< (TC0) Status Register (channel = 0) 2 */
#define REG_TC0_IER2 (0x4000C0A4) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC0_IDR2 (0x4000C0A8) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC0_IMR2 (0x4000C0AC) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC0_EMR2 (0x4000C0B0) /**< (TC0) Extended Mode Register (channel = 0) 2 */
#define REG_TC0_BCR (0x4000C0C0) /**< (TC0) Block Control Register */
#define REG_TC0_BMR (0x4000C0C4) /**< (TC0) Block Mode Register */
#define REG_TC0_QIER (0x4000C0C8) /**< (TC0) QDEC Interrupt Enable Register */
#define REG_TC0_QIDR (0x4000C0CC) /**< (TC0) QDEC Interrupt Disable Register */
#define REG_TC0_QIMR (0x4000C0D0) /**< (TC0) QDEC Interrupt Mask Register */
#define REG_TC0_QISR (0x4000C0D4) /**< (TC0) QDEC Interrupt Status Register */
#define REG_TC0_FMR (0x4000C0D8) /**< (TC0) Fault Mode Register */
#define REG_TC0_WPMR (0x4000C0E4) /**< (TC0) Write Protection Mode Register */
#else
#define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< (TC0) Channel Control Register (channel = 0) 0 */
#define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< (TC0) Channel Mode Register (channel = 0) 0 */
#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< (TC0) Register AB (channel = 0) 0 */
#define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< (TC0) Counter Value (channel = 0) 0 */
#define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< (TC0) Register A (channel = 0) 0 */
#define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< (TC0) Register B (channel = 0) 0 */
#define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< (TC0) Register C (channel = 0) 0 */
#define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel = 0) 0 */
#define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< (TC0) Extended Mode Register (channel = 0) 0 */
#define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< (TC0) Channel Control Register (channel = 0) 1 */
#define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< (TC0) Channel Mode Register (channel = 0) 1 */
#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< (TC0) Register AB (channel = 0) 1 */
#define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< (TC0) Counter Value (channel = 0) 1 */
#define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< (TC0) Register A (channel = 0) 1 */
#define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< (TC0) Register B (channel = 0) 1 */
#define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< (TC0) Register C (channel = 0) 1 */
#define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< (TC0) Status Register (channel = 0) 1 */
#define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< (TC0) Extended Mode Register (channel = 0) 1 */
#define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< (TC0) Channel Control Register (channel = 0) 2 */
#define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< (TC0) Channel Mode Register (channel = 0) 2 */
#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< (TC0) Register AB (channel = 0) 2 */
#define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< (TC0) Counter Value (channel = 0) 2 */
#define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< (TC0) Register A (channel = 0) 2 */
#define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< (TC0) Register B (channel = 0) 2 */
#define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< (TC0) Register C (channel = 0) 2 */
#define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< (TC0) Status Register (channel = 0) 2 */
#define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< (TC0) Extended Mode Register (channel = 0) 2 */
#define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< (TC0) Block Control Register */
#define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< (TC0) Block Mode Register */
#define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< (TC0) QDEC Interrupt Enable Register */
#define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< (TC0) QDEC Interrupt Disable Register */
#define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< (TC0) QDEC Interrupt Mask Register */
#define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< (TC0) QDEC Interrupt Status Register */
#define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< (TC0) Fault Mode Register */
#define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< (TC0) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TC0 peripheral ========== */
#define TC0_INSTANCE_ID_CHANNEL1 24
#define TC0_INSTANCE_ID_CHANNEL0 23
#define TC0_INSTANCE_ID_CHANNEL2 25
#define TC0_DMAC_ID_RX 40
#endif /* _SAME70_TC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TC1_INSTANCE_H_
#define _SAME70_TC1_INSTANCE_H_
/* ========== Register definition for TC1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC1_CCR0 (0x40010000) /**< (TC1) Channel Control Register (channel = 0) 0 */
#define REG_TC1_CMR0 (0x40010004) /**< (TC1) Channel Mode Register (channel = 0) 0 */
#define REG_TC1_SMMR0 (0x40010008) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC1_RAB0 (0x4001000C) /**< (TC1) Register AB (channel = 0) 0 */
#define REG_TC1_CV0 (0x40010010) /**< (TC1) Counter Value (channel = 0) 0 */
#define REG_TC1_RA0 (0x40010014) /**< (TC1) Register A (channel = 0) 0 */
#define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */
#define REG_TC1_RC0 (0x4001001C) /**< (TC1) Register C (channel = 0) 0 */
#define REG_TC1_SR0 (0x40010020) /**< (TC1) Status Register (channel = 0) 0 */
#define REG_TC1_IER0 (0x40010024) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC1_IDR0 (0x40010028) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC1_IMR0 (0x4001002C) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC1_EMR0 (0x40010030) /**< (TC1) Extended Mode Register (channel = 0) 0 */
#define REG_TC1_CCR1 (0x40010040) /**< (TC1) Channel Control Register (channel = 0) 1 */
#define REG_TC1_CMR1 (0x40010044) /**< (TC1) Channel Mode Register (channel = 0) 1 */
#define REG_TC1_SMMR1 (0x40010048) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC1_RAB1 (0x4001004C) /**< (TC1) Register AB (channel = 0) 1 */
#define REG_TC1_CV1 (0x40010050) /**< (TC1) Counter Value (channel = 0) 1 */
#define REG_TC1_RA1 (0x40010054) /**< (TC1) Register A (channel = 0) 1 */
#define REG_TC1_RB1 (0x40010058) /**< (TC1) Register B (channel = 0) 1 */
#define REG_TC1_RC1 (0x4001005C) /**< (TC1) Register C (channel = 0) 1 */
#define REG_TC1_SR1 (0x40010060) /**< (TC1) Status Register (channel = 0) 1 */
#define REG_TC1_IER1 (0x40010064) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC1_IDR1 (0x40010068) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC1_IMR1 (0x4001006C) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC1_EMR1 (0x40010070) /**< (TC1) Extended Mode Register (channel = 0) 1 */
#define REG_TC1_CCR2 (0x40010080) /**< (TC1) Channel Control Register (channel = 0) 2 */
#define REG_TC1_CMR2 (0x40010084) /**< (TC1) Channel Mode Register (channel = 0) 2 */
#define REG_TC1_SMMR2 (0x40010088) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC1_RAB2 (0x4001008C) /**< (TC1) Register AB (channel = 0) 2 */
#define REG_TC1_CV2 (0x40010090) /**< (TC1) Counter Value (channel = 0) 2 */
#define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */
#define REG_TC1_RB2 (0x40010098) /**< (TC1) Register B (channel = 0) 2 */
#define REG_TC1_RC2 (0x4001009C) /**< (TC1) Register C (channel = 0) 2 */
#define REG_TC1_SR2 (0x400100A0) /**< (TC1) Status Register (channel = 0) 2 */
#define REG_TC1_IER2 (0x400100A4) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC1_IDR2 (0x400100A8) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC1_IMR2 (0x400100AC) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC1_EMR2 (0x400100B0) /**< (TC1) Extended Mode Register (channel = 0) 2 */
#define REG_TC1_BCR (0x400100C0) /**< (TC1) Block Control Register */
#define REG_TC1_BMR (0x400100C4) /**< (TC1) Block Mode Register */
#define REG_TC1_QIER (0x400100C8) /**< (TC1) QDEC Interrupt Enable Register */
#define REG_TC1_QIDR (0x400100CC) /**< (TC1) QDEC Interrupt Disable Register */
#define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */
#define REG_TC1_QISR (0x400100D4) /**< (TC1) QDEC Interrupt Status Register */
#define REG_TC1_FMR (0x400100D8) /**< (TC1) Fault Mode Register */
#define REG_TC1_WPMR (0x400100E4) /**< (TC1) Write Protection Mode Register */
#else
#define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< (TC1) Channel Control Register (channel = 0) 0 */
#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< (TC1) Channel Mode Register (channel = 0) 0 */
#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< (TC1) Register AB (channel = 0) 0 */
#define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< (TC1) Counter Value (channel = 0) 0 */
#define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< (TC1) Register A (channel = 0) 0 */
#define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) 0 */
#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< (TC1) Register C (channel = 0) 0 */
#define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< (TC1) Status Register (channel = 0) 0 */
#define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< (TC1) Extended Mode Register (channel = 0) 0 */
#define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< (TC1) Channel Control Register (channel = 0) 1 */
#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< (TC1) Channel Mode Register (channel = 0) 1 */
#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< (TC1) Register AB (channel = 0) 1 */
#define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< (TC1) Counter Value (channel = 0) 1 */
#define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< (TC1) Register A (channel = 0) 1 */
#define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< (TC1) Register B (channel = 0) 1 */
#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< (TC1) Register C (channel = 0) 1 */
#define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< (TC1) Status Register (channel = 0) 1 */
#define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< (TC1) Extended Mode Register (channel = 0) 1 */
#define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< (TC1) Channel Control Register (channel = 0) 2 */
#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< (TC1) Channel Mode Register (channel = 0) 2 */
#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< (TC1) Register AB (channel = 0) 2 */
#define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< (TC1) Counter Value (channel = 0) 2 */
#define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) 2 */
#define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< (TC1) Register B (channel = 0) 2 */
#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< (TC1) Register C (channel = 0) 2 */
#define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< (TC1) Status Register (channel = 0) 2 */
#define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< (TC1) Extended Mode Register (channel = 0) 2 */
#define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< (TC1) Block Control Register */
#define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< (TC1) Block Mode Register */
#define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< (TC1) QDEC Interrupt Enable Register */
#define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< (TC1) QDEC Interrupt Disable Register */
#define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Register */
#define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< (TC1) QDEC Interrupt Status Register */
#define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< (TC1) Fault Mode Register */
#define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< (TC1) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TC1 peripheral ========== */
#define TC1_INSTANCE_ID_CHANNEL1 27
#define TC1_INSTANCE_ID_CHANNEL0 26
#define TC1_INSTANCE_ID_CHANNEL2 28
#define TC1_DMAC_ID_RX 41
#endif /* _SAME70_TC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC2
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TC2_INSTANCE_H_
#define _SAME70_TC2_INSTANCE_H_
/* ========== Register definition for TC2 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC2_CCR0 (0x40014000) /**< (TC2) Channel Control Register (channel = 0) 0 */
#define REG_TC2_CMR0 (0x40014004) /**< (TC2) Channel Mode Register (channel = 0) 0 */
#define REG_TC2_SMMR0 (0x40014008) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC2_RAB0 (0x4001400C) /**< (TC2) Register AB (channel = 0) 0 */
#define REG_TC2_CV0 (0x40014010) /**< (TC2) Counter Value (channel = 0) 0 */
#define REG_TC2_RA0 (0x40014014) /**< (TC2) Register A (channel = 0) 0 */
#define REG_TC2_RB0 (0x40014018) /**< (TC2) Register B (channel = 0) 0 */
#define REG_TC2_RC0 (0x4001401C) /**< (TC2) Register C (channel = 0) 0 */
#define REG_TC2_SR0 (0x40014020) /**< (TC2) Status Register (channel = 0) 0 */
#define REG_TC2_IER0 (0x40014024) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC2_IDR0 (0x40014028) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC2_IMR0 (0x4001402C) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC2_EMR0 (0x40014030) /**< (TC2) Extended Mode Register (channel = 0) 0 */
#define REG_TC2_CCR1 (0x40014040) /**< (TC2) Channel Control Register (channel = 0) 1 */
#define REG_TC2_CMR1 (0x40014044) /**< (TC2) Channel Mode Register (channel = 0) 1 */
#define REG_TC2_SMMR1 (0x40014048) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC2_RAB1 (0x4001404C) /**< (TC2) Register AB (channel = 0) 1 */
#define REG_TC2_CV1 (0x40014050) /**< (TC2) Counter Value (channel = 0) 1 */
#define REG_TC2_RA1 (0x40014054) /**< (TC2) Register A (channel = 0) 1 */
#define REG_TC2_RB1 (0x40014058) /**< (TC2) Register B (channel = 0) 1 */
#define REG_TC2_RC1 (0x4001405C) /**< (TC2) Register C (channel = 0) 1 */
#define REG_TC2_SR1 (0x40014060) /**< (TC2) Status Register (channel = 0) 1 */
#define REG_TC2_IER1 (0x40014064) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC2_IDR1 (0x40014068) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC2_IMR1 (0x4001406C) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC2_EMR1 (0x40014070) /**< (TC2) Extended Mode Register (channel = 0) 1 */
#define REG_TC2_CCR2 (0x40014080) /**< (TC2) Channel Control Register (channel = 0) 2 */
#define REG_TC2_CMR2 (0x40014084) /**< (TC2) Channel Mode Register (channel = 0) 2 */
#define REG_TC2_SMMR2 (0x40014088) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC2_RAB2 (0x4001408C) /**< (TC2) Register AB (channel = 0) 2 */
#define REG_TC2_CV2 (0x40014090) /**< (TC2) Counter Value (channel = 0) 2 */
#define REG_TC2_RA2 (0x40014094) /**< (TC2) Register A (channel = 0) 2 */
#define REG_TC2_RB2 (0x40014098) /**< (TC2) Register B (channel = 0) 2 */
#define REG_TC2_RC2 (0x4001409C) /**< (TC2) Register C (channel = 0) 2 */
#define REG_TC2_SR2 (0x400140A0) /**< (TC2) Status Register (channel = 0) 2 */
#define REG_TC2_IER2 (0x400140A4) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC2_IDR2 (0x400140A8) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC2_IMR2 (0x400140AC) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC2_EMR2 (0x400140B0) /**< (TC2) Extended Mode Register (channel = 0) 2 */
#define REG_TC2_BCR (0x400140C0) /**< (TC2) Block Control Register */
#define REG_TC2_BMR (0x400140C4) /**< (TC2) Block Mode Register */
#define REG_TC2_QIER (0x400140C8) /**< (TC2) QDEC Interrupt Enable Register */
#define REG_TC2_QIDR (0x400140CC) /**< (TC2) QDEC Interrupt Disable Register */
#define REG_TC2_QIMR (0x400140D0) /**< (TC2) QDEC Interrupt Mask Register */
#define REG_TC2_QISR (0x400140D4) /**< (TC2) QDEC Interrupt Status Register */
#define REG_TC2_FMR (0x400140D8) /**< (TC2) Fault Mode Register */
#define REG_TC2_WPMR (0x400140E4) /**< (TC2) Write Protection Mode Register */
#else
#define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< (TC2) Channel Control Register (channel = 0) 0 */
#define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< (TC2) Channel Mode Register (channel = 0) 0 */
#define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< (TC2) Register AB (channel = 0) 0 */
#define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< (TC2) Counter Value (channel = 0) 0 */
#define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< (TC2) Register A (channel = 0) 0 */
#define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< (TC2) Register B (channel = 0) 0 */
#define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< (TC2) Register C (channel = 0) 0 */
#define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< (TC2) Status Register (channel = 0) 0 */
#define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< (TC2) Extended Mode Register (channel = 0) 0 */
#define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< (TC2) Channel Control Register (channel = 0) 1 */
#define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< (TC2) Channel Mode Register (channel = 0) 1 */
#define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< (TC2) Register AB (channel = 0) 1 */
#define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< (TC2) Counter Value (channel = 0) 1 */
#define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< (TC2) Register A (channel = 0) 1 */
#define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< (TC2) Register B (channel = 0) 1 */
#define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< (TC2) Register C (channel = 0) 1 */
#define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< (TC2) Status Register (channel = 0) 1 */
#define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< (TC2) Extended Mode Register (channel = 0) 1 */
#define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< (TC2) Channel Control Register (channel = 0) 2 */
#define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< (TC2) Channel Mode Register (channel = 0) 2 */
#define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< (TC2) Register AB (channel = 0) 2 */
#define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< (TC2) Counter Value (channel = 0) 2 */
#define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< (TC2) Register A (channel = 0) 2 */
#define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< (TC2) Register B (channel = 0) 2 */
#define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< (TC2) Register C (channel = 0) 2 */
#define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< (TC2) Status Register (channel = 0) 2 */
#define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< (TC2) Extended Mode Register (channel = 0) 2 */
#define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< (TC2) Block Control Register */
#define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< (TC2) Block Mode Register */
#define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< (TC2) QDEC Interrupt Enable Register */
#define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< (TC2) QDEC Interrupt Disable Register */
#define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< (TC2) QDEC Interrupt Mask Register */
#define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< (TC2) QDEC Interrupt Status Register */
#define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< (TC2) Fault Mode Register */
#define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< (TC2) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TC2 peripheral ========== */
#define TC2_INSTANCE_ID_CHANNEL1 48
#define TC2_INSTANCE_ID_CHANNEL0 47
#define TC2_INSTANCE_ID_CHANNEL2 49
#define TC2_DMAC_ID_RX 42
#endif /* _SAME70_TC2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC3
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TC3_INSTANCE_H_
#define _SAME70_TC3_INSTANCE_H_
/* ========== Register definition for TC3 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC3_CCR0 (0x40054000) /**< (TC3) Channel Control Register (channel = 0) 0 */
#define REG_TC3_CMR0 (0x40054004) /**< (TC3) Channel Mode Register (channel = 0) 0 */
#define REG_TC3_SMMR0 (0x40054008) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC3_RAB0 (0x4005400C) /**< (TC3) Register AB (channel = 0) 0 */
#define REG_TC3_CV0 (0x40054010) /**< (TC3) Counter Value (channel = 0) 0 */
#define REG_TC3_RA0 (0x40054014) /**< (TC3) Register A (channel = 0) 0 */
#define REG_TC3_RB0 (0x40054018) /**< (TC3) Register B (channel = 0) 0 */
#define REG_TC3_RC0 (0x4005401C) /**< (TC3) Register C (channel = 0) 0 */
#define REG_TC3_SR0 (0x40054020) /**< (TC3) Status Register (channel = 0) 0 */
#define REG_TC3_IER0 (0x40054024) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC3_IDR0 (0x40054028) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC3_IMR0 (0x4005402C) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC3_EMR0 (0x40054030) /**< (TC3) Extended Mode Register (channel = 0) 0 */
#define REG_TC3_CCR1 (0x40054040) /**< (TC3) Channel Control Register (channel = 0) 1 */
#define REG_TC3_CMR1 (0x40054044) /**< (TC3) Channel Mode Register (channel = 0) 1 */
#define REG_TC3_SMMR1 (0x40054048) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC3_RAB1 (0x4005404C) /**< (TC3) Register AB (channel = 0) 1 */
#define REG_TC3_CV1 (0x40054050) /**< (TC3) Counter Value (channel = 0) 1 */
#define REG_TC3_RA1 (0x40054054) /**< (TC3) Register A (channel = 0) 1 */
#define REG_TC3_RB1 (0x40054058) /**< (TC3) Register B (channel = 0) 1 */
#define REG_TC3_RC1 (0x4005405C) /**< (TC3) Register C (channel = 0) 1 */
#define REG_TC3_SR1 (0x40054060) /**< (TC3) Status Register (channel = 0) 1 */
#define REG_TC3_IER1 (0x40054064) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC3_IDR1 (0x40054068) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC3_IMR1 (0x4005406C) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC3_EMR1 (0x40054070) /**< (TC3) Extended Mode Register (channel = 0) 1 */
#define REG_TC3_CCR2 (0x40054080) /**< (TC3) Channel Control Register (channel = 0) 2 */
#define REG_TC3_CMR2 (0x40054084) /**< (TC3) Channel Mode Register (channel = 0) 2 */
#define REG_TC3_SMMR2 (0x40054088) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC3_RAB2 (0x4005408C) /**< (TC3) Register AB (channel = 0) 2 */
#define REG_TC3_CV2 (0x40054090) /**< (TC3) Counter Value (channel = 0) 2 */
#define REG_TC3_RA2 (0x40054094) /**< (TC3) Register A (channel = 0) 2 */
#define REG_TC3_RB2 (0x40054098) /**< (TC3) Register B (channel = 0) 2 */
#define REG_TC3_RC2 (0x4005409C) /**< (TC3) Register C (channel = 0) 2 */
#define REG_TC3_SR2 (0x400540A0) /**< (TC3) Status Register (channel = 0) 2 */
#define REG_TC3_IER2 (0x400540A4) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC3_IDR2 (0x400540A8) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC3_IMR2 (0x400540AC) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC3_EMR2 (0x400540B0) /**< (TC3) Extended Mode Register (channel = 0) 2 */
#define REG_TC3_BCR (0x400540C0) /**< (TC3) Block Control Register */
#define REG_TC3_BMR (0x400540C4) /**< (TC3) Block Mode Register */
#define REG_TC3_QIER (0x400540C8) /**< (TC3) QDEC Interrupt Enable Register */
#define REG_TC3_QIDR (0x400540CC) /**< (TC3) QDEC Interrupt Disable Register */
#define REG_TC3_QIMR (0x400540D0) /**< (TC3) QDEC Interrupt Mask Register */
#define REG_TC3_QISR (0x400540D4) /**< (TC3) QDEC Interrupt Status Register */
#define REG_TC3_FMR (0x400540D8) /**< (TC3) Fault Mode Register */
#define REG_TC3_WPMR (0x400540E4) /**< (TC3) Write Protection Mode Register */
#else
#define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< (TC3) Channel Control Register (channel = 0) 0 */
#define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< (TC3) Channel Mode Register (channel = 0) 0 */
#define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */
#define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< (TC3) Register AB (channel = 0) 0 */
#define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< (TC3) Counter Value (channel = 0) 0 */
#define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< (TC3) Register A (channel = 0) 0 */
#define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< (TC3) Register B (channel = 0) 0 */
#define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< (TC3) Register C (channel = 0) 0 */
#define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< (TC3) Status Register (channel = 0) 0 */
#define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */
#define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */
#define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */
#define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< (TC3) Extended Mode Register (channel = 0) 0 */
#define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< (TC3) Channel Control Register (channel = 0) 1 */
#define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< (TC3) Channel Mode Register (channel = 0) 1 */
#define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */
#define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< (TC3) Register AB (channel = 0) 1 */
#define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< (TC3) Counter Value (channel = 0) 1 */
#define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< (TC3) Register A (channel = 0) 1 */
#define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< (TC3) Register B (channel = 0) 1 */
#define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< (TC3) Register C (channel = 0) 1 */
#define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< (TC3) Status Register (channel = 0) 1 */
#define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */
#define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */
#define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */
#define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< (TC3) Extended Mode Register (channel = 0) 1 */
#define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< (TC3) Channel Control Register (channel = 0) 2 */
#define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< (TC3) Channel Mode Register (channel = 0) 2 */
#define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */
#define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< (TC3) Register AB (channel = 0) 2 */
#define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< (TC3) Counter Value (channel = 0) 2 */
#define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< (TC3) Register A (channel = 0) 2 */
#define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< (TC3) Register B (channel = 0) 2 */
#define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< (TC3) Register C (channel = 0) 2 */
#define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< (TC3) Status Register (channel = 0) 2 */
#define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */
#define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */
#define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */
#define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< (TC3) Extended Mode Register (channel = 0) 2 */
#define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< (TC3) Block Control Register */
#define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< (TC3) Block Mode Register */
#define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< (TC3) QDEC Interrupt Enable Register */
#define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< (TC3) QDEC Interrupt Disable Register */
#define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< (TC3) QDEC Interrupt Mask Register */
#define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< (TC3) QDEC Interrupt Status Register */
#define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< (TC3) Fault Mode Register */
#define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< (TC3) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TC3 peripheral ========== */
#define TC3_INSTANCE_ID_CHANNEL1 51
#define TC3_INSTANCE_ID_CHANNEL0 50
#define TC3_INSTANCE_ID_CHANNEL2 52
#define TC3_DMAC_ID_RX 43
#endif /* _SAME70_TC3_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TRNG
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TRNG_INSTANCE_H_
#define _SAME70_TRNG_INSTANCE_H_
/* ========== Register definition for TRNG peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TRNG_CR (0x40070000) /**< (TRNG) Control Register */
#define REG_TRNG_IER (0x40070010) /**< (TRNG) Interrupt Enable Register */
#define REG_TRNG_IDR (0x40070014) /**< (TRNG) Interrupt Disable Register */
#define REG_TRNG_IMR (0x40070018) /**< (TRNG) Interrupt Mask Register */
#define REG_TRNG_ISR (0x4007001C) /**< (TRNG) Interrupt Status Register */
#define REG_TRNG_ODATA (0x40070050) /**< (TRNG) Output Data Register */
#else
#define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< (TRNG) Control Register */
#define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< (TRNG) Interrupt Enable Register */
#define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< (TRNG) Interrupt Disable Register */
#define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< (TRNG) Interrupt Mask Register */
#define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< (TRNG) Interrupt Status Register */
#define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< (TRNG) Output Data Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TRNG peripheral ========== */
#define TRNG_INSTANCE_ID 57
#define TRNG_CLOCK_ID 57
#endif /* _SAME70_TRNG_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TWIHS0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TWIHS0_INSTANCE_H_
#define _SAME70_TWIHS0_INSTANCE_H_
/* ========== Register definition for TWIHS0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TWIHS0_CR (0x40018000) /**< (TWIHS0) Control Register */
#define REG_TWIHS0_MMR (0x40018004) /**< (TWIHS0) Master Mode Register */
#define REG_TWIHS0_SMR (0x40018008) /**< (TWIHS0) Slave Mode Register */
#define REG_TWIHS0_IADR (0x4001800C) /**< (TWIHS0) Internal Address Register */
#define REG_TWIHS0_CWGR (0x40018010) /**< (TWIHS0) Clock Waveform Generator Register */
#define REG_TWIHS0_SR (0x40018020) /**< (TWIHS0) Status Register */
#define REG_TWIHS0_IER (0x40018024) /**< (TWIHS0) Interrupt Enable Register */
#define REG_TWIHS0_IDR (0x40018028) /**< (TWIHS0) Interrupt Disable Register */
#define REG_TWIHS0_IMR (0x4001802C) /**< (TWIHS0) Interrupt Mask Register */
#define REG_TWIHS0_RHR (0x40018030) /**< (TWIHS0) Receive Holding Register */
#define REG_TWIHS0_THR (0x40018034) /**< (TWIHS0) Transmit Holding Register */
#define REG_TWIHS0_SMBTR (0x40018038) /**< (TWIHS0) SMBus Timing Register */
#define REG_TWIHS0_FILTR (0x40018044) /**< (TWIHS0) Filter Register */
#define REG_TWIHS0_SWMR (0x4001804C) /**< (TWIHS0) SleepWalking Matching Register */
#define REG_TWIHS0_WPMR (0x400180E4) /**< (TWIHS0) Write Protection Mode Register */
#define REG_TWIHS0_WPSR (0x400180E8) /**< (TWIHS0) Write Protection Status Register */
#else
#define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< (TWIHS0) Control Register */
#define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< (TWIHS0) Master Mode Register */
#define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< (TWIHS0) Slave Mode Register */
#define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< (TWIHS0) Internal Address Register */
#define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< (TWIHS0) Clock Waveform Generator Register */
#define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< (TWIHS0) Status Register */
#define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< (TWIHS0) Interrupt Enable Register */
#define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< (TWIHS0) Interrupt Disable Register */
#define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< (TWIHS0) Interrupt Mask Register */
#define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< (TWIHS0) Receive Holding Register */
#define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< (TWIHS0) Transmit Holding Register */
#define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< (TWIHS0) SMBus Timing Register */
#define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< (TWIHS0) Filter Register */
#define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< (TWIHS0) SleepWalking Matching Register */
#define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< (TWIHS0) Write Protection Mode Register */
#define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< (TWIHS0) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TWIHS0 peripheral ========== */
#define TWIHS0_INSTANCE_ID 19
#define TWIHS0_CLOCK_ID 19
#define TWIHS0_DMAC_ID_TX 14
#define TWIHS0_DMAC_ID_RX 15
#endif /* _SAME70_TWIHS0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TWIHS1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TWIHS1_INSTANCE_H_
#define _SAME70_TWIHS1_INSTANCE_H_
/* ========== Register definition for TWIHS1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TWIHS1_CR (0x4001C000) /**< (TWIHS1) Control Register */
#define REG_TWIHS1_MMR (0x4001C004) /**< (TWIHS1) Master Mode Register */
#define REG_TWIHS1_SMR (0x4001C008) /**< (TWIHS1) Slave Mode Register */
#define REG_TWIHS1_IADR (0x4001C00C) /**< (TWIHS1) Internal Address Register */
#define REG_TWIHS1_CWGR (0x4001C010) /**< (TWIHS1) Clock Waveform Generator Register */
#define REG_TWIHS1_SR (0x4001C020) /**< (TWIHS1) Status Register */
#define REG_TWIHS1_IER (0x4001C024) /**< (TWIHS1) Interrupt Enable Register */
#define REG_TWIHS1_IDR (0x4001C028) /**< (TWIHS1) Interrupt Disable Register */
#define REG_TWIHS1_IMR (0x4001C02C) /**< (TWIHS1) Interrupt Mask Register */
#define REG_TWIHS1_RHR (0x4001C030) /**< (TWIHS1) Receive Holding Register */
#define REG_TWIHS1_THR (0x4001C034) /**< (TWIHS1) Transmit Holding Register */
#define REG_TWIHS1_SMBTR (0x4001C038) /**< (TWIHS1) SMBus Timing Register */
#define REG_TWIHS1_FILTR (0x4001C044) /**< (TWIHS1) Filter Register */
#define REG_TWIHS1_SWMR (0x4001C04C) /**< (TWIHS1) SleepWalking Matching Register */
#define REG_TWIHS1_WPMR (0x4001C0E4) /**< (TWIHS1) Write Protection Mode Register */
#define REG_TWIHS1_WPSR (0x4001C0E8) /**< (TWIHS1) Write Protection Status Register */
#else
#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< (TWIHS1) Control Register */
#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< (TWIHS1) Master Mode Register */
#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< (TWIHS1) Slave Mode Register */
#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< (TWIHS1) Internal Address Register */
#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< (TWIHS1) Clock Waveform Generator Register */
#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< (TWIHS1) Status Register */
#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< (TWIHS1) Interrupt Enable Register */
#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< (TWIHS1) Interrupt Disable Register */
#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< (TWIHS1) Interrupt Mask Register */
#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< (TWIHS1) Receive Holding Register */
#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< (TWIHS1) Transmit Holding Register */
#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< (TWIHS1) SMBus Timing Register */
#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< (TWIHS1) Filter Register */
#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< (TWIHS1) SleepWalking Matching Register */
#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< (TWIHS1) Write Protection Mode Register */
#define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< (TWIHS1) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TWIHS1 peripheral ========== */
#define TWIHS1_INSTANCE_ID 20
#define TWIHS1_CLOCK_ID 20
#define TWIHS1_DMAC_ID_TX 16
#define TWIHS1_DMAC_ID_RX 17
#endif /* _SAME70_TWIHS1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TWIHS2
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_TWIHS2_INSTANCE_H_
#define _SAME70_TWIHS2_INSTANCE_H_
/* ========== Register definition for TWIHS2 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TWIHS2_CR (0x40060000) /**< (TWIHS2) Control Register */
#define REG_TWIHS2_MMR (0x40060004) /**< (TWIHS2) Master Mode Register */
#define REG_TWIHS2_SMR (0x40060008) /**< (TWIHS2) Slave Mode Register */
#define REG_TWIHS2_IADR (0x4006000C) /**< (TWIHS2) Internal Address Register */
#define REG_TWIHS2_CWGR (0x40060010) /**< (TWIHS2) Clock Waveform Generator Register */
#define REG_TWIHS2_SR (0x40060020) /**< (TWIHS2) Status Register */
#define REG_TWIHS2_IER (0x40060024) /**< (TWIHS2) Interrupt Enable Register */
#define REG_TWIHS2_IDR (0x40060028) /**< (TWIHS2) Interrupt Disable Register */
#define REG_TWIHS2_IMR (0x4006002C) /**< (TWIHS2) Interrupt Mask Register */
#define REG_TWIHS2_RHR (0x40060030) /**< (TWIHS2) Receive Holding Register */
#define REG_TWIHS2_THR (0x40060034) /**< (TWIHS2) Transmit Holding Register */
#define REG_TWIHS2_SMBTR (0x40060038) /**< (TWIHS2) SMBus Timing Register */
#define REG_TWIHS2_FILTR (0x40060044) /**< (TWIHS2) Filter Register */
#define REG_TWIHS2_SWMR (0x4006004C) /**< (TWIHS2) SleepWalking Matching Register */
#define REG_TWIHS2_WPMR (0x400600E4) /**< (TWIHS2) Write Protection Mode Register */
#define REG_TWIHS2_WPSR (0x400600E8) /**< (TWIHS2) Write Protection Status Register */
#else
#define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< (TWIHS2) Control Register */
#define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< (TWIHS2) Master Mode Register */
#define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< (TWIHS2) Slave Mode Register */
#define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< (TWIHS2) Internal Address Register */
#define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< (TWIHS2) Clock Waveform Generator Register */
#define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< (TWIHS2) Status Register */
#define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< (TWIHS2) Interrupt Enable Register */
#define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< (TWIHS2) Interrupt Disable Register */
#define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< (TWIHS2) Interrupt Mask Register */
#define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< (TWIHS2) Receive Holding Register */
#define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< (TWIHS2) Transmit Holding Register */
#define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< (TWIHS2) SMBus Timing Register */
#define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< (TWIHS2) Filter Register */
#define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< (TWIHS2) SleepWalking Matching Register */
#define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< (TWIHS2) Write Protection Mode Register */
#define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< (TWIHS2) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for TWIHS2 peripheral ========== */
#define TWIHS2_INSTANCE_ID 41
#define TWIHS2_CLOCK_ID 41
#define TWIHS2_DMAC_ID_TX 18
#define TWIHS2_DMAC_ID_RX 19
#endif /* _SAME70_TWIHS2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UART0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART0_INSTANCE_H_
#define _SAME70_UART0_INSTANCE_H_
/* ========== Register definition for UART0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART0_CR (0x400E0800) /**< (UART0) Control Register */
#define REG_UART0_MR (0x400E0804) /**< (UART0) Mode Register */
#define REG_UART0_IER (0x400E0808) /**< (UART0) Interrupt Enable Register */
#define REG_UART0_IDR (0x400E080C) /**< (UART0) Interrupt Disable Register */
#define REG_UART0_IMR (0x400E0810) /**< (UART0) Interrupt Mask Register */
#define REG_UART0_SR (0x400E0814) /**< (UART0) Status Register */
#define REG_UART0_RHR (0x400E0818) /**< (UART0) Receive Holding Register */
#define REG_UART0_THR (0x400E081C) /**< (UART0) Transmit Holding Register */
#define REG_UART0_BRGR (0x400E0820) /**< (UART0) Baud Rate Generator Register */
#define REG_UART0_CMPR (0x400E0824) /**< (UART0) Comparison Register */
#define REG_UART0_WPMR (0x400E08E4) /**< (UART0) Write Protection Mode Register */
#else
#define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */
#define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< (UART0) Mode Register */
#define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Register */
#define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Register */
#define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< (UART0) Interrupt Mask Register */
#define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< (UART0) Status Register */
#define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< (UART0) Receive Holding Register */
#define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Register */
#define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< (UART0) Baud Rate Generator Register */
#define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< (UART0) Comparison Register */
#define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< (UART0) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for UART0 peripheral ========== */
#define UART0_INSTANCE_ID 7
#define UART0_CLOCK_ID 7
#define UART0_DMAC_ID_TX 20
#define UART0_DMAC_ID_RX 21
#endif /* _SAME70_UART0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UART1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART1_INSTANCE_H_
#define _SAME70_UART1_INSTANCE_H_
/* ========== Register definition for UART1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART1_CR (0x400E0A00) /**< (UART1) Control Register */
#define REG_UART1_MR (0x400E0A04) /**< (UART1) Mode Register */
#define REG_UART1_IER (0x400E0A08) /**< (UART1) Interrupt Enable Register */
#define REG_UART1_IDR (0x400E0A0C) /**< (UART1) Interrupt Disable Register */
#define REG_UART1_IMR (0x400E0A10) /**< (UART1) Interrupt Mask Register */
#define REG_UART1_SR (0x400E0A14) /**< (UART1) Status Register */
#define REG_UART1_RHR (0x400E0A18) /**< (UART1) Receive Holding Register */
#define REG_UART1_THR (0x400E0A1C) /**< (UART1) Transmit Holding Register */
#define REG_UART1_BRGR (0x400E0A20) /**< (UART1) Baud Rate Generator Register */
#define REG_UART1_CMPR (0x400E0A24) /**< (UART1) Comparison Register */
#define REG_UART1_WPMR (0x400E0AE4) /**< (UART1) Write Protection Mode Register */
#else
#define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */
#define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< (UART1) Mode Register */
#define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Register */
#define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Register */
#define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< (UART1) Interrupt Mask Register */
#define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< (UART1) Status Register */
#define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< (UART1) Receive Holding Register */
#define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Register */
#define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< (UART1) Baud Rate Generator Register */
#define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< (UART1) Comparison Register */
#define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< (UART1) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for UART1 peripheral ========== */
#define UART1_INSTANCE_ID 8
#define UART1_CLOCK_ID 8
#define UART1_DMAC_ID_TX 22
#define UART1_DMAC_ID_RX 23
#endif /* _SAME70_UART1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UART2
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART2_INSTANCE_H_
#define _SAME70_UART2_INSTANCE_H_
/* ========== Register definition for UART2 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART2_CR (0x400E1A00) /**< (UART2) Control Register */
#define REG_UART2_MR (0x400E1A04) /**< (UART2) Mode Register */
#define REG_UART2_IER (0x400E1A08) /**< (UART2) Interrupt Enable Register */
#define REG_UART2_IDR (0x400E1A0C) /**< (UART2) Interrupt Disable Register */
#define REG_UART2_IMR (0x400E1A10) /**< (UART2) Interrupt Mask Register */
#define REG_UART2_SR (0x400E1A14) /**< (UART2) Status Register */
#define REG_UART2_RHR (0x400E1A18) /**< (UART2) Receive Holding Register */
#define REG_UART2_THR (0x400E1A1C) /**< (UART2) Transmit Holding Register */
#define REG_UART2_BRGR (0x400E1A20) /**< (UART2) Baud Rate Generator Register */
#define REG_UART2_CMPR (0x400E1A24) /**< (UART2) Comparison Register */
#define REG_UART2_WPMR (0x400E1AE4) /**< (UART2) Write Protection Mode Register */
#else
#define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< (UART2) Control Register */
#define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< (UART2) Mode Register */
#define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< (UART2) Interrupt Enable Register */
#define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< (UART2) Interrupt Disable Register */
#define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< (UART2) Interrupt Mask Register */
#define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< (UART2) Status Register */
#define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< (UART2) Receive Holding Register */
#define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< (UART2) Transmit Holding Register */
#define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< (UART2) Baud Rate Generator Register */
#define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< (UART2) Comparison Register */
#define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< (UART2) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for UART2 peripheral ========== */
#define UART2_INSTANCE_ID 44
#define UART2_CLOCK_ID 44
#define UART2_DMAC_ID_TX 24
#define UART2_DMAC_ID_RX 25
#endif /* _SAME70_UART2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UART3
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART3_INSTANCE_H_
#define _SAME70_UART3_INSTANCE_H_
/* ========== Register definition for UART3 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART3_CR (0x400E1C00) /**< (UART3) Control Register */
#define REG_UART3_MR (0x400E1C04) /**< (UART3) Mode Register */
#define REG_UART3_IER (0x400E1C08) /**< (UART3) Interrupt Enable Register */
#define REG_UART3_IDR (0x400E1C0C) /**< (UART3) Interrupt Disable Register */
#define REG_UART3_IMR (0x400E1C10) /**< (UART3) Interrupt Mask Register */
#define REG_UART3_SR (0x400E1C14) /**< (UART3) Status Register */
#define REG_UART3_RHR (0x400E1C18) /**< (UART3) Receive Holding Register */
#define REG_UART3_THR (0x400E1C1C) /**< (UART3) Transmit Holding Register */
#define REG_UART3_BRGR (0x400E1C20) /**< (UART3) Baud Rate Generator Register */
#define REG_UART3_CMPR (0x400E1C24) /**< (UART3) Comparison Register */
#define REG_UART3_WPMR (0x400E1CE4) /**< (UART3) Write Protection Mode Register */
#else
#define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< (UART3) Control Register */
#define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< (UART3) Mode Register */
#define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< (UART3) Interrupt Enable Register */
#define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< (UART3) Interrupt Disable Register */
#define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< (UART3) Interrupt Mask Register */
#define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< (UART3) Status Register */
#define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< (UART3) Receive Holding Register */
#define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< (UART3) Transmit Holding Register */
#define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< (UART3) Baud Rate Generator Register */
#define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< (UART3) Comparison Register */
#define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< (UART3) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for UART3 peripheral ========== */
#define UART3_INSTANCE_ID 45
#define UART3_CLOCK_ID 45
#define UART3_DMAC_ID_TX 26
#define UART3_DMAC_ID_RX 27
#endif /* _SAME70_UART3_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UART4
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UART4_INSTANCE_H_
#define _SAME70_UART4_INSTANCE_H_
/* ========== Register definition for UART4 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART4_CR (0x400E1E00) /**< (UART4) Control Register */
#define REG_UART4_MR (0x400E1E04) /**< (UART4) Mode Register */
#define REG_UART4_IER (0x400E1E08) /**< (UART4) Interrupt Enable Register */
#define REG_UART4_IDR (0x400E1E0C) /**< (UART4) Interrupt Disable Register */
#define REG_UART4_IMR (0x400E1E10) /**< (UART4) Interrupt Mask Register */
#define REG_UART4_SR (0x400E1E14) /**< (UART4) Status Register */
#define REG_UART4_RHR (0x400E1E18) /**< (UART4) Receive Holding Register */
#define REG_UART4_THR (0x400E1E1C) /**< (UART4) Transmit Holding Register */
#define REG_UART4_BRGR (0x400E1E20) /**< (UART4) Baud Rate Generator Register */
#define REG_UART4_CMPR (0x400E1E24) /**< (UART4) Comparison Register */
#define REG_UART4_WPMR (0x400E1EE4) /**< (UART4) Write Protection Mode Register */
#else
#define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< (UART4) Control Register */
#define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< (UART4) Mode Register */
#define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< (UART4) Interrupt Enable Register */
#define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< (UART4) Interrupt Disable Register */
#define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< (UART4) Interrupt Mask Register */
#define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< (UART4) Status Register */
#define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< (UART4) Receive Holding Register */
#define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< (UART4) Transmit Holding Register */
#define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< (UART4) Baud Rate Generator Register */
#define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< (UART4) Comparison Register */
#define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< (UART4) Write Protection Mode Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for UART4 peripheral ========== */
#define UART4_INSTANCE_ID 46
#define UART4_CLOCK_ID 46
#define UART4_DMAC_ID_TX 28
#define UART4_DMAC_ID_RX 29
#endif /* _SAME70_UART4_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for USART0
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_USART0_INSTANCE_H_
#define _SAME70_USART0_INSTANCE_H_
/* ========== Register definition for USART0 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USART0_US_CR (0x40024000) /**< (USART0) Control Register */
#define REG_USART0_US_MR (0x40024004) /**< (USART0) Mode Register */
#define REG_USART0_US_IER (0x40024008) /**< (USART0) Interrupt Enable Register */
#define REG_USART0_US_IDR (0x4002400C) /**< (USART0) Interrupt Disable Register */
#define REG_USART0_US_IMR (0x40024010) /**< (USART0) Interrupt Mask Register */
#define REG_USART0_US_CSR (0x40024014) /**< (USART0) Channel Status Register */
#define REG_USART0_US_RHR (0x40024018) /**< (USART0) Receive Holding Register */
#define REG_USART0_US_THR (0x4002401C) /**< (USART0) Transmit Holding Register */
#define REG_USART0_US_BRGR (0x40024020) /**< (USART0) Baud Rate Generator Register */
#define REG_USART0_US_RTOR (0x40024024) /**< (USART0) Receiver Time-out Register */
#define REG_USART0_US_TTGR (0x40024028) /**< (USART0) Transmitter Timeguard Register */
#define REG_USART0_US_FIDI (0x40024040) /**< (USART0) FI DI Ratio Register */
#define REG_USART0_US_NER (0x40024044) /**< (USART0) Number of Errors Register */
#define REG_USART0_US_IF (0x4002404C) /**< (USART0) IrDA Filter Register */
#define REG_USART0_US_MAN (0x40024050) /**< (USART0) Manchester Configuration Register */
#define REG_USART0_US_LINMR (0x40024054) /**< (USART0) LIN Mode Register */
#define REG_USART0_US_LINIR (0x40024058) /**< (USART0) LIN Identifier Register */
#define REG_USART0_US_LINBRR (0x4002405C) /**< (USART0) LIN Baud Rate Register */
#define REG_USART0_US_LONMR (0x40024060) /**< (USART0) LON Mode Register */
#define REG_USART0_US_LONPR (0x40024064) /**< (USART0) LON Preamble Register */
#define REG_USART0_US_LONDL (0x40024068) /**< (USART0) LON Data Length Register */
#define REG_USART0_US_LONL2HDR (0x4002406C) /**< (USART0) LON L2HDR Register */
#define REG_USART0_US_LONBL (0x40024070) /**< (USART0) LON Backlog Register */
#define REG_USART0_US_LONB1TX (0x40024074) /**< (USART0) LON Beta1 Tx Register */
#define REG_USART0_US_LONB1RX (0x40024078) /**< (USART0) LON Beta1 Rx Register */
#define REG_USART0_US_LONPRIO (0x4002407C) /**< (USART0) LON Priority Register */
#define REG_USART0_US_IDTTX (0x40024080) /**< (USART0) LON IDT Tx Register */
#define REG_USART0_US_IDTRX (0x40024084) /**< (USART0) LON IDT Rx Register */
#define REG_USART0_US_ICDIFF (0x40024088) /**< (USART0) IC DIFF Register */
#define REG_USART0_US_WPMR (0x400240E4) /**< (USART0) Write Protection Mode Register */
#define REG_USART0_US_WPSR (0x400240E8) /**< (USART0) Write Protection Status Register */
#else
#define REG_USART0_US_CR (*(__O uint32_t*)0x40024000U) /**< (USART0) Control Register */
#define REG_USART0_US_MR (*(__IO uint32_t*)0x40024004U) /**< (USART0) Mode Register */
#define REG_USART0_US_IER (*(__O uint32_t*)0x40024008U) /**< (USART0) Interrupt Enable Register */
#define REG_USART0_US_IDR (*(__O uint32_t*)0x4002400CU) /**< (USART0) Interrupt Disable Register */
#define REG_USART0_US_IMR (*(__I uint32_t*)0x40024010U) /**< (USART0) Interrupt Mask Register */
#define REG_USART0_US_CSR (*(__I uint32_t*)0x40024014U) /**< (USART0) Channel Status Register */
#define REG_USART0_US_RHR (*(__I uint32_t*)0x40024018U) /**< (USART0) Receive Holding Register */
#define REG_USART0_US_THR (*(__O uint32_t*)0x4002401CU) /**< (USART0) Transmit Holding Register */
#define REG_USART0_US_BRGR (*(__IO uint32_t*)0x40024020U) /**< (USART0) Baud Rate Generator Register */
#define REG_USART0_US_RTOR (*(__IO uint32_t*)0x40024024U) /**< (USART0) Receiver Time-out Register */
#define REG_USART0_US_TTGR (*(__IO uint32_t*)0x40024028U) /**< (USART0) Transmitter Timeguard Register */
#define REG_USART0_US_FIDI (*(__IO uint32_t*)0x40024040U) /**< (USART0) FI DI Ratio Register */
#define REG_USART0_US_NER (*(__I uint32_t*)0x40024044U) /**< (USART0) Number of Errors Register */
#define REG_USART0_US_IF (*(__IO uint32_t*)0x4002404CU) /**< (USART0) IrDA Filter Register */
#define REG_USART0_US_MAN (*(__IO uint32_t*)0x40024050U) /**< (USART0) Manchester Configuration Register */
#define REG_USART0_US_LINMR (*(__IO uint32_t*)0x40024054U) /**< (USART0) LIN Mode Register */
#define REG_USART0_US_LINIR (*(__IO uint32_t*)0x40024058U) /**< (USART0) LIN Identifier Register */
#define REG_USART0_US_LINBRR (*(__I uint32_t*)0x4002405CU) /**< (USART0) LIN Baud Rate Register */
#define REG_USART0_US_LONMR (*(__IO uint32_t*)0x40024060U) /**< (USART0) LON Mode Register */
#define REG_USART0_US_LONPR (*(__IO uint32_t*)0x40024064U) /**< (USART0) LON Preamble Register */
#define REG_USART0_US_LONDL (*(__IO uint32_t*)0x40024068U) /**< (USART0) LON Data Length Register */
#define REG_USART0_US_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< (USART0) LON L2HDR Register */
#define REG_USART0_US_LONBL (*(__I uint32_t*)0x40024070U) /**< (USART0) LON Backlog Register */
#define REG_USART0_US_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< (USART0) LON Beta1 Tx Register */
#define REG_USART0_US_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< (USART0) LON Beta1 Rx Register */
#define REG_USART0_US_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< (USART0) LON Priority Register */
#define REG_USART0_US_IDTTX (*(__IO uint32_t*)0x40024080U) /**< (USART0) LON IDT Tx Register */
#define REG_USART0_US_IDTRX (*(__IO uint32_t*)0x40024084U) /**< (USART0) LON IDT Rx Register */
#define REG_USART0_US_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< (USART0) IC DIFF Register */
#define REG_USART0_US_WPMR (*(__IO uint32_t*)0x400240E4U) /**< (USART0) Write Protection Mode Register */
#define REG_USART0_US_WPSR (*(__I uint32_t*)0x400240E8U) /**< (USART0) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for USART0 peripheral ========== */
#define USART0_INSTANCE_ID 13
#define USART0_CLOCK_ID 13
#define USART0_DMAC_ID_TX 7
#define USART0_DMAC_ID_RX 8
#endif /* _SAME70_USART0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for USART1
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_USART1_INSTANCE_H_
#define _SAME70_USART1_INSTANCE_H_
/* ========== Register definition for USART1 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USART1_US_CR (0x40028000) /**< (USART1) Control Register */
#define REG_USART1_US_MR (0x40028004) /**< (USART1) Mode Register */
#define REG_USART1_US_IER (0x40028008) /**< (USART1) Interrupt Enable Register */
#define REG_USART1_US_IDR (0x4002800C) /**< (USART1) Interrupt Disable Register */
#define REG_USART1_US_IMR (0x40028010) /**< (USART1) Interrupt Mask Register */
#define REG_USART1_US_CSR (0x40028014) /**< (USART1) Channel Status Register */
#define REG_USART1_US_RHR (0x40028018) /**< (USART1) Receive Holding Register */
#define REG_USART1_US_THR (0x4002801C) /**< (USART1) Transmit Holding Register */
#define REG_USART1_US_BRGR (0x40028020) /**< (USART1) Baud Rate Generator Register */
#define REG_USART1_US_RTOR (0x40028024) /**< (USART1) Receiver Time-out Register */
#define REG_USART1_US_TTGR (0x40028028) /**< (USART1) Transmitter Timeguard Register */
#define REG_USART1_US_FIDI (0x40028040) /**< (USART1) FI DI Ratio Register */
#define REG_USART1_US_NER (0x40028044) /**< (USART1) Number of Errors Register */
#define REG_USART1_US_IF (0x4002804C) /**< (USART1) IrDA Filter Register */
#define REG_USART1_US_MAN (0x40028050) /**< (USART1) Manchester Configuration Register */
#define REG_USART1_US_LINMR (0x40028054) /**< (USART1) LIN Mode Register */
#define REG_USART1_US_LINIR (0x40028058) /**< (USART1) LIN Identifier Register */
#define REG_USART1_US_LINBRR (0x4002805C) /**< (USART1) LIN Baud Rate Register */
#define REG_USART1_US_LONMR (0x40028060) /**< (USART1) LON Mode Register */
#define REG_USART1_US_LONPR (0x40028064) /**< (USART1) LON Preamble Register */
#define REG_USART1_US_LONDL (0x40028068) /**< (USART1) LON Data Length Register */
#define REG_USART1_US_LONL2HDR (0x4002806C) /**< (USART1) LON L2HDR Register */
#define REG_USART1_US_LONBL (0x40028070) /**< (USART1) LON Backlog Register */
#define REG_USART1_US_LONB1TX (0x40028074) /**< (USART1) LON Beta1 Tx Register */
#define REG_USART1_US_LONB1RX (0x40028078) /**< (USART1) LON Beta1 Rx Register */
#define REG_USART1_US_LONPRIO (0x4002807C) /**< (USART1) LON Priority Register */
#define REG_USART1_US_IDTTX (0x40028080) /**< (USART1) LON IDT Tx Register */
#define REG_USART1_US_IDTRX (0x40028084) /**< (USART1) LON IDT Rx Register */
#define REG_USART1_US_ICDIFF (0x40028088) /**< (USART1) IC DIFF Register */
#define REG_USART1_US_WPMR (0x400280E4) /**< (USART1) Write Protection Mode Register */
#define REG_USART1_US_WPSR (0x400280E8) /**< (USART1) Write Protection Status Register */
#else
#define REG_USART1_US_CR (*(__O uint32_t*)0x40028000U) /**< (USART1) Control Register */
#define REG_USART1_US_MR (*(__IO uint32_t*)0x40028004U) /**< (USART1) Mode Register */
#define REG_USART1_US_IER (*(__O uint32_t*)0x40028008U) /**< (USART1) Interrupt Enable Register */
#define REG_USART1_US_IDR (*(__O uint32_t*)0x4002800CU) /**< (USART1) Interrupt Disable Register */
#define REG_USART1_US_IMR (*(__I uint32_t*)0x40028010U) /**< (USART1) Interrupt Mask Register */
#define REG_USART1_US_CSR (*(__I uint32_t*)0x40028014U) /**< (USART1) Channel Status Register */
#define REG_USART1_US_RHR (*(__I uint32_t*)0x40028018U) /**< (USART1) Receive Holding Register */
#define REG_USART1_US_THR (*(__O uint32_t*)0x4002801CU) /**< (USART1) Transmit Holding Register */
#define REG_USART1_US_BRGR (*(__IO uint32_t*)0x40028020U) /**< (USART1) Baud Rate Generator Register */
#define REG_USART1_US_RTOR (*(__IO uint32_t*)0x40028024U) /**< (USART1) Receiver Time-out Register */
#define REG_USART1_US_TTGR (*(__IO uint32_t*)0x40028028U) /**< (USART1) Transmitter Timeguard Register */
#define REG_USART1_US_FIDI (*(__IO uint32_t*)0x40028040U) /**< (USART1) FI DI Ratio Register */
#define REG_USART1_US_NER (*(__I uint32_t*)0x40028044U) /**< (USART1) Number of Errors Register */
#define REG_USART1_US_IF (*(__IO uint32_t*)0x4002804CU) /**< (USART1) IrDA Filter Register */
#define REG_USART1_US_MAN (*(__IO uint32_t*)0x40028050U) /**< (USART1) Manchester Configuration Register */
#define REG_USART1_US_LINMR (*(__IO uint32_t*)0x40028054U) /**< (USART1) LIN Mode Register */
#define REG_USART1_US_LINIR (*(__IO uint32_t*)0x40028058U) /**< (USART1) LIN Identifier Register */
#define REG_USART1_US_LINBRR (*(__I uint32_t*)0x4002805CU) /**< (USART1) LIN Baud Rate Register */
#define REG_USART1_US_LONMR (*(__IO uint32_t*)0x40028060U) /**< (USART1) LON Mode Register */
#define REG_USART1_US_LONPR (*(__IO uint32_t*)0x40028064U) /**< (USART1) LON Preamble Register */
#define REG_USART1_US_LONDL (*(__IO uint32_t*)0x40028068U) /**< (USART1) LON Data Length Register */
#define REG_USART1_US_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< (USART1) LON L2HDR Register */
#define REG_USART1_US_LONBL (*(__I uint32_t*)0x40028070U) /**< (USART1) LON Backlog Register */
#define REG_USART1_US_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< (USART1) LON Beta1 Tx Register */
#define REG_USART1_US_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< (USART1) LON Beta1 Rx Register */
#define REG_USART1_US_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< (USART1) LON Priority Register */
#define REG_USART1_US_IDTTX (*(__IO uint32_t*)0x40028080U) /**< (USART1) LON IDT Tx Register */
#define REG_USART1_US_IDTRX (*(__IO uint32_t*)0x40028084U) /**< (USART1) LON IDT Rx Register */
#define REG_USART1_US_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< (USART1) IC DIFF Register */
#define REG_USART1_US_WPMR (*(__IO uint32_t*)0x400280E4U) /**< (USART1) Write Protection Mode Register */
#define REG_USART1_US_WPSR (*(__I uint32_t*)0x400280E8U) /**< (USART1) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for USART1 peripheral ========== */
#define USART1_INSTANCE_ID 14
#define USART1_CLOCK_ID 14
#define USART1_DMAC_ID_TX 9
#define USART1_DMAC_ID_RX 10
#endif /* _SAME70_USART1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for USART2
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_USART2_INSTANCE_H_
#define _SAME70_USART2_INSTANCE_H_
/* ========== Register definition for USART2 peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USART2_US_CR (0x4002C000) /**< (USART2) Control Register */
#define REG_USART2_US_MR (0x4002C004) /**< (USART2) Mode Register */
#define REG_USART2_US_IER (0x4002C008) /**< (USART2) Interrupt Enable Register */
#define REG_USART2_US_IDR (0x4002C00C) /**< (USART2) Interrupt Disable Register */
#define REG_USART2_US_IMR (0x4002C010) /**< (USART2) Interrupt Mask Register */
#define REG_USART2_US_CSR (0x4002C014) /**< (USART2) Channel Status Register */
#define REG_USART2_US_RHR (0x4002C018) /**< (USART2) Receive Holding Register */
#define REG_USART2_US_THR (0x4002C01C) /**< (USART2) Transmit Holding Register */
#define REG_USART2_US_BRGR (0x4002C020) /**< (USART2) Baud Rate Generator Register */
#define REG_USART2_US_RTOR (0x4002C024) /**< (USART2) Receiver Time-out Register */
#define REG_USART2_US_TTGR (0x4002C028) /**< (USART2) Transmitter Timeguard Register */
#define REG_USART2_US_FIDI (0x4002C040) /**< (USART2) FI DI Ratio Register */
#define REG_USART2_US_NER (0x4002C044) /**< (USART2) Number of Errors Register */
#define REG_USART2_US_IF (0x4002C04C) /**< (USART2) IrDA Filter Register */
#define REG_USART2_US_MAN (0x4002C050) /**< (USART2) Manchester Configuration Register */
#define REG_USART2_US_LINMR (0x4002C054) /**< (USART2) LIN Mode Register */
#define REG_USART2_US_LINIR (0x4002C058) /**< (USART2) LIN Identifier Register */
#define REG_USART2_US_LINBRR (0x4002C05C) /**< (USART2) LIN Baud Rate Register */
#define REG_USART2_US_LONMR (0x4002C060) /**< (USART2) LON Mode Register */
#define REG_USART2_US_LONPR (0x4002C064) /**< (USART2) LON Preamble Register */
#define REG_USART2_US_LONDL (0x4002C068) /**< (USART2) LON Data Length Register */
#define REG_USART2_US_LONL2HDR (0x4002C06C) /**< (USART2) LON L2HDR Register */
#define REG_USART2_US_LONBL (0x4002C070) /**< (USART2) LON Backlog Register */
#define REG_USART2_US_LONB1TX (0x4002C074) /**< (USART2) LON Beta1 Tx Register */
#define REG_USART2_US_LONB1RX (0x4002C078) /**< (USART2) LON Beta1 Rx Register */
#define REG_USART2_US_LONPRIO (0x4002C07C) /**< (USART2) LON Priority Register */
#define REG_USART2_US_IDTTX (0x4002C080) /**< (USART2) LON IDT Tx Register */
#define REG_USART2_US_IDTRX (0x4002C084) /**< (USART2) LON IDT Rx Register */
#define REG_USART2_US_ICDIFF (0x4002C088) /**< (USART2) IC DIFF Register */
#define REG_USART2_US_WPMR (0x4002C0E4) /**< (USART2) Write Protection Mode Register */
#define REG_USART2_US_WPSR (0x4002C0E8) /**< (USART2) Write Protection Status Register */
#else
#define REG_USART2_US_CR (*(__O uint32_t*)0x4002C000U) /**< (USART2) Control Register */
#define REG_USART2_US_MR (*(__IO uint32_t*)0x4002C004U) /**< (USART2) Mode Register */
#define REG_USART2_US_IER (*(__O uint32_t*)0x4002C008U) /**< (USART2) Interrupt Enable Register */
#define REG_USART2_US_IDR (*(__O uint32_t*)0x4002C00CU) /**< (USART2) Interrupt Disable Register */
#define REG_USART2_US_IMR (*(__I uint32_t*)0x4002C010U) /**< (USART2) Interrupt Mask Register */
#define REG_USART2_US_CSR (*(__I uint32_t*)0x4002C014U) /**< (USART2) Channel Status Register */
#define REG_USART2_US_RHR (*(__I uint32_t*)0x4002C018U) /**< (USART2) Receive Holding Register */
#define REG_USART2_US_THR (*(__O uint32_t*)0x4002C01CU) /**< (USART2) Transmit Holding Register */
#define REG_USART2_US_BRGR (*(__IO uint32_t*)0x4002C020U) /**< (USART2) Baud Rate Generator Register */
#define REG_USART2_US_RTOR (*(__IO uint32_t*)0x4002C024U) /**< (USART2) Receiver Time-out Register */
#define REG_USART2_US_TTGR (*(__IO uint32_t*)0x4002C028U) /**< (USART2) Transmitter Timeguard Register */
#define REG_USART2_US_FIDI (*(__IO uint32_t*)0x4002C040U) /**< (USART2) FI DI Ratio Register */
#define REG_USART2_US_NER (*(__I uint32_t*)0x4002C044U) /**< (USART2) Number of Errors Register */
#define REG_USART2_US_IF (*(__IO uint32_t*)0x4002C04CU) /**< (USART2) IrDA Filter Register */
#define REG_USART2_US_MAN (*(__IO uint32_t*)0x4002C050U) /**< (USART2) Manchester Configuration Register */
#define REG_USART2_US_LINMR (*(__IO uint32_t*)0x4002C054U) /**< (USART2) LIN Mode Register */
#define REG_USART2_US_LINIR (*(__IO uint32_t*)0x4002C058U) /**< (USART2) LIN Identifier Register */
#define REG_USART2_US_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< (USART2) LIN Baud Rate Register */
#define REG_USART2_US_LONMR (*(__IO uint32_t*)0x4002C060U) /**< (USART2) LON Mode Register */
#define REG_USART2_US_LONPR (*(__IO uint32_t*)0x4002C064U) /**< (USART2) LON Preamble Register */
#define REG_USART2_US_LONDL (*(__IO uint32_t*)0x4002C068U) /**< (USART2) LON Data Length Register */
#define REG_USART2_US_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< (USART2) LON L2HDR Register */
#define REG_USART2_US_LONBL (*(__I uint32_t*)0x4002C070U) /**< (USART2) LON Backlog Register */
#define REG_USART2_US_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< (USART2) LON Beta1 Tx Register */
#define REG_USART2_US_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< (USART2) LON Beta1 Rx Register */
#define REG_USART2_US_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< (USART2) LON Priority Register */
#define REG_USART2_US_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< (USART2) LON IDT Tx Register */
#define REG_USART2_US_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< (USART2) LON IDT Rx Register */
#define REG_USART2_US_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< (USART2) IC DIFF Register */
#define REG_USART2_US_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< (USART2) Write Protection Mode Register */
#define REG_USART2_US_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< (USART2) Write Protection Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for USART2 peripheral ========== */
#define USART2_INSTANCE_ID 15
#define USART2_CLOCK_ID 15
#define USART2_DMAC_ID_TX 11
#define USART2_DMAC_ID_RX 12
#endif /* _SAME70_USART2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for USBHS
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_USBHS_INSTANCE_H_
#define _SAME70_USBHS_INSTANCE_H_
/* ========== Register definition for USBHS peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USBHS_DEVDMANXTDSC0 (0x40038310) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 0 */
#define REG_USBHS_DEVDMAADDRESS0 (0x40038314) /**< (USBHS) Device DMA Channel Address Register (n = 1) 0 */
#define REG_USBHS_DEVDMACONTROL0 (0x40038318) /**< (USBHS) Device DMA Channel Control Register (n = 1) 0 */
#define REG_USBHS_DEVDMASTATUS0 (0x4003831C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 0 */
#define REG_USBHS_DEVDMANXTDSC1 (0x40038320) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 1 */
#define REG_USBHS_DEVDMAADDRESS1 (0x40038324) /**< (USBHS) Device DMA Channel Address Register (n = 1) 1 */
#define REG_USBHS_DEVDMACONTROL1 (0x40038328) /**< (USBHS) Device DMA Channel Control Register (n = 1) 1 */
#define REG_USBHS_DEVDMASTATUS1 (0x4003832C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 1 */
#define REG_USBHS_DEVDMANXTDSC2 (0x40038330) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 2 */
#define REG_USBHS_DEVDMAADDRESS2 (0x40038334) /**< (USBHS) Device DMA Channel Address Register (n = 1) 2 */
#define REG_USBHS_DEVDMACONTROL2 (0x40038338) /**< (USBHS) Device DMA Channel Control Register (n = 1) 2 */
#define REG_USBHS_DEVDMASTATUS2 (0x4003833C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 2 */
#define REG_USBHS_DEVDMANXTDSC3 (0x40038340) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 3 */
#define REG_USBHS_DEVDMAADDRESS3 (0x40038344) /**< (USBHS) Device DMA Channel Address Register (n = 1) 3 */
#define REG_USBHS_DEVDMACONTROL3 (0x40038348) /**< (USBHS) Device DMA Channel Control Register (n = 1) 3 */
#define REG_USBHS_DEVDMASTATUS3 (0x4003834C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 3 */
#define REG_USBHS_DEVDMANXTDSC4 (0x40038350) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 4 */
#define REG_USBHS_DEVDMAADDRESS4 (0x40038354) /**< (USBHS) Device DMA Channel Address Register (n = 1) 4 */
#define REG_USBHS_DEVDMACONTROL4 (0x40038358) /**< (USBHS) Device DMA Channel Control Register (n = 1) 4 */
#define REG_USBHS_DEVDMASTATUS4 (0x4003835C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 4 */
#define REG_USBHS_DEVDMANXTDSC5 (0x40038360) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 5 */
#define REG_USBHS_DEVDMAADDRESS5 (0x40038364) /**< (USBHS) Device DMA Channel Address Register (n = 1) 5 */
#define REG_USBHS_DEVDMACONTROL5 (0x40038368) /**< (USBHS) Device DMA Channel Control Register (n = 1) 5 */
#define REG_USBHS_DEVDMASTATUS5 (0x4003836C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 5 */
#define REG_USBHS_DEVDMANXTDSC6 (0x40038370) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 6 */
#define REG_USBHS_DEVDMAADDRESS6 (0x40038374) /**< (USBHS) Device DMA Channel Address Register (n = 1) 6 */
#define REG_USBHS_DEVDMACONTROL6 (0x40038378) /**< (USBHS) Device DMA Channel Control Register (n = 1) 6 */
#define REG_USBHS_DEVDMASTATUS6 (0x4003837C) /**< (USBHS) Device DMA Channel Status Register (n = 1) 6 */
#define REG_USBHS_HSTDMANXTDSC0 (0x40038710) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 0 */
#define REG_USBHS_HSTDMAADDRESS0 (0x40038714) /**< (USBHS) Host DMA Channel Address Register (n = 1) 0 */
#define REG_USBHS_HSTDMACONTROL0 (0x40038718) /**< (USBHS) Host DMA Channel Control Register (n = 1) 0 */
#define REG_USBHS_HSTDMASTATUS0 (0x4003871C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 0 */
#define REG_USBHS_HSTDMANXTDSC1 (0x40038720) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 1 */
#define REG_USBHS_HSTDMAADDRESS1 (0x40038724) /**< (USBHS) Host DMA Channel Address Register (n = 1) 1 */
#define REG_USBHS_HSTDMACONTROL1 (0x40038728) /**< (USBHS) Host DMA Channel Control Register (n = 1) 1 */
#define REG_USBHS_HSTDMASTATUS1 (0x4003872C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 1 */
#define REG_USBHS_HSTDMANXTDSC2 (0x40038730) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 2 */
#define REG_USBHS_HSTDMAADDRESS2 (0x40038734) /**< (USBHS) Host DMA Channel Address Register (n = 1) 2 */
#define REG_USBHS_HSTDMACONTROL2 (0x40038738) /**< (USBHS) Host DMA Channel Control Register (n = 1) 2 */
#define REG_USBHS_HSTDMASTATUS2 (0x4003873C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 2 */
#define REG_USBHS_HSTDMANXTDSC3 (0x40038740) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 3 */
#define REG_USBHS_HSTDMAADDRESS3 (0x40038744) /**< (USBHS) Host DMA Channel Address Register (n = 1) 3 */
#define REG_USBHS_HSTDMACONTROL3 (0x40038748) /**< (USBHS) Host DMA Channel Control Register (n = 1) 3 */
#define REG_USBHS_HSTDMASTATUS3 (0x4003874C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 3 */
#define REG_USBHS_HSTDMANXTDSC4 (0x40038750) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 4 */
#define REG_USBHS_HSTDMAADDRESS4 (0x40038754) /**< (USBHS) Host DMA Channel Address Register (n = 1) 4 */
#define REG_USBHS_HSTDMACONTROL4 (0x40038758) /**< (USBHS) Host DMA Channel Control Register (n = 1) 4 */
#define REG_USBHS_HSTDMASTATUS4 (0x4003875C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 4 */
#define REG_USBHS_HSTDMANXTDSC5 (0x40038760) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 5 */
#define REG_USBHS_HSTDMAADDRESS5 (0x40038764) /**< (USBHS) Host DMA Channel Address Register (n = 1) 5 */
#define REG_USBHS_HSTDMACONTROL5 (0x40038768) /**< (USBHS) Host DMA Channel Control Register (n = 1) 5 */
#define REG_USBHS_HSTDMASTATUS5 (0x4003876C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 5 */
#define REG_USBHS_HSTDMANXTDSC6 (0x40038770) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 6 */
#define REG_USBHS_HSTDMAADDRESS6 (0x40038774) /**< (USBHS) Host DMA Channel Address Register (n = 1) 6 */
#define REG_USBHS_HSTDMACONTROL6 (0x40038778) /**< (USBHS) Host DMA Channel Control Register (n = 1) 6 */
#define REG_USBHS_HSTDMASTATUS6 (0x4003877C) /**< (USBHS) Host DMA Channel Status Register (n = 1) 6 */
#define REG_USBHS_DEVCTRL (0x40038000) /**< (USBHS) Device General Control Register */
#define REG_USBHS_DEVISR (0x40038004) /**< (USBHS) Device Global Interrupt Status Register */
#define REG_USBHS_DEVICR (0x40038008) /**< (USBHS) Device Global Interrupt Clear Register */
#define REG_USBHS_DEVIFR (0x4003800C) /**< (USBHS) Device Global Interrupt Set Register */
#define REG_USBHS_DEVIMR (0x40038010) /**< (USBHS) Device Global Interrupt Mask Register */
#define REG_USBHS_DEVIDR (0x40038014) /**< (USBHS) Device Global Interrupt Disable Register */
#define REG_USBHS_DEVIER (0x40038018) /**< (USBHS) Device Global Interrupt Enable Register */
#define REG_USBHS_DEVEPT (0x4003801C) /**< (USBHS) Device Endpoint Register */
#define REG_USBHS_DEVFNUM (0x40038020) /**< (USBHS) Device Frame Number Register */
#define REG_USBHS_DEVEPTCFG (0x40038100) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */
#define REG_USBHS_DEVEPTCFG0 (0x40038100) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */
#define REG_USBHS_DEVEPTCFG1 (0x40038104) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 1 */
#define REG_USBHS_DEVEPTCFG2 (0x40038108) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 2 */
#define REG_USBHS_DEVEPTCFG3 (0x4003810C) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 3 */
#define REG_USBHS_DEVEPTCFG4 (0x40038110) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 4 */
#define REG_USBHS_DEVEPTCFG5 (0x40038114) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 5 */
#define REG_USBHS_DEVEPTCFG6 (0x40038118) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 6 */
#define REG_USBHS_DEVEPTCFG7 (0x4003811C) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 7 */
#define REG_USBHS_DEVEPTCFG8 (0x40038120) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 8 */
#define REG_USBHS_DEVEPTCFG9 (0x40038124) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 9 */
#define REG_USBHS_DEVEPTISR (0x40038130) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */
#define REG_USBHS_DEVEPTISR0 (0x40038130) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */
#define REG_USBHS_DEVEPTISR1 (0x40038134) /**< (USBHS) Device Endpoint Status Register (n = 0) 1 */
#define REG_USBHS_DEVEPTISR2 (0x40038138) /**< (USBHS) Device Endpoint Status Register (n = 0) 2 */
#define REG_USBHS_DEVEPTISR3 (0x4003813C) /**< (USBHS) Device Endpoint Status Register (n = 0) 3 */
#define REG_USBHS_DEVEPTISR4 (0x40038140) /**< (USBHS) Device Endpoint Status Register (n = 0) 4 */
#define REG_USBHS_DEVEPTISR5 (0x40038144) /**< (USBHS) Device Endpoint Status Register (n = 0) 5 */
#define REG_USBHS_DEVEPTISR6 (0x40038148) /**< (USBHS) Device Endpoint Status Register (n = 0) 6 */
#define REG_USBHS_DEVEPTISR7 (0x4003814C) /**< (USBHS) Device Endpoint Status Register (n = 0) 7 */
#define REG_USBHS_DEVEPTISR8 (0x40038150) /**< (USBHS) Device Endpoint Status Register (n = 0) 8 */
#define REG_USBHS_DEVEPTISR9 (0x40038154) /**< (USBHS) Device Endpoint Status Register (n = 0) 9 */
#define REG_USBHS_DEVEPTICR (0x40038160) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */
#define REG_USBHS_DEVEPTICR0 (0x40038160) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */
#define REG_USBHS_DEVEPTICR1 (0x40038164) /**< (USBHS) Device Endpoint Clear Register (n = 0) 1 */
#define REG_USBHS_DEVEPTICR2 (0x40038168) /**< (USBHS) Device Endpoint Clear Register (n = 0) 2 */
#define REG_USBHS_DEVEPTICR3 (0x4003816C) /**< (USBHS) Device Endpoint Clear Register (n = 0) 3 */
#define REG_USBHS_DEVEPTICR4 (0x40038170) /**< (USBHS) Device Endpoint Clear Register (n = 0) 4 */
#define REG_USBHS_DEVEPTICR5 (0x40038174) /**< (USBHS) Device Endpoint Clear Register (n = 0) 5 */
#define REG_USBHS_DEVEPTICR6 (0x40038178) /**< (USBHS) Device Endpoint Clear Register (n = 0) 6 */
#define REG_USBHS_DEVEPTICR7 (0x4003817C) /**< (USBHS) Device Endpoint Clear Register (n = 0) 7 */
#define REG_USBHS_DEVEPTICR8 (0x40038180) /**< (USBHS) Device Endpoint Clear Register (n = 0) 8 */
#define REG_USBHS_DEVEPTICR9 (0x40038184) /**< (USBHS) Device Endpoint Clear Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIFR (0x40038190) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIFR0 (0x40038190) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIFR1 (0x40038194) /**< (USBHS) Device Endpoint Set Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIFR2 (0x40038198) /**< (USBHS) Device Endpoint Set Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIFR3 (0x4003819C) /**< (USBHS) Device Endpoint Set Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIFR4 (0x400381A0) /**< (USBHS) Device Endpoint Set Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIFR5 (0x400381A4) /**< (USBHS) Device Endpoint Set Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIFR6 (0x400381A8) /**< (USBHS) Device Endpoint Set Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIFR7 (0x400381AC) /**< (USBHS) Device Endpoint Set Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIFR8 (0x400381B0) /**< (USBHS) Device Endpoint Set Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIFR9 (0x400381B4) /**< (USBHS) Device Endpoint Set Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIMR (0x400381C0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIMR0 (0x400381C0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIMR1 (0x400381C4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIMR2 (0x400381C8) /**< (USBHS) Device Endpoint Mask Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIMR3 (0x400381CC) /**< (USBHS) Device Endpoint Mask Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIMR4 (0x400381D0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIMR5 (0x400381D4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIMR6 (0x400381D8) /**< (USBHS) Device Endpoint Mask Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIMR7 (0x400381DC) /**< (USBHS) Device Endpoint Mask Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIMR8 (0x400381E0) /**< (USBHS) Device Endpoint Mask Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIMR9 (0x400381E4) /**< (USBHS) Device Endpoint Mask Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIER (0x400381F0) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIER0 (0x400381F0) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIER1 (0x400381F4) /**< (USBHS) Device Endpoint Enable Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIER2 (0x400381F8) /**< (USBHS) Device Endpoint Enable Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIER3 (0x400381FC) /**< (USBHS) Device Endpoint Enable Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIER4 (0x40038200) /**< (USBHS) Device Endpoint Enable Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIER5 (0x40038204) /**< (USBHS) Device Endpoint Enable Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIER6 (0x40038208) /**< (USBHS) Device Endpoint Enable Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIER7 (0x4003820C) /**< (USBHS) Device Endpoint Enable Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIER8 (0x40038210) /**< (USBHS) Device Endpoint Enable Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIER9 (0x40038214) /**< (USBHS) Device Endpoint Enable Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIDR (0x40038220) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIDR0 (0x40038220) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIDR1 (0x40038224) /**< (USBHS) Device Endpoint Disable Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIDR2 (0x40038228) /**< (USBHS) Device Endpoint Disable Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIDR3 (0x4003822C) /**< (USBHS) Device Endpoint Disable Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIDR4 (0x40038230) /**< (USBHS) Device Endpoint Disable Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIDR5 (0x40038234) /**< (USBHS) Device Endpoint Disable Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIDR6 (0x40038238) /**< (USBHS) Device Endpoint Disable Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIDR7 (0x4003823C) /**< (USBHS) Device Endpoint Disable Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIDR8 (0x40038240) /**< (USBHS) Device Endpoint Disable Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIDR9 (0x40038244) /**< (USBHS) Device Endpoint Disable Register (n = 0) 9 */
#define REG_USBHS_HSTCTRL (0x40038400) /**< (USBHS) Host General Control Register */
#define REG_USBHS_HSTISR (0x40038404) /**< (USBHS) Host Global Interrupt Status Register */
#define REG_USBHS_HSTICR (0x40038408) /**< (USBHS) Host Global Interrupt Clear Register */
#define REG_USBHS_HSTIFR (0x4003840C) /**< (USBHS) Host Global Interrupt Set Register */
#define REG_USBHS_HSTIMR (0x40038410) /**< (USBHS) Host Global Interrupt Mask Register */
#define REG_USBHS_HSTIDR (0x40038414) /**< (USBHS) Host Global Interrupt Disable Register */
#define REG_USBHS_HSTIER (0x40038418) /**< (USBHS) Host Global Interrupt Enable Register */
#define REG_USBHS_HSTPIP (0x4003841C) /**< (USBHS) Host Pipe Register */
#define REG_USBHS_HSTFNUM (0x40038420) /**< (USBHS) Host Frame Number Register */
#define REG_USBHS_HSTADDR1 (0x40038424) /**< (USBHS) Host Address 1 Register */
#define REG_USBHS_HSTADDR2 (0x40038428) /**< (USBHS) Host Address 2 Register */
#define REG_USBHS_HSTADDR3 (0x4003842C) /**< (USBHS) Host Address 3 Register */
#define REG_USBHS_HSTPIPCFG (0x40038500) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */
#define REG_USBHS_HSTPIPCFG0 (0x40038500) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */
#define REG_USBHS_HSTPIPCFG1 (0x40038504) /**< (USBHS) Host Pipe Configuration Register (n = 0) 1 */
#define REG_USBHS_HSTPIPCFG2 (0x40038508) /**< (USBHS) Host Pipe Configuration Register (n = 0) 2 */
#define REG_USBHS_HSTPIPCFG3 (0x4003850C) /**< (USBHS) Host Pipe Configuration Register (n = 0) 3 */
#define REG_USBHS_HSTPIPCFG4 (0x40038510) /**< (USBHS) Host Pipe Configuration Register (n = 0) 4 */
#define REG_USBHS_HSTPIPCFG5 (0x40038514) /**< (USBHS) Host Pipe Configuration Register (n = 0) 5 */
#define REG_USBHS_HSTPIPCFG6 (0x40038518) /**< (USBHS) Host Pipe Configuration Register (n = 0) 6 */
#define REG_USBHS_HSTPIPCFG7 (0x4003851C) /**< (USBHS) Host Pipe Configuration Register (n = 0) 7 */
#define REG_USBHS_HSTPIPCFG8 (0x40038520) /**< (USBHS) Host Pipe Configuration Register (n = 0) 8 */
#define REG_USBHS_HSTPIPCFG9 (0x40038524) /**< (USBHS) Host Pipe Configuration Register (n = 0) 9 */
#define REG_USBHS_HSTPIPISR (0x40038530) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */
#define REG_USBHS_HSTPIPISR0 (0x40038530) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */
#define REG_USBHS_HSTPIPISR1 (0x40038534) /**< (USBHS) Host Pipe Status Register (n = 0) 1 */
#define REG_USBHS_HSTPIPISR2 (0x40038538) /**< (USBHS) Host Pipe Status Register (n = 0) 2 */
#define REG_USBHS_HSTPIPISR3 (0x4003853C) /**< (USBHS) Host Pipe Status Register (n = 0) 3 */
#define REG_USBHS_HSTPIPISR4 (0x40038540) /**< (USBHS) Host Pipe Status Register (n = 0) 4 */
#define REG_USBHS_HSTPIPISR5 (0x40038544) /**< (USBHS) Host Pipe Status Register (n = 0) 5 */
#define REG_USBHS_HSTPIPISR6 (0x40038548) /**< (USBHS) Host Pipe Status Register (n = 0) 6 */
#define REG_USBHS_HSTPIPISR7 (0x4003854C) /**< (USBHS) Host Pipe Status Register (n = 0) 7 */
#define REG_USBHS_HSTPIPISR8 (0x40038550) /**< (USBHS) Host Pipe Status Register (n = 0) 8 */
#define REG_USBHS_HSTPIPISR9 (0x40038554) /**< (USBHS) Host Pipe Status Register (n = 0) 9 */
#define REG_USBHS_HSTPIPICR (0x40038560) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */
#define REG_USBHS_HSTPIPICR0 (0x40038560) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */
#define REG_USBHS_HSTPIPICR1 (0x40038564) /**< (USBHS) Host Pipe Clear Register (n = 0) 1 */
#define REG_USBHS_HSTPIPICR2 (0x40038568) /**< (USBHS) Host Pipe Clear Register (n = 0) 2 */
#define REG_USBHS_HSTPIPICR3 (0x4003856C) /**< (USBHS) Host Pipe Clear Register (n = 0) 3 */
#define REG_USBHS_HSTPIPICR4 (0x40038570) /**< (USBHS) Host Pipe Clear Register (n = 0) 4 */
#define REG_USBHS_HSTPIPICR5 (0x40038574) /**< (USBHS) Host Pipe Clear Register (n = 0) 5 */
#define REG_USBHS_HSTPIPICR6 (0x40038578) /**< (USBHS) Host Pipe Clear Register (n = 0) 6 */
#define REG_USBHS_HSTPIPICR7 (0x4003857C) /**< (USBHS) Host Pipe Clear Register (n = 0) 7 */
#define REG_USBHS_HSTPIPICR8 (0x40038580) /**< (USBHS) Host Pipe Clear Register (n = 0) 8 */
#define REG_USBHS_HSTPIPICR9 (0x40038584) /**< (USBHS) Host Pipe Clear Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIFR (0x40038590) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIFR0 (0x40038590) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIFR1 (0x40038594) /**< (USBHS) Host Pipe Set Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIFR2 (0x40038598) /**< (USBHS) Host Pipe Set Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIFR3 (0x4003859C) /**< (USBHS) Host Pipe Set Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIFR4 (0x400385A0) /**< (USBHS) Host Pipe Set Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIFR5 (0x400385A4) /**< (USBHS) Host Pipe Set Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIFR6 (0x400385A8) /**< (USBHS) Host Pipe Set Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIFR7 (0x400385AC) /**< (USBHS) Host Pipe Set Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIFR8 (0x400385B0) /**< (USBHS) Host Pipe Set Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIFR9 (0x400385B4) /**< (USBHS) Host Pipe Set Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIMR (0x400385C0) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIMR0 (0x400385C0) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIMR1 (0x400385C4) /**< (USBHS) Host Pipe Mask Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIMR2 (0x400385C8) /**< (USBHS) Host Pipe Mask Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIMR3 (0x400385CC) /**< (USBHS) Host Pipe Mask Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIMR4 (0x400385D0) /**< (USBHS) Host Pipe Mask Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIMR5 (0x400385D4) /**< (USBHS) Host Pipe Mask Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIMR6 (0x400385D8) /**< (USBHS) Host Pipe Mask Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIMR7 (0x400385DC) /**< (USBHS) Host Pipe Mask Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIMR8 (0x400385E0) /**< (USBHS) Host Pipe Mask Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIMR9 (0x400385E4) /**< (USBHS) Host Pipe Mask Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIER (0x400385F0) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIER0 (0x400385F0) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIER1 (0x400385F4) /**< (USBHS) Host Pipe Enable Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIER2 (0x400385F8) /**< (USBHS) Host Pipe Enable Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIER3 (0x400385FC) /**< (USBHS) Host Pipe Enable Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIER4 (0x40038600) /**< (USBHS) Host Pipe Enable Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIER5 (0x40038604) /**< (USBHS) Host Pipe Enable Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIER6 (0x40038608) /**< (USBHS) Host Pipe Enable Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIER7 (0x4003860C) /**< (USBHS) Host Pipe Enable Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIER8 (0x40038610) /**< (USBHS) Host Pipe Enable Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIER9 (0x40038614) /**< (USBHS) Host Pipe Enable Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIDR (0x40038620) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIDR0 (0x40038620) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIDR1 (0x40038624) /**< (USBHS) Host Pipe Disable Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIDR2 (0x40038628) /**< (USBHS) Host Pipe Disable Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIDR3 (0x4003862C) /**< (USBHS) Host Pipe Disable Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIDR4 (0x40038630) /**< (USBHS) Host Pipe Disable Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIDR5 (0x40038634) /**< (USBHS) Host Pipe Disable Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIDR6 (0x40038638) /**< (USBHS) Host Pipe Disable Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIDR7 (0x4003863C) /**< (USBHS) Host Pipe Disable Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIDR8 (0x40038640) /**< (USBHS) Host Pipe Disable Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIDR9 (0x40038644) /**< (USBHS) Host Pipe Disable Register (n = 0) 9 */
#define REG_USBHS_HSTPIPINRQ (0x40038650) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */
#define REG_USBHS_HSTPIPINRQ0 (0x40038650) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */
#define REG_USBHS_HSTPIPINRQ1 (0x40038654) /**< (USBHS) Host Pipe IN Request Register (n = 0) 1 */
#define REG_USBHS_HSTPIPINRQ2 (0x40038658) /**< (USBHS) Host Pipe IN Request Register (n = 0) 2 */
#define REG_USBHS_HSTPIPINRQ3 (0x4003865C) /**< (USBHS) Host Pipe IN Request Register (n = 0) 3 */
#define REG_USBHS_HSTPIPINRQ4 (0x40038660) /**< (USBHS) Host Pipe IN Request Register (n = 0) 4 */
#define REG_USBHS_HSTPIPINRQ5 (0x40038664) /**< (USBHS) Host Pipe IN Request Register (n = 0) 5 */
#define REG_USBHS_HSTPIPINRQ6 (0x40038668) /**< (USBHS) Host Pipe IN Request Register (n = 0) 6 */
#define REG_USBHS_HSTPIPINRQ7 (0x4003866C) /**< (USBHS) Host Pipe IN Request Register (n = 0) 7 */
#define REG_USBHS_HSTPIPINRQ8 (0x40038670) /**< (USBHS) Host Pipe IN Request Register (n = 0) 8 */
#define REG_USBHS_HSTPIPINRQ9 (0x40038674) /**< (USBHS) Host Pipe IN Request Register (n = 0) 9 */
#define REG_USBHS_HSTPIPERR (0x40038680) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */
#define REG_USBHS_HSTPIPERR0 (0x40038680) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */
#define REG_USBHS_HSTPIPERR1 (0x40038684) /**< (USBHS) Host Pipe Error Register (n = 0) 1 */
#define REG_USBHS_HSTPIPERR2 (0x40038688) /**< (USBHS) Host Pipe Error Register (n = 0) 2 */
#define REG_USBHS_HSTPIPERR3 (0x4003868C) /**< (USBHS) Host Pipe Error Register (n = 0) 3 */
#define REG_USBHS_HSTPIPERR4 (0x40038690) /**< (USBHS) Host Pipe Error Register (n = 0) 4 */
#define REG_USBHS_HSTPIPERR5 (0x40038694) /**< (USBHS) Host Pipe Error Register (n = 0) 5 */
#define REG_USBHS_HSTPIPERR6 (0x40038698) /**< (USBHS) Host Pipe Error Register (n = 0) 6 */
#define REG_USBHS_HSTPIPERR7 (0x4003869C) /**< (USBHS) Host Pipe Error Register (n = 0) 7 */
#define REG_USBHS_HSTPIPERR8 (0x400386A0) /**< (USBHS) Host Pipe Error Register (n = 0) 8 */
#define REG_USBHS_HSTPIPERR9 (0x400386A4) /**< (USBHS) Host Pipe Error Register (n = 0) 9 */
#define REG_USBHS_CTRL (0x40038800) /**< (USBHS) General Control Register */
#define REG_USBHS_SR (0x40038804) /**< (USBHS) General Status Register */
#define REG_USBHS_SCR (0x40038808) /**< (USBHS) General Status Clear Register */
#define REG_USBHS_SFR (0x4003880C) /**< (USBHS) General Status Set Register */
#else
#define REG_USBHS_DEVDMANXTDSC0 (*(__IO uint32_t*)0x40038310U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 0 */
#define REG_USBHS_DEVDMAADDRESS0 (*(__IO uint32_t*)0x40038314U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 0 */
#define REG_USBHS_DEVDMACONTROL0 (*(__IO uint32_t*)0x40038318U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 0 */
#define REG_USBHS_DEVDMASTATUS0 (*(__IO uint32_t*)0x4003831CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 0 */
#define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038320U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 1 */
#define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038324U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 1 */
#define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038328U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 1 */
#define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003832CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 1 */
#define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038330U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 2 */
#define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038334U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 2 */
#define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038338U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 2 */
#define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003833CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 2 */
#define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038340U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 3 */
#define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038344U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 3 */
#define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038348U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 3 */
#define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003834CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 3 */
#define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038350U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 4 */
#define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038354U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 4 */
#define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038358U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 4 */
#define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003835CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 4 */
#define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038360U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 5 */
#define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038364U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 5 */
#define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038368U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 5 */
#define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003836CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 5 */
#define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038370U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) 6 */
#define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038374U) /**< (USBHS) Device DMA Channel Address Register (n = 1) 6 */
#define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038378U) /**< (USBHS) Device DMA Channel Control Register (n = 1) 6 */
#define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003837CU) /**< (USBHS) Device DMA Channel Status Register (n = 1) 6 */
#define REG_USBHS_HSTDMANXTDSC0 (*(__IO uint32_t*)0x40038710U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 0 */
#define REG_USBHS_HSTDMAADDRESS0 (*(__IO uint32_t*)0x40038714U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 0 */
#define REG_USBHS_HSTDMACONTROL0 (*(__IO uint32_t*)0x40038718U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 0 */
#define REG_USBHS_HSTDMASTATUS0 (*(__IO uint32_t*)0x4003871CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 0 */
#define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038720U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 1 */
#define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038724U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 1 */
#define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038728U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 1 */
#define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003872CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 1 */
#define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038730U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 2 */
#define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038734U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 2 */
#define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038738U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 2 */
#define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003873CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 2 */
#define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038740U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 3 */
#define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038744U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 3 */
#define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038748U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 3 */
#define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003874CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 3 */
#define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038750U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 4 */
#define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038754U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 4 */
#define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038758U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 4 */
#define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003875CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 4 */
#define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038760U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 5 */
#define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038764U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 5 */
#define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038768U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 5 */
#define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003876CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 5 */
#define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038770U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) 6 */
#define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038774U) /**< (USBHS) Host DMA Channel Address Register (n = 1) 6 */
#define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038778U) /**< (USBHS) Host DMA Channel Control Register (n = 1) 6 */
#define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003877CU) /**< (USBHS) Host DMA Channel Status Register (n = 1) 6 */
#define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< (USBHS) Device General Control Register */
#define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< (USBHS) Device Global Interrupt Status Register */
#define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< (USBHS) Device Global Interrupt Clear Register */
#define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< (USBHS) Device Global Interrupt Set Register */
#define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< (USBHS) Device Global Interrupt Mask Register */
#define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< (USBHS) Device Global Interrupt Disable Register */
#define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< (USBHS) Device Global Interrupt Enable Register */
#define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< (USBHS) Device Endpoint Register */
#define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< (USBHS) Device Frame Number Register */
#define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */
#define REG_USBHS_DEVEPTCFG0 (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 0 */
#define REG_USBHS_DEVEPTCFG1 (*(__IO uint32_t*)0x40038104U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 1 */
#define REG_USBHS_DEVEPTCFG2 (*(__IO uint32_t*)0x40038108U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 2 */
#define REG_USBHS_DEVEPTCFG3 (*(__IO uint32_t*)0x4003810CU) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 3 */
#define REG_USBHS_DEVEPTCFG4 (*(__IO uint32_t*)0x40038110U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 4 */
#define REG_USBHS_DEVEPTCFG5 (*(__IO uint32_t*)0x40038114U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 5 */
#define REG_USBHS_DEVEPTCFG6 (*(__IO uint32_t*)0x40038118U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 6 */
#define REG_USBHS_DEVEPTCFG7 (*(__IO uint32_t*)0x4003811CU) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 7 */
#define REG_USBHS_DEVEPTCFG8 (*(__IO uint32_t*)0x40038120U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 8 */
#define REG_USBHS_DEVEPTCFG9 (*(__IO uint32_t*)0x40038124U) /**< (USBHS) Device Endpoint Configuration Register (n = 0) 9 */
#define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */
#define REG_USBHS_DEVEPTISR0 (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Status Register (n = 0) 0 */
#define REG_USBHS_DEVEPTISR1 (*(__I uint32_t*)0x40038134U) /**< (USBHS) Device Endpoint Status Register (n = 0) 1 */
#define REG_USBHS_DEVEPTISR2 (*(__I uint32_t*)0x40038138U) /**< (USBHS) Device Endpoint Status Register (n = 0) 2 */
#define REG_USBHS_DEVEPTISR3 (*(__I uint32_t*)0x4003813CU) /**< (USBHS) Device Endpoint Status Register (n = 0) 3 */
#define REG_USBHS_DEVEPTISR4 (*(__I uint32_t*)0x40038140U) /**< (USBHS) Device Endpoint Status Register (n = 0) 4 */
#define REG_USBHS_DEVEPTISR5 (*(__I uint32_t*)0x40038144U) /**< (USBHS) Device Endpoint Status Register (n = 0) 5 */
#define REG_USBHS_DEVEPTISR6 (*(__I uint32_t*)0x40038148U) /**< (USBHS) Device Endpoint Status Register (n = 0) 6 */
#define REG_USBHS_DEVEPTISR7 (*(__I uint32_t*)0x4003814CU) /**< (USBHS) Device Endpoint Status Register (n = 0) 7 */
#define REG_USBHS_DEVEPTISR8 (*(__I uint32_t*)0x40038150U) /**< (USBHS) Device Endpoint Status Register (n = 0) 8 */
#define REG_USBHS_DEVEPTISR9 (*(__I uint32_t*)0x40038154U) /**< (USBHS) Device Endpoint Status Register (n = 0) 9 */
#define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */
#define REG_USBHS_DEVEPTICR0 (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 0 */
#define REG_USBHS_DEVEPTICR1 (*(__O uint32_t*)0x40038164U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 1 */
#define REG_USBHS_DEVEPTICR2 (*(__O uint32_t*)0x40038168U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 2 */
#define REG_USBHS_DEVEPTICR3 (*(__O uint32_t*)0x4003816CU) /**< (USBHS) Device Endpoint Clear Register (n = 0) 3 */
#define REG_USBHS_DEVEPTICR4 (*(__O uint32_t*)0x40038170U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 4 */
#define REG_USBHS_DEVEPTICR5 (*(__O uint32_t*)0x40038174U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 5 */
#define REG_USBHS_DEVEPTICR6 (*(__O uint32_t*)0x40038178U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 6 */
#define REG_USBHS_DEVEPTICR7 (*(__O uint32_t*)0x4003817CU) /**< (USBHS) Device Endpoint Clear Register (n = 0) 7 */
#define REG_USBHS_DEVEPTICR8 (*(__O uint32_t*)0x40038180U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 8 */
#define REG_USBHS_DEVEPTICR9 (*(__O uint32_t*)0x40038184U) /**< (USBHS) Device Endpoint Clear Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIFR0 (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Set Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIFR1 (*(__O uint32_t*)0x40038194U) /**< (USBHS) Device Endpoint Set Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIFR2 (*(__O uint32_t*)0x40038198U) /**< (USBHS) Device Endpoint Set Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIFR3 (*(__O uint32_t*)0x4003819CU) /**< (USBHS) Device Endpoint Set Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIFR4 (*(__O uint32_t*)0x400381A0U) /**< (USBHS) Device Endpoint Set Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIFR5 (*(__O uint32_t*)0x400381A4U) /**< (USBHS) Device Endpoint Set Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIFR6 (*(__O uint32_t*)0x400381A8U) /**< (USBHS) Device Endpoint Set Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIFR7 (*(__O uint32_t*)0x400381ACU) /**< (USBHS) Device Endpoint Set Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIFR8 (*(__O uint32_t*)0x400381B0U) /**< (USBHS) Device Endpoint Set Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIFR9 (*(__O uint32_t*)0x400381B4U) /**< (USBHS) Device Endpoint Set Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIMR0 (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIMR1 (*(__I uint32_t*)0x400381C4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIMR2 (*(__I uint32_t*)0x400381C8U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIMR3 (*(__I uint32_t*)0x400381CCU) /**< (USBHS) Device Endpoint Mask Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIMR4 (*(__I uint32_t*)0x400381D0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIMR5 (*(__I uint32_t*)0x400381D4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIMR6 (*(__I uint32_t*)0x400381D8U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIMR7 (*(__I uint32_t*)0x400381DCU) /**< (USBHS) Device Endpoint Mask Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIMR8 (*(__I uint32_t*)0x400381E0U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIMR9 (*(__I uint32_t*)0x400381E4U) /**< (USBHS) Device Endpoint Mask Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIER0 (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIER1 (*(__O uint32_t*)0x400381F4U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIER2 (*(__O uint32_t*)0x400381F8U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIER3 (*(__O uint32_t*)0x400381FCU) /**< (USBHS) Device Endpoint Enable Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIER4 (*(__O uint32_t*)0x40038200U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIER5 (*(__O uint32_t*)0x40038204U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIER6 (*(__O uint32_t*)0x40038208U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIER7 (*(__O uint32_t*)0x4003820CU) /**< (USBHS) Device Endpoint Enable Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIER8 (*(__O uint32_t*)0x40038210U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIER9 (*(__O uint32_t*)0x40038214U) /**< (USBHS) Device Endpoint Enable Register (n = 0) 9 */
#define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIDR0 (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 0 */
#define REG_USBHS_DEVEPTIDR1 (*(__O uint32_t*)0x40038224U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 1 */
#define REG_USBHS_DEVEPTIDR2 (*(__O uint32_t*)0x40038228U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 2 */
#define REG_USBHS_DEVEPTIDR3 (*(__O uint32_t*)0x4003822CU) /**< (USBHS) Device Endpoint Disable Register (n = 0) 3 */
#define REG_USBHS_DEVEPTIDR4 (*(__O uint32_t*)0x40038230U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 4 */
#define REG_USBHS_DEVEPTIDR5 (*(__O uint32_t*)0x40038234U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 5 */
#define REG_USBHS_DEVEPTIDR6 (*(__O uint32_t*)0x40038238U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 6 */
#define REG_USBHS_DEVEPTIDR7 (*(__O uint32_t*)0x4003823CU) /**< (USBHS) Device Endpoint Disable Register (n = 0) 7 */
#define REG_USBHS_DEVEPTIDR8 (*(__O uint32_t*)0x40038240U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 8 */
#define REG_USBHS_DEVEPTIDR9 (*(__O uint32_t*)0x40038244U) /**< (USBHS) Device Endpoint Disable Register (n = 0) 9 */
#define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< (USBHS) Host General Control Register */
#define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< (USBHS) Host Global Interrupt Status Register */
#define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< (USBHS) Host Global Interrupt Clear Register */
#define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< (USBHS) Host Global Interrupt Set Register */
#define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< (USBHS) Host Global Interrupt Mask Register */
#define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< (USBHS) Host Global Interrupt Disable Register */
#define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< (USBHS) Host Global Interrupt Enable Register */
#define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< (USBHS) Host Pipe Register */
#define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< (USBHS) Host Frame Number Register */
#define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< (USBHS) Host Address 1 Register */
#define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< (USBHS) Host Address 2 Register */
#define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< (USBHS) Host Address 3 Register */
#define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */
#define REG_USBHS_HSTPIPCFG0 (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 0 */
#define REG_USBHS_HSTPIPCFG1 (*(__IO uint32_t*)0x40038504U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 1 */
#define REG_USBHS_HSTPIPCFG2 (*(__IO uint32_t*)0x40038508U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 2 */
#define REG_USBHS_HSTPIPCFG3 (*(__IO uint32_t*)0x4003850CU) /**< (USBHS) Host Pipe Configuration Register (n = 0) 3 */
#define REG_USBHS_HSTPIPCFG4 (*(__IO uint32_t*)0x40038510U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 4 */
#define REG_USBHS_HSTPIPCFG5 (*(__IO uint32_t*)0x40038514U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 5 */
#define REG_USBHS_HSTPIPCFG6 (*(__IO uint32_t*)0x40038518U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 6 */
#define REG_USBHS_HSTPIPCFG7 (*(__IO uint32_t*)0x4003851CU) /**< (USBHS) Host Pipe Configuration Register (n = 0) 7 */
#define REG_USBHS_HSTPIPCFG8 (*(__IO uint32_t*)0x40038520U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 8 */
#define REG_USBHS_HSTPIPCFG9 (*(__IO uint32_t*)0x40038524U) /**< (USBHS) Host Pipe Configuration Register (n = 0) 9 */
#define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */
#define REG_USBHS_HSTPIPISR0 (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register (n = 0) 0 */
#define REG_USBHS_HSTPIPISR1 (*(__I uint32_t*)0x40038534U) /**< (USBHS) Host Pipe Status Register (n = 0) 1 */
#define REG_USBHS_HSTPIPISR2 (*(__I uint32_t*)0x40038538U) /**< (USBHS) Host Pipe Status Register (n = 0) 2 */
#define REG_USBHS_HSTPIPISR3 (*(__I uint32_t*)0x4003853CU) /**< (USBHS) Host Pipe Status Register (n = 0) 3 */
#define REG_USBHS_HSTPIPISR4 (*(__I uint32_t*)0x40038540U) /**< (USBHS) Host Pipe Status Register (n = 0) 4 */
#define REG_USBHS_HSTPIPISR5 (*(__I uint32_t*)0x40038544U) /**< (USBHS) Host Pipe Status Register (n = 0) 5 */
#define REG_USBHS_HSTPIPISR6 (*(__I uint32_t*)0x40038548U) /**< (USBHS) Host Pipe Status Register (n = 0) 6 */
#define REG_USBHS_HSTPIPISR7 (*(__I uint32_t*)0x4003854CU) /**< (USBHS) Host Pipe Status Register (n = 0) 7 */
#define REG_USBHS_HSTPIPISR8 (*(__I uint32_t*)0x40038550U) /**< (USBHS) Host Pipe Status Register (n = 0) 8 */
#define REG_USBHS_HSTPIPISR9 (*(__I uint32_t*)0x40038554U) /**< (USBHS) Host Pipe Status Register (n = 0) 9 */
#define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */
#define REG_USBHS_HSTPIPICR0 (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register (n = 0) 0 */
#define REG_USBHS_HSTPIPICR1 (*(__O uint32_t*)0x40038564U) /**< (USBHS) Host Pipe Clear Register (n = 0) 1 */
#define REG_USBHS_HSTPIPICR2 (*(__O uint32_t*)0x40038568U) /**< (USBHS) Host Pipe Clear Register (n = 0) 2 */
#define REG_USBHS_HSTPIPICR3 (*(__O uint32_t*)0x4003856CU) /**< (USBHS) Host Pipe Clear Register (n = 0) 3 */
#define REG_USBHS_HSTPIPICR4 (*(__O uint32_t*)0x40038570U) /**< (USBHS) Host Pipe Clear Register (n = 0) 4 */
#define REG_USBHS_HSTPIPICR5 (*(__O uint32_t*)0x40038574U) /**< (USBHS) Host Pipe Clear Register (n = 0) 5 */
#define REG_USBHS_HSTPIPICR6 (*(__O uint32_t*)0x40038578U) /**< (USBHS) Host Pipe Clear Register (n = 0) 6 */
#define REG_USBHS_HSTPIPICR7 (*(__O uint32_t*)0x4003857CU) /**< (USBHS) Host Pipe Clear Register (n = 0) 7 */
#define REG_USBHS_HSTPIPICR8 (*(__O uint32_t*)0x40038580U) /**< (USBHS) Host Pipe Clear Register (n = 0) 8 */
#define REG_USBHS_HSTPIPICR9 (*(__O uint32_t*)0x40038584U) /**< (USBHS) Host Pipe Clear Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIFR0 (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIFR1 (*(__O uint32_t*)0x40038594U) /**< (USBHS) Host Pipe Set Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIFR2 (*(__O uint32_t*)0x40038598U) /**< (USBHS) Host Pipe Set Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIFR3 (*(__O uint32_t*)0x4003859CU) /**< (USBHS) Host Pipe Set Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIFR4 (*(__O uint32_t*)0x400385A0U) /**< (USBHS) Host Pipe Set Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIFR5 (*(__O uint32_t*)0x400385A4U) /**< (USBHS) Host Pipe Set Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIFR6 (*(__O uint32_t*)0x400385A8U) /**< (USBHS) Host Pipe Set Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIFR7 (*(__O uint32_t*)0x400385ACU) /**< (USBHS) Host Pipe Set Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIFR8 (*(__O uint32_t*)0x400385B0U) /**< (USBHS) Host Pipe Set Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIFR9 (*(__O uint32_t*)0x400385B4U) /**< (USBHS) Host Pipe Set Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIMR0 (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIMR1 (*(__I uint32_t*)0x400385C4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIMR2 (*(__I uint32_t*)0x400385C8U) /**< (USBHS) Host Pipe Mask Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIMR3 (*(__I uint32_t*)0x400385CCU) /**< (USBHS) Host Pipe Mask Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIMR4 (*(__I uint32_t*)0x400385D0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIMR5 (*(__I uint32_t*)0x400385D4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIMR6 (*(__I uint32_t*)0x400385D8U) /**< (USBHS) Host Pipe Mask Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIMR7 (*(__I uint32_t*)0x400385DCU) /**< (USBHS) Host Pipe Mask Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIMR8 (*(__I uint32_t*)0x400385E0U) /**< (USBHS) Host Pipe Mask Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIMR9 (*(__I uint32_t*)0x400385E4U) /**< (USBHS) Host Pipe Mask Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIER0 (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIER1 (*(__O uint32_t*)0x400385F4U) /**< (USBHS) Host Pipe Enable Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIER2 (*(__O uint32_t*)0x400385F8U) /**< (USBHS) Host Pipe Enable Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIER3 (*(__O uint32_t*)0x400385FCU) /**< (USBHS) Host Pipe Enable Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIER4 (*(__O uint32_t*)0x40038600U) /**< (USBHS) Host Pipe Enable Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIER5 (*(__O uint32_t*)0x40038604U) /**< (USBHS) Host Pipe Enable Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIER6 (*(__O uint32_t*)0x40038608U) /**< (USBHS) Host Pipe Enable Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIER7 (*(__O uint32_t*)0x4003860CU) /**< (USBHS) Host Pipe Enable Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIER8 (*(__O uint32_t*)0x40038610U) /**< (USBHS) Host Pipe Enable Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIER9 (*(__O uint32_t*)0x40038614U) /**< (USBHS) Host Pipe Enable Register (n = 0) 9 */
#define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIDR0 (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register (n = 0) 0 */
#define REG_USBHS_HSTPIPIDR1 (*(__O uint32_t*)0x40038624U) /**< (USBHS) Host Pipe Disable Register (n = 0) 1 */
#define REG_USBHS_HSTPIPIDR2 (*(__O uint32_t*)0x40038628U) /**< (USBHS) Host Pipe Disable Register (n = 0) 2 */
#define REG_USBHS_HSTPIPIDR3 (*(__O uint32_t*)0x4003862CU) /**< (USBHS) Host Pipe Disable Register (n = 0) 3 */
#define REG_USBHS_HSTPIPIDR4 (*(__O uint32_t*)0x40038630U) /**< (USBHS) Host Pipe Disable Register (n = 0) 4 */
#define REG_USBHS_HSTPIPIDR5 (*(__O uint32_t*)0x40038634U) /**< (USBHS) Host Pipe Disable Register (n = 0) 5 */
#define REG_USBHS_HSTPIPIDR6 (*(__O uint32_t*)0x40038638U) /**< (USBHS) Host Pipe Disable Register (n = 0) 6 */
#define REG_USBHS_HSTPIPIDR7 (*(__O uint32_t*)0x4003863CU) /**< (USBHS) Host Pipe Disable Register (n = 0) 7 */
#define REG_USBHS_HSTPIPIDR8 (*(__O uint32_t*)0x40038640U) /**< (USBHS) Host Pipe Disable Register (n = 0) 8 */
#define REG_USBHS_HSTPIPIDR9 (*(__O uint32_t*)0x40038644U) /**< (USBHS) Host Pipe Disable Register (n = 0) 9 */
#define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */
#define REG_USBHS_HSTPIPINRQ0 (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 0 */
#define REG_USBHS_HSTPIPINRQ1 (*(__IO uint32_t*)0x40038654U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 1 */
#define REG_USBHS_HSTPIPINRQ2 (*(__IO uint32_t*)0x40038658U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 2 */
#define REG_USBHS_HSTPIPINRQ3 (*(__IO uint32_t*)0x4003865CU) /**< (USBHS) Host Pipe IN Request Register (n = 0) 3 */
#define REG_USBHS_HSTPIPINRQ4 (*(__IO uint32_t*)0x40038660U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 4 */
#define REG_USBHS_HSTPIPINRQ5 (*(__IO uint32_t*)0x40038664U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 5 */
#define REG_USBHS_HSTPIPINRQ6 (*(__IO uint32_t*)0x40038668U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 6 */
#define REG_USBHS_HSTPIPINRQ7 (*(__IO uint32_t*)0x4003866CU) /**< (USBHS) Host Pipe IN Request Register (n = 0) 7 */
#define REG_USBHS_HSTPIPINRQ8 (*(__IO uint32_t*)0x40038670U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 8 */
#define REG_USBHS_HSTPIPINRQ9 (*(__IO uint32_t*)0x40038674U) /**< (USBHS) Host Pipe IN Request Register (n = 0) 9 */
#define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */
#define REG_USBHS_HSTPIPERR0 (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register (n = 0) 0 */
#define REG_USBHS_HSTPIPERR1 (*(__IO uint32_t*)0x40038684U) /**< (USBHS) Host Pipe Error Register (n = 0) 1 */
#define REG_USBHS_HSTPIPERR2 (*(__IO uint32_t*)0x40038688U) /**< (USBHS) Host Pipe Error Register (n = 0) 2 */
#define REG_USBHS_HSTPIPERR3 (*(__IO uint32_t*)0x4003868CU) /**< (USBHS) Host Pipe Error Register (n = 0) 3 */
#define REG_USBHS_HSTPIPERR4 (*(__IO uint32_t*)0x40038690U) /**< (USBHS) Host Pipe Error Register (n = 0) 4 */
#define REG_USBHS_HSTPIPERR5 (*(__IO uint32_t*)0x40038694U) /**< (USBHS) Host Pipe Error Register (n = 0) 5 */
#define REG_USBHS_HSTPIPERR6 (*(__IO uint32_t*)0x40038698U) /**< (USBHS) Host Pipe Error Register (n = 0) 6 */
#define REG_USBHS_HSTPIPERR7 (*(__IO uint32_t*)0x4003869CU) /**< (USBHS) Host Pipe Error Register (n = 0) 7 */
#define REG_USBHS_HSTPIPERR8 (*(__IO uint32_t*)0x400386A0U) /**< (USBHS) Host Pipe Error Register (n = 0) 8 */
#define REG_USBHS_HSTPIPERR9 (*(__IO uint32_t*)0x400386A4U) /**< (USBHS) Host Pipe Error Register (n = 0) 9 */
#define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< (USBHS) General Control Register */
#define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< (USBHS) General Status Register */
#define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< (USBHS) General Status Clear Register */
#define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< (USBHS) General Status Set Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for USBHS peripheral ========== */
#define USBHS_INSTANCE_ID 34
#define USBHS_CLOCK_ID 34
#endif /* _SAME70_USBHS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for UTMI
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_UTMI_INSTANCE_H_
#define _SAME70_UTMI_INSTANCE_H_
/* ========== Register definition for UTMI peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UTMI_OHCIICR (0x400E0410) /**< (UTMI) OHCI Interrupt Configuration Register */
#define REG_UTMI_CKTRIM (0x400E0430) /**< (UTMI) UTMI Clock Trimming Register */
#else
#define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< (UTMI) OHCI Interrupt Configuration Register */
#define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< (UTMI) UTMI Clock Trimming Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME70_UTMI_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for WDT
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_WDT_INSTANCE_H_
#define _SAME70_WDT_INSTANCE_H_
/* ========== Register definition for WDT peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_WDT_CR (0x400E1850) /**< (WDT) Control Register */
#define REG_WDT_MR (0x400E1854) /**< (WDT) Mode Register */
#define REG_WDT_SR (0x400E1858) /**< (WDT) Status Register */
#else
#define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< (WDT) Control Register */
#define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< (WDT) Mode Register */
#define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< (WDT) Status Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for WDT peripheral ========== */
#define WDT_INSTANCE_ID 4
#endif /* _SAME70_WDT_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for XDMAC
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
/* file generated from device description version 2017-09-13T14:00:00Z */
#ifndef _SAME70_XDMAC_INSTANCE_H_
#define _SAME70_XDMAC_INSTANCE_H_
/* ========== Register definition for XDMAC peripheral ========== */
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_XDMAC_CIE0 (0x40078050) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 0 */
#define REG_XDMAC_CID0 (0x40078054) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 0 */
#define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 0 */
#define REG_XDMAC_CIS0 (0x4007805C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 0 */
#define REG_XDMAC_CSA0 (0x40078060) /**< (XDMAC) Channel Source Address Register (chid = 0) 0 */
#define REG_XDMAC_CDA0 (0x40078064) /**< (XDMAC) Channel Destination Address Register (chid = 0) 0 */
#define REG_XDMAC_CNDA0 (0x40078068) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 0 */
#define REG_XDMAC_CNDC0 (0x4007806C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 0 */
#define REG_XDMAC_CUBC0 (0x40078070) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 0 */
#define REG_XDMAC_CBC0 (0x40078074) /**< (XDMAC) Channel Block Control Register (chid = 0) 0 */
#define REG_XDMAC_CC0 (0x40078078) /**< (XDMAC) Channel Configuration Register (chid = 0) 0 */
#define REG_XDMAC_CDS_MSP0 (0x4007807C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 0 */
#define REG_XDMAC_CSUS0 (0x40078080) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 0 */
#define REG_XDMAC_CDUS0 (0x40078084) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 0 */
#define REG_XDMAC_CIE1 (0x40078090) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 1 */
#define REG_XDMAC_CID1 (0x40078094) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 1 */
#define REG_XDMAC_CIM1 (0x40078098) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 1 */
#define REG_XDMAC_CIS1 (0x4007809C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 1 */
#define REG_XDMAC_CSA1 (0x400780A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 1 */
#define REG_XDMAC_CDA1 (0x400780A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 1 */
#define REG_XDMAC_CNDA1 (0x400780A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 1 */
#define REG_XDMAC_CNDC1 (0x400780AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 1 */
#define REG_XDMAC_CUBC1 (0x400780B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 1 */
#define REG_XDMAC_CBC1 (0x400780B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 1 */
#define REG_XDMAC_CC1 (0x400780B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 1 */
#define REG_XDMAC_CDS_MSP1 (0x400780BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 1 */
#define REG_XDMAC_CSUS1 (0x400780C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 1 */
#define REG_XDMAC_CDUS1 (0x400780C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 1 */
#define REG_XDMAC_CIE2 (0x400780D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 2 */
#define REG_XDMAC_CID2 (0x400780D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 2 */
#define REG_XDMAC_CIM2 (0x400780D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 2 */
#define REG_XDMAC_CIS2 (0x400780DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 2 */
#define REG_XDMAC_CSA2 (0x400780E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 2 */
#define REG_XDMAC_CDA2 (0x400780E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 2 */
#define REG_XDMAC_CNDA2 (0x400780E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 2 */
#define REG_XDMAC_CNDC2 (0x400780EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 2 */
#define REG_XDMAC_CUBC2 (0x400780F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 2 */
#define REG_XDMAC_CBC2 (0x400780F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 2 */
#define REG_XDMAC_CC2 (0x400780F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 2 */
#define REG_XDMAC_CDS_MSP2 (0x400780FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 2 */
#define REG_XDMAC_CSUS2 (0x40078100) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 2 */
#define REG_XDMAC_CDUS2 (0x40078104) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 2 */
#define REG_XDMAC_CIE3 (0x40078110) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 3 */
#define REG_XDMAC_CID3 (0x40078114) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 3 */
#define REG_XDMAC_CIM3 (0x40078118) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 3 */
#define REG_XDMAC_CIS3 (0x4007811C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 3 */
#define REG_XDMAC_CSA3 (0x40078120) /**< (XDMAC) Channel Source Address Register (chid = 0) 3 */
#define REG_XDMAC_CDA3 (0x40078124) /**< (XDMAC) Channel Destination Address Register (chid = 0) 3 */
#define REG_XDMAC_CNDA3 (0x40078128) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 3 */
#define REG_XDMAC_CNDC3 (0x4007812C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 3 */
#define REG_XDMAC_CUBC3 (0x40078130) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 3 */
#define REG_XDMAC_CBC3 (0x40078134) /**< (XDMAC) Channel Block Control Register (chid = 0) 3 */
#define REG_XDMAC_CC3 (0x40078138) /**< (XDMAC) Channel Configuration Register (chid = 0) 3 */
#define REG_XDMAC_CDS_MSP3 (0x4007813C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 3 */
#define REG_XDMAC_CSUS3 (0x40078140) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 3 */
#define REG_XDMAC_CDUS3 (0x40078144) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 3 */
#define REG_XDMAC_CIE4 (0x40078150) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 4 */
#define REG_XDMAC_CID4 (0x40078154) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 4 */
#define REG_XDMAC_CIM4 (0x40078158) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 4 */
#define REG_XDMAC_CIS4 (0x4007815C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 4 */
#define REG_XDMAC_CSA4 (0x40078160) /**< (XDMAC) Channel Source Address Register (chid = 0) 4 */
#define REG_XDMAC_CDA4 (0x40078164) /**< (XDMAC) Channel Destination Address Register (chid = 0) 4 */
#define REG_XDMAC_CNDA4 (0x40078168) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 4 */
#define REG_XDMAC_CNDC4 (0x4007816C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 4 */
#define REG_XDMAC_CUBC4 (0x40078170) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 4 */
#define REG_XDMAC_CBC4 (0x40078174) /**< (XDMAC) Channel Block Control Register (chid = 0) 4 */
#define REG_XDMAC_CC4 (0x40078178) /**< (XDMAC) Channel Configuration Register (chid = 0) 4 */
#define REG_XDMAC_CDS_MSP4 (0x4007817C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 4 */
#define REG_XDMAC_CSUS4 (0x40078180) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 4 */
#define REG_XDMAC_CDUS4 (0x40078184) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 4 */
#define REG_XDMAC_CIE5 (0x40078190) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 5 */
#define REG_XDMAC_CID5 (0x40078194) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 5 */
#define REG_XDMAC_CIM5 (0x40078198) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 5 */
#define REG_XDMAC_CIS5 (0x4007819C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 5 */
#define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 5 */
#define REG_XDMAC_CDA5 (0x400781A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 5 */
#define REG_XDMAC_CNDA5 (0x400781A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 5 */
#define REG_XDMAC_CNDC5 (0x400781AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 5 */
#define REG_XDMAC_CUBC5 (0x400781B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 5 */
#define REG_XDMAC_CBC5 (0x400781B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 5 */
#define REG_XDMAC_CC5 (0x400781B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 5 */
#define REG_XDMAC_CDS_MSP5 (0x400781BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 5 */
#define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 5 */
#define REG_XDMAC_CDUS5 (0x400781C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 5 */
#define REG_XDMAC_CIE6 (0x400781D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 6 */
#define REG_XDMAC_CID6 (0x400781D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 6 */
#define REG_XDMAC_CIM6 (0x400781D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 6 */
#define REG_XDMAC_CIS6 (0x400781DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 6 */
#define REG_XDMAC_CSA6 (0x400781E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 6 */
#define REG_XDMAC_CDA6 (0x400781E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 6 */
#define REG_XDMAC_CNDA6 (0x400781E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 6 */
#define REG_XDMAC_CNDC6 (0x400781EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 6 */
#define REG_XDMAC_CUBC6 (0x400781F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 6 */
#define REG_XDMAC_CBC6 (0x400781F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 6 */
#define REG_XDMAC_CC6 (0x400781F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 6 */
#define REG_XDMAC_CDS_MSP6 (0x400781FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 6 */
#define REG_XDMAC_CSUS6 (0x40078200) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 6 */
#define REG_XDMAC_CDUS6 (0x40078204) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 6 */
#define REG_XDMAC_CIE7 (0x40078210) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 7 */
#define REG_XDMAC_CID7 (0x40078214) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 7 */
#define REG_XDMAC_CIM7 (0x40078218) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 7 */
#define REG_XDMAC_CIS7 (0x4007821C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 7 */
#define REG_XDMAC_CSA7 (0x40078220) /**< (XDMAC) Channel Source Address Register (chid = 0) 7 */
#define REG_XDMAC_CDA7 (0x40078224) /**< (XDMAC) Channel Destination Address Register (chid = 0) 7 */
#define REG_XDMAC_CNDA7 (0x40078228) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 7 */
#define REG_XDMAC_CNDC7 (0x4007822C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 7 */
#define REG_XDMAC_CUBC7 (0x40078230) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 7 */
#define REG_XDMAC_CBC7 (0x40078234) /**< (XDMAC) Channel Block Control Register (chid = 0) 7 */
#define REG_XDMAC_CC7 (0x40078238) /**< (XDMAC) Channel Configuration Register (chid = 0) 7 */
#define REG_XDMAC_CDS_MSP7 (0x4007823C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 7 */
#define REG_XDMAC_CSUS7 (0x40078240) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 7 */
#define REG_XDMAC_CDUS7 (0x40078244) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 7 */
#define REG_XDMAC_CIE8 (0x40078250) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 8 */
#define REG_XDMAC_CID8 (0x40078254) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 8 */
#define REG_XDMAC_CIM8 (0x40078258) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 8 */
#define REG_XDMAC_CIS8 (0x4007825C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 8 */
#define REG_XDMAC_CSA8 (0x40078260) /**< (XDMAC) Channel Source Address Register (chid = 0) 8 */
#define REG_XDMAC_CDA8 (0x40078264) /**< (XDMAC) Channel Destination Address Register (chid = 0) 8 */
#define REG_XDMAC_CNDA8 (0x40078268) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 8 */
#define REG_XDMAC_CNDC8 (0x4007826C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 8 */
#define REG_XDMAC_CUBC8 (0x40078270) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 8 */
#define REG_XDMAC_CBC8 (0x40078274) /**< (XDMAC) Channel Block Control Register (chid = 0) 8 */
#define REG_XDMAC_CC8 (0x40078278) /**< (XDMAC) Channel Configuration Register (chid = 0) 8 */
#define REG_XDMAC_CDS_MSP8 (0x4007827C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 8 */
#define REG_XDMAC_CSUS8 (0x40078280) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 8 */
#define REG_XDMAC_CDUS8 (0x40078284) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 8 */
#define REG_XDMAC_CIE9 (0x40078290) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 9 */
#define REG_XDMAC_CID9 (0x40078294) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 9 */
#define REG_XDMAC_CIM9 (0x40078298) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 9 */
#define REG_XDMAC_CIS9 (0x4007829C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 9 */
#define REG_XDMAC_CSA9 (0x400782A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 9 */
#define REG_XDMAC_CDA9 (0x400782A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 9 */
#define REG_XDMAC_CNDA9 (0x400782A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 9 */
#define REG_XDMAC_CNDC9 (0x400782AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 9 */
#define REG_XDMAC_CUBC9 (0x400782B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 9 */
#define REG_XDMAC_CBC9 (0x400782B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 9 */
#define REG_XDMAC_CC9 (0x400782B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 9 */
#define REG_XDMAC_CDS_MSP9 (0x400782BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 9 */
#define REG_XDMAC_CSUS9 (0x400782C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 9 */
#define REG_XDMAC_CDUS9 (0x400782C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 9 */
#define REG_XDMAC_CIE10 (0x400782D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 10 */
#define REG_XDMAC_CID10 (0x400782D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 10 */
#define REG_XDMAC_CIM10 (0x400782D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 10 */
#define REG_XDMAC_CIS10 (0x400782DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 10 */
#define REG_XDMAC_CSA10 (0x400782E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 10 */
#define REG_XDMAC_CDA10 (0x400782E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 10 */
#define REG_XDMAC_CNDA10 (0x400782E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 10 */
#define REG_XDMAC_CNDC10 (0x400782EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 10 */
#define REG_XDMAC_CUBC10 (0x400782F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 10 */
#define REG_XDMAC_CBC10 (0x400782F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 10 */
#define REG_XDMAC_CC10 (0x400782F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 10 */
#define REG_XDMAC_CDS_MSP10 (0x400782FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 10 */
#define REG_XDMAC_CSUS10 (0x40078300) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 10 */
#define REG_XDMAC_CDUS10 (0x40078304) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 10 */
#define REG_XDMAC_CIE11 (0x40078310) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 11 */
#define REG_XDMAC_CID11 (0x40078314) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 11 */
#define REG_XDMAC_CIM11 (0x40078318) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 11 */
#define REG_XDMAC_CIS11 (0x4007831C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 11 */
#define REG_XDMAC_CSA11 (0x40078320) /**< (XDMAC) Channel Source Address Register (chid = 0) 11 */
#define REG_XDMAC_CDA11 (0x40078324) /**< (XDMAC) Channel Destination Address Register (chid = 0) 11 */
#define REG_XDMAC_CNDA11 (0x40078328) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 11 */
#define REG_XDMAC_CNDC11 (0x4007832C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 11 */
#define REG_XDMAC_CUBC11 (0x40078330) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 11 */
#define REG_XDMAC_CBC11 (0x40078334) /**< (XDMAC) Channel Block Control Register (chid = 0) 11 */
#define REG_XDMAC_CC11 (0x40078338) /**< (XDMAC) Channel Configuration Register (chid = 0) 11 */
#define REG_XDMAC_CDS_MSP11 (0x4007833C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 11 */
#define REG_XDMAC_CSUS11 (0x40078340) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 11 */
#define REG_XDMAC_CDUS11 (0x40078344) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 11 */
#define REG_XDMAC_CIE12 (0x40078350) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 12 */
#define REG_XDMAC_CID12 (0x40078354) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 12 */
#define REG_XDMAC_CIM12 (0x40078358) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 12 */
#define REG_XDMAC_CIS12 (0x4007835C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 12 */
#define REG_XDMAC_CSA12 (0x40078360) /**< (XDMAC) Channel Source Address Register (chid = 0) 12 */
#define REG_XDMAC_CDA12 (0x40078364) /**< (XDMAC) Channel Destination Address Register (chid = 0) 12 */
#define REG_XDMAC_CNDA12 (0x40078368) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 12 */
#define REG_XDMAC_CNDC12 (0x4007836C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 12 */
#define REG_XDMAC_CUBC12 (0x40078370) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 12 */
#define REG_XDMAC_CBC12 (0x40078374) /**< (XDMAC) Channel Block Control Register (chid = 0) 12 */
#define REG_XDMAC_CC12 (0x40078378) /**< (XDMAC) Channel Configuration Register (chid = 0) 12 */
#define REG_XDMAC_CDS_MSP12 (0x4007837C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 12 */
#define REG_XDMAC_CSUS12 (0x40078380) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 12 */
#define REG_XDMAC_CDUS12 (0x40078384) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 12 */
#define REG_XDMAC_CIE13 (0x40078390) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 13 */
#define REG_XDMAC_CID13 (0x40078394) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 13 */
#define REG_XDMAC_CIM13 (0x40078398) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 13 */
#define REG_XDMAC_CIS13 (0x4007839C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 13 */
#define REG_XDMAC_CSA13 (0x400783A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 13 */
#define REG_XDMAC_CDA13 (0x400783A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 13 */
#define REG_XDMAC_CNDA13 (0x400783A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 13 */
#define REG_XDMAC_CNDC13 (0x400783AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 13 */
#define REG_XDMAC_CUBC13 (0x400783B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 13 */
#define REG_XDMAC_CBC13 (0x400783B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 13 */
#define REG_XDMAC_CC13 (0x400783B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 13 */
#define REG_XDMAC_CDS_MSP13 (0x400783BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 13 */
#define REG_XDMAC_CSUS13 (0x400783C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 13 */
#define REG_XDMAC_CDUS13 (0x400783C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 13 */
#define REG_XDMAC_CIE14 (0x400783D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 14 */
#define REG_XDMAC_CID14 (0x400783D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 14 */
#define REG_XDMAC_CIM14 (0x400783D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 14 */
#define REG_XDMAC_CIS14 (0x400783DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 14 */
#define REG_XDMAC_CSA14 (0x400783E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 14 */
#define REG_XDMAC_CDA14 (0x400783E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 14 */
#define REG_XDMAC_CNDA14 (0x400783E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 14 */
#define REG_XDMAC_CNDC14 (0x400783EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 14 */
#define REG_XDMAC_CUBC14 (0x400783F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 14 */
#define REG_XDMAC_CBC14 (0x400783F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 14 */
#define REG_XDMAC_CC14 (0x400783F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 14 */
#define REG_XDMAC_CDS_MSP14 (0x400783FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 14 */
#define REG_XDMAC_CSUS14 (0x40078400) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 14 */
#define REG_XDMAC_CDUS14 (0x40078404) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 14 */
#define REG_XDMAC_CIE15 (0x40078410) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 15 */
#define REG_XDMAC_CID15 (0x40078414) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 15 */
#define REG_XDMAC_CIM15 (0x40078418) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 15 */
#define REG_XDMAC_CIS15 (0x4007841C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 15 */
#define REG_XDMAC_CSA15 (0x40078420) /**< (XDMAC) Channel Source Address Register (chid = 0) 15 */
#define REG_XDMAC_CDA15 (0x40078424) /**< (XDMAC) Channel Destination Address Register (chid = 0) 15 */
#define REG_XDMAC_CNDA15 (0x40078428) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 15 */
#define REG_XDMAC_CNDC15 (0x4007842C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 15 */
#define REG_XDMAC_CUBC15 (0x40078430) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 15 */
#define REG_XDMAC_CBC15 (0x40078434) /**< (XDMAC) Channel Block Control Register (chid = 0) 15 */
#define REG_XDMAC_CC15 (0x40078438) /**< (XDMAC) Channel Configuration Register (chid = 0) 15 */
#define REG_XDMAC_CDS_MSP15 (0x4007843C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 15 */
#define REG_XDMAC_CSUS15 (0x40078440) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 15 */
#define REG_XDMAC_CDUS15 (0x40078444) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 15 */
#define REG_XDMAC_CIE16 (0x40078450) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 16 */
#define REG_XDMAC_CID16 (0x40078454) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 16 */
#define REG_XDMAC_CIM16 (0x40078458) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 16 */
#define REG_XDMAC_CIS16 (0x4007845C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 16 */
#define REG_XDMAC_CSA16 (0x40078460) /**< (XDMAC) Channel Source Address Register (chid = 0) 16 */
#define REG_XDMAC_CDA16 (0x40078464) /**< (XDMAC) Channel Destination Address Register (chid = 0) 16 */
#define REG_XDMAC_CNDA16 (0x40078468) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 16 */
#define REG_XDMAC_CNDC16 (0x4007846C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 16 */
#define REG_XDMAC_CUBC16 (0x40078470) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 16 */
#define REG_XDMAC_CBC16 (0x40078474) /**< (XDMAC) Channel Block Control Register (chid = 0) 16 */
#define REG_XDMAC_CC16 (0x40078478) /**< (XDMAC) Channel Configuration Register (chid = 0) 16 */
#define REG_XDMAC_CDS_MSP16 (0x4007847C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 16 */
#define REG_XDMAC_CSUS16 (0x40078480) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 16 */
#define REG_XDMAC_CDUS16 (0x40078484) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 16 */
#define REG_XDMAC_CIE17 (0x40078490) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 17 */
#define REG_XDMAC_CID17 (0x40078494) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 17 */
#define REG_XDMAC_CIM17 (0x40078498) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 17 */
#define REG_XDMAC_CIS17 (0x4007849C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 17 */
#define REG_XDMAC_CSA17 (0x400784A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 17 */
#define REG_XDMAC_CDA17 (0x400784A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 17 */
#define REG_XDMAC_CNDA17 (0x400784A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 17 */
#define REG_XDMAC_CNDC17 (0x400784AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 17 */
#define REG_XDMAC_CUBC17 (0x400784B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 17 */
#define REG_XDMAC_CBC17 (0x400784B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 17 */
#define REG_XDMAC_CC17 (0x400784B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 17 */
#define REG_XDMAC_CDS_MSP17 (0x400784BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 17 */
#define REG_XDMAC_CSUS17 (0x400784C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 17 */
#define REG_XDMAC_CDUS17 (0x400784C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 17 */
#define REG_XDMAC_CIE18 (0x400784D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 18 */
#define REG_XDMAC_CID18 (0x400784D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 18 */
#define REG_XDMAC_CIM18 (0x400784D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 18 */
#define REG_XDMAC_CIS18 (0x400784DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 18 */
#define REG_XDMAC_CSA18 (0x400784E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 18 */
#define REG_XDMAC_CDA18 (0x400784E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 18 */
#define REG_XDMAC_CNDA18 (0x400784E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 18 */
#define REG_XDMAC_CNDC18 (0x400784EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 18 */
#define REG_XDMAC_CUBC18 (0x400784F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 18 */
#define REG_XDMAC_CBC18 (0x400784F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 18 */
#define REG_XDMAC_CC18 (0x400784F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 18 */
#define REG_XDMAC_CDS_MSP18 (0x400784FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 18 */
#define REG_XDMAC_CSUS18 (0x40078500) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 18 */
#define REG_XDMAC_CDUS18 (0x40078504) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 18 */
#define REG_XDMAC_CIE19 (0x40078510) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 19 */
#define REG_XDMAC_CID19 (0x40078514) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 19 */
#define REG_XDMAC_CIM19 (0x40078518) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 19 */
#define REG_XDMAC_CIS19 (0x4007851C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 19 */
#define REG_XDMAC_CSA19 (0x40078520) /**< (XDMAC) Channel Source Address Register (chid = 0) 19 */
#define REG_XDMAC_CDA19 (0x40078524) /**< (XDMAC) Channel Destination Address Register (chid = 0) 19 */
#define REG_XDMAC_CNDA19 (0x40078528) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 19 */
#define REG_XDMAC_CNDC19 (0x4007852C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 19 */
#define REG_XDMAC_CUBC19 (0x40078530) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 19 */
#define REG_XDMAC_CBC19 (0x40078534) /**< (XDMAC) Channel Block Control Register (chid = 0) 19 */
#define REG_XDMAC_CC19 (0x40078538) /**< (XDMAC) Channel Configuration Register (chid = 0) 19 */
#define REG_XDMAC_CDS_MSP19 (0x4007853C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 19 */
#define REG_XDMAC_CSUS19 (0x40078540) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 19 */
#define REG_XDMAC_CDUS19 (0x40078544) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 19 */
#define REG_XDMAC_CIE20 (0x40078550) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 20 */
#define REG_XDMAC_CID20 (0x40078554) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 20 */
#define REG_XDMAC_CIM20 (0x40078558) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 20 */
#define REG_XDMAC_CIS20 (0x4007855C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 20 */
#define REG_XDMAC_CSA20 (0x40078560) /**< (XDMAC) Channel Source Address Register (chid = 0) 20 */
#define REG_XDMAC_CDA20 (0x40078564) /**< (XDMAC) Channel Destination Address Register (chid = 0) 20 */
#define REG_XDMAC_CNDA20 (0x40078568) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 20 */
#define REG_XDMAC_CNDC20 (0x4007856C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 20 */
#define REG_XDMAC_CUBC20 (0x40078570) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 20 */
#define REG_XDMAC_CBC20 (0x40078574) /**< (XDMAC) Channel Block Control Register (chid = 0) 20 */
#define REG_XDMAC_CC20 (0x40078578) /**< (XDMAC) Channel Configuration Register (chid = 0) 20 */
#define REG_XDMAC_CDS_MSP20 (0x4007857C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 20 */
#define REG_XDMAC_CSUS20 (0x40078580) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 20 */
#define REG_XDMAC_CDUS20 (0x40078584) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 20 */
#define REG_XDMAC_CIE21 (0x40078590) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 21 */
#define REG_XDMAC_CID21 (0x40078594) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 21 */
#define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 21 */
#define REG_XDMAC_CIS21 (0x4007859C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 21 */
#define REG_XDMAC_CSA21 (0x400785A0) /**< (XDMAC) Channel Source Address Register (chid = 0) 21 */
#define REG_XDMAC_CDA21 (0x400785A4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 21 */
#define REG_XDMAC_CNDA21 (0x400785A8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 21 */
#define REG_XDMAC_CNDC21 (0x400785AC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 21 */
#define REG_XDMAC_CUBC21 (0x400785B0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 21 */
#define REG_XDMAC_CBC21 (0x400785B4) /**< (XDMAC) Channel Block Control Register (chid = 0) 21 */
#define REG_XDMAC_CC21 (0x400785B8) /**< (XDMAC) Channel Configuration Register (chid = 0) 21 */
#define REG_XDMAC_CDS_MSP21 (0x400785BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 21 */
#define REG_XDMAC_CSUS21 (0x400785C0) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 21 */
#define REG_XDMAC_CDUS21 (0x400785C4) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 21 */
#define REG_XDMAC_CIE22 (0x400785D0) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 22 */
#define REG_XDMAC_CID22 (0x400785D4) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 22 */
#define REG_XDMAC_CIM22 (0x400785D8) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 22 */
#define REG_XDMAC_CIS22 (0x400785DC) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 22 */
#define REG_XDMAC_CSA22 (0x400785E0) /**< (XDMAC) Channel Source Address Register (chid = 0) 22 */
#define REG_XDMAC_CDA22 (0x400785E4) /**< (XDMAC) Channel Destination Address Register (chid = 0) 22 */
#define REG_XDMAC_CNDA22 (0x400785E8) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 22 */
#define REG_XDMAC_CNDC22 (0x400785EC) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 22 */
#define REG_XDMAC_CUBC22 (0x400785F0) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 22 */
#define REG_XDMAC_CBC22 (0x400785F4) /**< (XDMAC) Channel Block Control Register (chid = 0) 22 */
#define REG_XDMAC_CC22 (0x400785F8) /**< (XDMAC) Channel Configuration Register (chid = 0) 22 */
#define REG_XDMAC_CDS_MSP22 (0x400785FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 22 */
#define REG_XDMAC_CSUS22 (0x40078600) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 22 */
#define REG_XDMAC_CDUS22 (0x40078604) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 22 */
#define REG_XDMAC_CIE23 (0x40078610) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 23 */
#define REG_XDMAC_CID23 (0x40078614) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 23 */
#define REG_XDMAC_CIM23 (0x40078618) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 23 */
#define REG_XDMAC_CIS23 (0x4007861C) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 23 */
#define REG_XDMAC_CSA23 (0x40078620) /**< (XDMAC) Channel Source Address Register (chid = 0) 23 */
#define REG_XDMAC_CDA23 (0x40078624) /**< (XDMAC) Channel Destination Address Register (chid = 0) 23 */
#define REG_XDMAC_CNDA23 (0x40078628) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 23 */
#define REG_XDMAC_CNDC23 (0x4007862C) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 23 */
#define REG_XDMAC_CUBC23 (0x40078630) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 23 */
#define REG_XDMAC_CBC23 (0x40078634) /**< (XDMAC) Channel Block Control Register (chid = 0) 23 */
#define REG_XDMAC_CC23 (0x40078638) /**< (XDMAC) Channel Configuration Register (chid = 0) 23 */
#define REG_XDMAC_CDS_MSP23 (0x4007863C) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 23 */
#define REG_XDMAC_CSUS23 (0x40078640) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 23 */
#define REG_XDMAC_CDUS23 (0x40078644) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 23 */
#define REG_XDMAC_GTYPE (0x40078000) /**< (XDMAC) Global Type Register */
#define REG_XDMAC_GCFG (0x40078004) /**< (XDMAC) Global Configuration Register */
#define REG_XDMAC_GWAC (0x40078008) /**< (XDMAC) Global Weighted Arbiter Configuration Register */
#define REG_XDMAC_GIE (0x4007800C) /**< (XDMAC) Global Interrupt Enable Register */
#define REG_XDMAC_GID (0x40078010) /**< (XDMAC) Global Interrupt Disable Register */
#define REG_XDMAC_GIM (0x40078014) /**< (XDMAC) Global Interrupt Mask Register */
#define REG_XDMAC_GIS (0x40078018) /**< (XDMAC) Global Interrupt Status Register */
#define REG_XDMAC_GE (0x4007801C) /**< (XDMAC) Global Channel Enable Register */
#define REG_XDMAC_GD (0x40078020) /**< (XDMAC) Global Channel Disable Register */
#define REG_XDMAC_GS (0x40078024) /**< (XDMAC) Global Channel Status Register */
#define REG_XDMAC_GRS (0x40078028) /**< (XDMAC) Global Channel Read Suspend Register */
#define REG_XDMAC_GWS (0x4007802C) /**< (XDMAC) Global Channel Write Suspend Register */
#define REG_XDMAC_GRWS (0x40078030) /**< (XDMAC) Global Channel Read Write Suspend Register */
#define REG_XDMAC_GRWR (0x40078034) /**< (XDMAC) Global Channel Read Write Resume Register */
#define REG_XDMAC_GSWR (0x40078038) /**< (XDMAC) Global Channel Software Request Register */
#define REG_XDMAC_GSWS (0x4007803C) /**< (XDMAC) Global Channel Software Request Status Register */
#define REG_XDMAC_GSWF (0x40078040) /**< (XDMAC) Global Channel Software Flush Request Register */
#else
#define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 0 */
#define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 0 */
#define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 0 */
#define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 0 */
#define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< (XDMAC) Channel Source Address Register (chid = 0) 0 */
#define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 0 */
#define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 0 */
#define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 0 */
#define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 0 */
#define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< (XDMAC) Channel Block Control Register (chid = 0) 0 */
#define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< (XDMAC) Channel Configuration Register (chid = 0) 0 */
#define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 0 */
#define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 0 */
#define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 0 */
#define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 1 */
#define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 1 */
#define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 1 */
#define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 1 */
#define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 1 */
#define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 1 */
#define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 1 */
#define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 1 */
#define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 1 */
#define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 1 */
#define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 1 */
#define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 1 */
#define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 1 */
#define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 1 */
#define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 2 */
#define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 2 */
#define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 2 */
#define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 2 */
#define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 2 */
#define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 2 */
#define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 2 */
#define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 2 */
#define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 2 */
#define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 2 */
#define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 2 */
#define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 2 */
#define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 2 */
#define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 2 */
#define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 3 */
#define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 3 */
#define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 3 */
#define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 3 */
#define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< (XDMAC) Channel Source Address Register (chid = 0) 3 */
#define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 3 */
#define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 3 */
#define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 3 */
#define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 3 */
#define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< (XDMAC) Channel Block Control Register (chid = 0) 3 */
#define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< (XDMAC) Channel Configuration Register (chid = 0) 3 */
#define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 3 */
#define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 3 */
#define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 3 */
#define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 4 */
#define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 4 */
#define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 4 */
#define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 4 */
#define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< (XDMAC) Channel Source Address Register (chid = 0) 4 */
#define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 4 */
#define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 4 */
#define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 4 */
#define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 4 */
#define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< (XDMAC) Channel Block Control Register (chid = 0) 4 */
#define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< (XDMAC) Channel Configuration Register (chid = 0) 4 */
#define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 4 */
#define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 4 */
#define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 4 */
#define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 5 */
#define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 5 */
#define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 5 */
#define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 5 */
#define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 5 */
#define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 5 */
#define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 5 */
#define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 5 */
#define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 5 */
#define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 5 */
#define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 5 */
#define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 5 */
#define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 5 */
#define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 5 */
#define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 6 */
#define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 6 */
#define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 6 */
#define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 6 */
#define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 6 */
#define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 6 */
#define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 6 */
#define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 6 */
#define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 6 */
#define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 6 */
#define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 6 */
#define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 6 */
#define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 6 */
#define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 6 */
#define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 7 */
#define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 7 */
#define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 7 */
#define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 7 */
#define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< (XDMAC) Channel Source Address Register (chid = 0) 7 */
#define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 7 */
#define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 7 */
#define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 7 */
#define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 7 */
#define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< (XDMAC) Channel Block Control Register (chid = 0) 7 */
#define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< (XDMAC) Channel Configuration Register (chid = 0) 7 */
#define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 7 */
#define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 7 */
#define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 7 */
#define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 8 */
#define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 8 */
#define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 8 */
#define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 8 */
#define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< (XDMAC) Channel Source Address Register (chid = 0) 8 */
#define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 8 */
#define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 8 */
#define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 8 */
#define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 8 */
#define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< (XDMAC) Channel Block Control Register (chid = 0) 8 */
#define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< (XDMAC) Channel Configuration Register (chid = 0) 8 */
#define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 8 */
#define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 8 */
#define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 8 */
#define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 9 */
#define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 9 */
#define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 9 */
#define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 9 */
#define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 9 */
#define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 9 */
#define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 9 */
#define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 9 */
#define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 9 */
#define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 9 */
#define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 9 */
#define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 9 */
#define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 9 */
#define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 9 */
#define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 10 */
#define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 10 */
#define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 10 */
#define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 10 */
#define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 10 */
#define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 10 */
#define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 10 */
#define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 10 */
#define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 10 */
#define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 10 */
#define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 10 */
#define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 10 */
#define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 10 */
#define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 10 */
#define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 11 */
#define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 11 */
#define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 11 */
#define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 11 */
#define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< (XDMAC) Channel Source Address Register (chid = 0) 11 */
#define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 11 */
#define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 11 */
#define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 11 */
#define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 11 */
#define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< (XDMAC) Channel Block Control Register (chid = 0) 11 */
#define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< (XDMAC) Channel Configuration Register (chid = 0) 11 */
#define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 11 */
#define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 11 */
#define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 11 */
#define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 12 */
#define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 12 */
#define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 12 */
#define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 12 */
#define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< (XDMAC) Channel Source Address Register (chid = 0) 12 */
#define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 12 */
#define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 12 */
#define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 12 */
#define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 12 */
#define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< (XDMAC) Channel Block Control Register (chid = 0) 12 */
#define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< (XDMAC) Channel Configuration Register (chid = 0) 12 */
#define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 12 */
#define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 12 */
#define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 12 */
#define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 13 */
#define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 13 */
#define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 13 */
#define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 13 */
#define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 13 */
#define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 13 */
#define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 13 */
#define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 13 */
#define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 13 */
#define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 13 */
#define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 13 */
#define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 13 */
#define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 13 */
#define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 13 */
#define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 14 */
#define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 14 */
#define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 14 */
#define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 14 */
#define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 14 */
#define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 14 */
#define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 14 */
#define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 14 */
#define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 14 */
#define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 14 */
#define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 14 */
#define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 14 */
#define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 14 */
#define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 14 */
#define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 15 */
#define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 15 */
#define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 15 */
#define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 15 */
#define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< (XDMAC) Channel Source Address Register (chid = 0) 15 */
#define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 15 */
#define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 15 */
#define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 15 */
#define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 15 */
#define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< (XDMAC) Channel Block Control Register (chid = 0) 15 */
#define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< (XDMAC) Channel Configuration Register (chid = 0) 15 */
#define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 15 */
#define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 15 */
#define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 15 */
#define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 16 */
#define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 16 */
#define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 16 */
#define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 16 */
#define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< (XDMAC) Channel Source Address Register (chid = 0) 16 */
#define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 16 */
#define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 16 */
#define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 16 */
#define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 16 */
#define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< (XDMAC) Channel Block Control Register (chid = 0) 16 */
#define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< (XDMAC) Channel Configuration Register (chid = 0) 16 */
#define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 16 */
#define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 16 */
#define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 16 */
#define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 17 */
#define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 17 */
#define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 17 */
#define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 17 */
#define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 17 */
#define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 17 */
#define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 17 */
#define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 17 */
#define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 17 */
#define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 17 */
#define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 17 */
#define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 17 */
#define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 17 */
#define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 17 */
#define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 18 */
#define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 18 */
#define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 18 */
#define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 18 */
#define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 18 */
#define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 18 */
#define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 18 */
#define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 18 */
#define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 18 */
#define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 18 */
#define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 18 */
#define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 18 */
#define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 18 */
#define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 18 */
#define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 19 */
#define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 19 */
#define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 19 */
#define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 19 */
#define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< (XDMAC) Channel Source Address Register (chid = 0) 19 */
#define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 19 */
#define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 19 */
#define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 19 */
#define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 19 */
#define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< (XDMAC) Channel Block Control Register (chid = 0) 19 */
#define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< (XDMAC) Channel Configuration Register (chid = 0) 19 */
#define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 19 */
#define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 19 */
#define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 19 */
#define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 20 */
#define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 20 */
#define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 20 */
#define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 20 */
#define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< (XDMAC) Channel Source Address Register (chid = 0) 20 */
#define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 20 */
#define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 20 */
#define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 20 */
#define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 20 */
#define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< (XDMAC) Channel Block Control Register (chid = 0) 20 */
#define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< (XDMAC) Channel Configuration Register (chid = 0) 20 */
#define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 20 */
#define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 20 */
#define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 20 */
#define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 21 */
#define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 21 */
#define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 21 */
#define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 21 */
#define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 21 */
#define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 21 */
#define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 21 */
#define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 21 */
#define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 21 */
#define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 21 */
#define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 21 */
#define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 21 */
#define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 21 */
#define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 21 */
#define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 22 */
#define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 22 */
#define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 22 */
#define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 22 */
#define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< (XDMAC) Channel Source Address Register (chid = 0) 22 */
#define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 22 */
#define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 22 */
#define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 22 */
#define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 22 */
#define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< (XDMAC) Channel Block Control Register (chid = 0) 22 */
#define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< (XDMAC) Channel Configuration Register (chid = 0) 22 */
#define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 22 */
#define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 22 */
#define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 22 */
#define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< (XDMAC) Channel Interrupt Enable Register (chid = 0) 23 */
#define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< (XDMAC) Channel Interrupt Disable Register (chid = 0) 23 */
#define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0) 23 */
#define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< (XDMAC) Channel Interrupt Status Register (chid = 0) 23 */
#define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< (XDMAC) Channel Source Address Register (chid = 0) 23 */
#define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< (XDMAC) Channel Destination Address Register (chid = 0) 23 */
#define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< (XDMAC) Channel Next Descriptor Address Register (chid = 0) 23 */
#define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< (XDMAC) Channel Next Descriptor Control Register (chid = 0) 23 */
#define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< (XDMAC) Channel Microblock Control Register (chid = 0) 23 */
#define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< (XDMAC) Channel Block Control Register (chid = 0) 23 */
#define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< (XDMAC) Channel Configuration Register (chid = 0) 23 */
#define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) 23 */
#define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< (XDMAC) Channel Source Microblock Stride (chid = 0) 23 */
#define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< (XDMAC) Channel Destination Microblock Stride (chid = 0) 23 */
#define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< (XDMAC) Global Type Register */
#define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< (XDMAC) Global Configuration Register */
#define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< (XDMAC) Global Weighted Arbiter Configuration Register */
#define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< (XDMAC) Global Interrupt Enable Register */
#define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< (XDMAC) Global Interrupt Disable Register */
#define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< (XDMAC) Global Interrupt Mask Register */
#define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< (XDMAC) Global Interrupt Status Register */
#define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< (XDMAC) Global Channel Enable Register */
#define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< (XDMAC) Global Channel Disable Register */
#define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< (XDMAC) Global Channel Status Register */
#define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< (XDMAC) Global Channel Read Suspend Register */
#define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< (XDMAC) Global Channel Write Suspend Register */
#define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< (XDMAC) Global Channel Read Write Suspend Register */
#define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< (XDMAC) Global Channel Read Write Resume Register */
#define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< (XDMAC) Global Channel Software Request Register */
#define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< (XDMAC) Global Channel Software Request Status Register */
#define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< (XDMAC) Global Channel Software Flush Request Register */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance Parameter definitions for XDMAC peripheral ========== */
#define XDMAC_INSTANCE_ID 58
#define XDMAC_CLOCK_ID 58
#endif /* _SAME70_XDMAC_INSTANCE_ */

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