drivers: esp32: SDHC implementation

Implementation of SDHC driver for ESP32

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>

drivers/sdhc/CMakeLists.txt

@@ -10,4 +10,5 @@ zephyr_library_sources_ifdef(CONFIG_SAM_HSMCI sam_hsmci.c)
 zephyr_library_sources_ifdef(CONFIG_INTEL_EMMC_HOST intel_emmc_host.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c)
 zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
 endif()

drivers/sdhc/Kconfig

@@ -15,6 +15,7 @@ source "drivers/sdhc/Kconfig.mcux_sdif"
 source "drivers/sdhc/Kconfig.sam_hsmci"
 source "drivers/sdhc/Kconfig.intel"
 source "drivers/sdhc/Kconfig.sdhc_cdns"
+source "drivers/sdhc/Kconfig.esp32"
 
 config SDHC_INIT_PRIORITY
 	int "SDHC driver init priority"

drivers/sdhc/Kconfig.esp32

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX -License-Identifier: Apache-2.0
+
+config SDHC_ESP32
+	bool "ESP32 SDHC Driver"
+	default y
+	depends on DT_HAS_ESPRESSIF_ESP32_SDHC_SLOT_ENABLED
+	select SDHC_SUPPORTS_NATIVE_MODE
+	select PINCTRL
+	help
+	  Enables the ESP32 SD Host controller driver
+
+if SDHC_ESP32
+
+# ESP32 DMA needs 32 bit aligned buffers
+config SDHC_BUFFER_ALIGNMENT
+	default 4
+
+endif

drivers/sdhc/sdhc_esp32.h

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define SDMMC_FREQ_DEFAULT   20000 /*!< SD/MMC Default speed (limited by clock divider) */
+#define SDMMC_FREQ_HIGHSPEED 40000 /*!< SD High speed (limited by clock divider) */
+#define SDMMC_FREQ_PROBING   400   /*!< SD/MMC probing speed */
+#define SDMMC_FREQ_52M       52000 /*!< MMC 52MHz speed */
+#define SDMMC_FREQ_26M       26000 /*!< MMC 26MHz speed */
+
+#define SDMMC_DATA_ERR_MASK                                                                        \
+	(uint32_t)(SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC | SDMMC_INTMASK_HTO |                    \
+		   SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE)
+
+#define SDMMC_DMA_DONE_MASK                                                                        \
+	(uint32_t)(SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI | SDMMC_IDMAC_INTMASK_NI)
+
+#define SDMMC_CMD_ERR_MASK                                                                         \
+	(uint32_t)(SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC | SDMMC_INTMASK_RESP_ERR)
+
+enum sdmmc_req_state {
+	SDMMC_IDLE,
+	SDMMC_SENDING_CMD,
+	SDMMC_SENDING_DATA,
+	SDMMC_BUSY,
+};
+
+/* SDHC command flags */
+#define SCF_ITSDONE     0x0001 /*!< command is complete */
+#define SCF_CMD(flags)  ((flags) & 0x00f0)
+#define SCF_CMD_AC      0x0000
+#define SCF_CMD_ADTC    0x0010
+#define SCF_CMD_BC      0x0020
+#define SCF_CMD_BCR     0x0030
+#define SCF_CMD_READ    0x0040 /*!< read command (data expected) */
+#define SCF_RSP_BSY     0x0100
+#define SCF_RSP_136     0x0200
+#define SCF_RSP_CRC     0x0400
+#define SCF_RSP_IDX     0x0800
+#define SCF_RSP_PRESENT 0x1000
+/* response types */
+#define SCF_RSP_R0      0 /*!< none */
+#define SCF_RSP_R1      (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
+#define SCF_RSP_R1B     (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX | SCF_RSP_BSY)
+#define SCF_RSP_R2      (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_136)
+#define SCF_RSP_R3      (SCF_RSP_PRESENT)
+#define SCF_RSP_R4      (SCF_RSP_PRESENT)
+#define SCF_RSP_R5      (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
+#define SCF_RSP_R5B     (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX | SCF_RSP_BSY)
+#define SCF_RSP_R6      (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
+#define SCF_RSP_R7      (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
+/* special flags */
+#define SCF_WAIT_BUSY   0x2000 /*!< Wait for completion of card busy signal before returning */
+
+#define SD_OCR_SDHC_CAP (1 << 30)
+#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
+
+/* For debug only */
+static const char *const timingStr[] = {"UNKNOWN", "LEGACY", "HS",    "SDR12", "SDR25", "SDR50",
+					"SDR104",  "DDR50",  "DDR52", "HS200", "HS400"};
+
+struct sdmmc_transfer_state {
+	uint8_t *ptr;
+	size_t size_remaining;
+	size_t next_desc;
+	size_t desc_remaining;
+};
+
+struct sdmmc_event {
+	uint32_t header_DUMMY; /* Reserved for system use (Zephyr message queue) */
+	uint32_t sdmmc_status; /* masked SDMMC interrupt status */
+	uint32_t dma_status;   /* masked DMA interrupt status */
+};
+
+/**
+ * Host contexts
+ */
+struct host_ctx {
+	intr_handle_t intr_handle;
+	struct k_msgq *event_queue;
+};
+
+/**
+ * SD/MMC command information
+ */
+struct sdmmc_command {
+	uint32_t opcode;      /*!< SD or MMC command index */
+	uint32_t arg;         /*!< SD/MMC command argument */
+	uint32_t response[4]; /*!< response buffer */
+	void *data;           /*!< buffer to send or read into */
+	size_t datalen;       /*!< length of data in the buffer */
+	size_t buflen;        /*!< length of the buffer */
+	size_t blklen;        /*!< block length */
+	int flags;            /*!< see below */
+	esp_err_t error;      /*!< error returned from transfer */
+	uint32_t timeout_ms;  /*!< response timeout, in milliseconds */
+};
+
+/**
+ * @brief Convert ESP to Zephyr error codes
+ *
+ * @param ret_esp ESP return value
+ *
+ * @return Zephyr error code
+ */
+static __attribute__((always_inline)) inline int err_esp2zep(int ret_esp)
+{
+	int ret;
+
+	switch (ret_esp) {
+	/* Treating the error codes most relevant to be individuated */
+	case ESP_ERR_INVALID_ARG:
+		ret = -EINVAL;
+		break;
+	case ESP_ERR_TIMEOUT:
+		ret = -ETIMEDOUT;
+		break;
+	case ESP_ERR_NOT_FOUND:
+		ret = -ENODEV; /* SD card not inserted (requires CD signal) */
+		break;
+	case ESP_ERR_INVALID_STATE:
+		ret = -EACCES; /* SD card write-protected (requires WP sinal) */
+		break;
+	default:
+		ret = -EIO;
+		break;
+	}
+
+	return ret;
+}

dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml

@@ -0,0 +1,76 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif ESP32 SDHC controller slot
+
+compatible: "espressif,esp32-sdhc-slot"
+
+include: [sdhc.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  bus-width:
+    type: int
+    enum:
+      - 1
+      - 4
+    default: 4
+    description: SD bus width in bits
+
+  clk-pin:
+    type: int
+    description: |
+      Clock pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  cmd-pin:
+    type: int
+    description: |
+      Command pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  d0-pin:
+    type: int
+    description: |
+      Data 0 pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  d1-pin:
+    type: int
+    description: |
+      Data 1 pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  d2-pin:
+    type: int
+    description: |
+      Data 2 pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  d3-pin:
+    type: int
+    description: |
+      Data 3 pin for ESP32 and SoC models with fixed pins for SDIO.
+      For devices with GPIO matrix support, configuration shall be done
+      using pin control (pinctrl-0 field).
+
+  pwr-gpios:
+    type: phandle-array
+    description: |
+      Power pin
+      This is a configurable pin to deliver power supply to the SD card.
+      It is configured as a GPIO in order to execute power toggles and
+      reinitialize the SD slave when necessary.

dts/bindings/sdhc/espressif,esp32-sdhc.yaml

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Espressif ESP32 SDHC controller
+
+compatible: "espressif,esp32-sdhc"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true

dts/xtensa/espressif/esp32/esp32_common.dtsi

@@ -425,5 +425,26 @@
 			status = "disabled";
 		};
 
+		sdhc: sdhc@3ff68000 {
+			compatible = "espressif,esp32-sdhc";
+			reg = <0x3ff68000 0x1000>;
+			interrupts = <SDIO_HOST_INTR_SOURCE>;
+			interrupt-parent = <&intc>;
+			clocks = <&rtc ESP32_SDMMC_MODULE>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sdhc0: sdhc@0 {
+				compatible = "espressif,esp32-sdhc-slot";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			sdhc1: sdhc@1 {
+				compatible = "espressif,esp32-sdhc-slot";
+				reg = <1>;
+				status = "disabled";
+			};
+		};
 	};
 };

include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h

@@ -8133,6 +8133,164 @@
 #define PCNT7_CH1SIG_GPIO39 \
 	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
+/* SDHC0_CD */
+#define SDHC0_CD_GPIO5 \
+	ESP32_PINMUX(5, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO6 \
+	ESP32_PINMUX(6, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO7 \
+	ESP32_PINMUX(7, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO8 \
+	ESP32_PINMUX(8, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO9 \
+	ESP32_PINMUX(9, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO10 \
+	ESP32_PINMUX(10, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO11 \
+	ESP32_PINMUX(11, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO16 \
+	ESP32_PINMUX(16, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO17 \
+	ESP32_PINMUX(17, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO18 \
+	ESP32_PINMUX(18, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO19 \
+	ESP32_PINMUX(19, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO20 \
+	ESP32_PINMUX(20, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO21 \
+	ESP32_PINMUX(21, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO22 \
+	ESP32_PINMUX(22, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO23 \
+	ESP32_PINMUX(23, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO25 \
+	ESP32_PINMUX(25, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO26 \
+	ESP32_PINMUX(26, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO27 \
+	ESP32_PINMUX(27, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO32 \
+	ESP32_PINMUX(32, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO33 \
+	ESP32_PINMUX(33, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO34 \
+	ESP32_PINMUX(34, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO35 \
+	ESP32_PINMUX(35, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO36 \
+	ESP32_PINMUX(36, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO37 \
+	ESP32_PINMUX(37, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO38 \
+	ESP32_PINMUX(38, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+#define SDHC0_CD_GPIO39 \
+	ESP32_PINMUX(39, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+
+/* SDHC0_WP */
+#define SDHC0_WP_GPIO5 \
+	ESP32_PINMUX(5, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO6 \
+	ESP32_PINMUX(6, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO7 \
+	ESP32_PINMUX(7, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO8 \
+	ESP32_PINMUX(8, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO9 \
+	ESP32_PINMUX(9, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO10 \
+	ESP32_PINMUX(10, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO11 \
+	ESP32_PINMUX(11, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO16 \
+	ESP32_PINMUX(16, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO17 \
+	ESP32_PINMUX(17, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO18 \
+	ESP32_PINMUX(18, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO19 \
+	ESP32_PINMUX(19, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO20 \
+	ESP32_PINMUX(20, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO21 \
+	ESP32_PINMUX(21, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO22 \
+	ESP32_PINMUX(22, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO23 \
+	ESP32_PINMUX(23, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO25 \
+	ESP32_PINMUX(25, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO26 \
+	ESP32_PINMUX(26, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO27 \
+	ESP32_PINMUX(27, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO32 \
+	ESP32_PINMUX(32, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO33 \
+	ESP32_PINMUX(33, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO34 \
+	ESP32_PINMUX(34, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO35 \
+	ESP32_PINMUX(35, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO36 \
+	ESP32_PINMUX(36, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO37 \
+	ESP32_PINMUX(37, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO38 \
+	ESP32_PINMUX(38, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
+#define SDHC0_WP_GPIO39 \
+	ESP32_PINMUX(39, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+
 /* SMI_MDC */
 #define SMI_MDC_GPIO0 \
 	ESP32_PINMUX(0, ESP_NOSIG, ESP_EMAC_MDC_O)