dts: mbox: add PolarFire SoC mailbox interface

Add Microchip's PolarFire SoC mailbox node.

Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>

dts/bindings/mbox/microchip,mpfs-mailbox.yaml

@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2024 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+  compatible:
+    const: microchip,mpfs-mailbox
+
+  reg:
+    - items:
+        - description: mailbox control registers
+        - description: mailbox interrupt registers
+        - description: mailbox data registers
+
+  interrupts:
+    maxItems: 1
+
+  "#mbox-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+      mbox: mailbox@37020000 {
+        compatible = "microchip,mpfs-mailbox";
+        reg = <0x37020000 0x58>, <0x2000318C 0x40>,
+              <0x37020800 0x100>;
+        interrupt-parent = <&L1>;
+        interrupts = <96>;
+        #mbox-cells = <1>;
+      };
+    };

dts/riscv/microchip/mpfs.dtsi

@@ -129,6 +129,16 @@
 			riscv,ndev = <186>;
 		};
 
+		mbox: mailbox@37020000 {
+			compatible = "microchip,mpfs-mailbox";
+			reg = <0x37020000 0x58>, <0x2000318C 0x40>,
+				<0x37020800 0x100>;
+			interrupt-parent = <&plic>;
+			interrupts = <96 1>;
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
 		uart0: uart@20000000 {
 			compatible = "ns16550";
 			reg = <0x20000000 0x1000>;