From f5728c298dce210cf72e1ab5dc9cd7174a299c8a Mon Sep 17 00:00:00 2001 From: Jaroslaw Stelter Date: Mon, 19 Sep 2022 15:22:00 +0200 Subject: [PATCH] intel_adsp: ace20_lnl: add initial ace 2.0 (LNL) board definition This commit adds definition of ACE 2.0 Lunar Lake board.board. Signed-off-by: Krzysztof Frydryk Signed-off-by: Jaroslaw Stelter Signed-off-by: Anas Nashif --- .../xtensa/intel_adsp_ace20_lnl/Kconfig.board | 8 + .../intel_adsp_ace20_lnl/Kconfig.defconfig | 10 + .../xtensa/intel_adsp_ace20_lnl/board.cmake | 5 + .../intel_adsp_ace20_lnl.dts | 18 + .../intel_adsp_ace20_lnl.yaml | 14 + .../intel_adsp_ace20_lnl_defconfig | 14 + dts/bindings/dma/intel,adsp-hda.yaml | 3 + dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 364 ++++++++++++++++++ 8 files changed, 436 insertions(+) create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/board.cmake create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml create mode 100644 boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig create mode 100644 dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board new file mode 100644 index 0000000000..26994dfb6c --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board @@ -0,0 +1,8 @@ +# Xtensa board configuration + +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADSP_ACE20_LNL + bool "Intel ADSP ACE 2.0 Lunar Lake PCH" + depends on SOC_SERIES_INTEL_ACE diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig new file mode 100644 index 0000000000..756481eba0 --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_INTEL_ADSP_ACE20_LNL + +config BOARD + default "intel_adsp_ace20_lnl" + +endif # BOARD_INTEL_ADSP_ACE20_LNL diff --git a/boards/xtensa/intel_adsp_ace20_lnl/board.cmake b/boards/xtensa/intel_adsp_ace20_lnl/board.cmake new file mode 100644 index 0000000000..5a24853aa9 --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS acesim) + +board_set_rimage_target(lnl) diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts new file mode 100644 index 0000000000..0b4dc75cc8 --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "intel_adsp_ace20_lnl"; + compatible = "intel"; + + chosen { + zephyr,sram = &sram0; + }; +}; diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml new file mode 100644 index 0000000000..cec6609aa7 --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml @@ -0,0 +1,14 @@ +identifier: intel_adsp_ace20_lnl +name: ACE 2.0 LNL Audio DSP +type: mcu +arch: xtensa +toolchain: + - xcc + - xt-clang +supported: + - dma +testing: + ignore_tags: + - net + - bluetooth + - mcumgr diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig new file mode 100644 index 0000000000..760715a855 --- /dev/null +++ b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_SOC_SERIES_INTEL_ACE=y +CONFIG_SOC_INTEL_ACE20_LNL=y +CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y diff --git a/dts/bindings/dma/intel,adsp-hda.yaml b/dts/bindings/dma/intel,adsp-hda.yaml index e9732412f1..9594fde43b 100644 --- a/dts/bindings/dma/intel,adsp-hda.yaml +++ b/dts/bindings/dma/intel,adsp-hda.yaml @@ -23,3 +23,6 @@ properties: "dma-copy-alignment": required: true + +dma-cells: + - channel diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi new file mode 100644 index 0000000000..b48f08f921 --- /dev/null +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <0>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <1>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <2>; + cpu-power-states = <&d0i3 &d3>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "cdns,tensilica-xtensa-lx7"; + reg = <3>; + cpu-power-states = <&d0i3 &d3>; + }; + + }; + + power-states { + d0i3: idle { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + min-residency-us = <200>; + exit-latency-us = <100>; + }; + /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. + * The procedure is triggered by IPC from the HOST (SET_DX). + */ + d3: off { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <2147483647>; + exit-latency-us = <0>; + }; + }; + + sram0: memory@a0020000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0020000 DT_SIZE_K(2816)>; + }; + + sram1: memory@a0000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0xa0000000 DT_SIZE_K(64)>; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + audioclk: audio-clock { + compatible = "fixed-clock"; + clock-frequency = <24576000>; + #clock-cells = <0>; + }; + + pllclk: pll-clock { + compatible = "fixed-clock"; + clock-frequency = <96000000>; + #clock-cells = <0>; + }; + + IMR1: memory@A1000000 { + compatible = "intel,adsp-imr"; + reg = <0xA1000000 DT_SIZE_M(16)>; + block-size = <0x1000>; + zephyr,memory-region = "IMR1"; + }; + + soc { + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0x00 0x400>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + adsp_host_ipc: ace_host_ipc@73000 { + compatible = "intel,adsp-host-ipc"; + status = "okay"; + reg = <0x73000 0x30>; + interrupts = <0 0 0>; + interrupt-parent = <&ace_intc>; + }; + + adsp_idc: ace_idc@70400 { + compatible = "intel,adsp-idc"; + reg = <0x70400 0x0400>; + interrupts = <24 0 0>; + interrupt-parent = <&ace_intc>; + }; + + /* This is actually an array of per-core designware + * controllers, but the special setup and extra + * masking layer makes it easier for LNL to handle + * this internally. + */ + ace_intc: ace_intc@7ac00 { + compatible = "intel,ace-intc"; + reg = <0x7ac00 0xc00>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <4 0 0>; + num-irqs = <28>; + interrupt-parent = <&core_intc>; + }; + + ace_timestamp: ace_timestamp@72040 { + compatible = "intel,ace-timestamp"; + reg = <0x72040 0x0032>; + }; + + ace_art_counter: ace_art_counter@72058 { + compatible = "intel,ace-art-counter"; + reg = <0x72058 0x0064>; + }; + + ace_rtc_counter: ace_rtc_counter@72008 { + compatible = "intel,ace-rtc-counter"; + reg = <0x72008 0x0064>; + }; + + lps: lps@71ac0 { + compatible = "intel,adsp-lps"; + reg = <0x00071ac0 0x100>; + }; + + sspbase: ssp_base@28000 { + compatible = "intel,ssp-sspbase"; + reg = <0x28000 0x1000>; + }; + + win: win@70200 { + compatible = "intel,cavs-win"; + reg = <0x70200 0x30>; + }; + + tlb: tlb@17e000 { + compatible = "intel,adsp-tlb"; + reg = <0x17e000 0x1000>; + paddr-size = <12>; + exec-bit-idx = <14>; + write-bit-idx= <15>; + }; + + hda_host_out: dma@72800 { + compatible = "intel,adsp-hda-host-out"; + #dma-cells = <1>; + reg = <0x00072800 0x40>; + dma-channels = <9>; + dma-buf-alignment = <128>; + status = "okay"; + }; + + hda_host_in: dma@72c00 { + compatible = "intel,adsp-hda-host-in"; + #dma-cells = <1>; + reg = <0x00072c00 0x40>; + dma-channels = <11>; + dma-buf-alignment = <128>; + status = "okay"; + }; + + hda_link_out: dma@79400 { + compatible = "intel,adsp-hda-link-out"; + #dma-cells = <1>; + reg = <0x00079400 0x40>; + dma-channels = <9>; + dma-buf-alignment = <128>; + status = "okay"; + }; + + hda_link_in: dma@79800 { + compatible = "intel,adsp-hda-link-in"; + #dma-cells = <1>; + reg = <0x00079800 0x40>; + dma-channels = <11>; + dma-buf-alignment = <128>; + status = "okay"; + }; + + dmic0: dai-dmic@10000 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0xcc0 0x10>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + }; + + dmic1: dai-dmic@10001 { + compatible = "intel,dai-dmic"; + reg = <0x10100 0x8000>; + shim = <0xcc0 0x10>; + interrupts = <0x08 0 0>; + interrupt-parent = <&ace_intc>; + }; + + ssp0:ssp@28100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00028100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x00 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 1 + &hda_link_in 1>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + ssp1:ssp@29100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00029100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x01 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 2 + &hda_link_in 2>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + ssp2:ssp@2a100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002a100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x02 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 3 + &hda_link_in 3>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + ssp3:ssp@2b100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002b100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x03 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 4 + &hda_link_in 4>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + ssp4:ssp@2c100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002c100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x04 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 5 + &hda_link_in 5>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + ssp5:ssp@2d100 { + compatible = "intel,ssp-dai"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0002d100 0x1000 + 0x00079C00 0x200>; + interrupts = <0x04 0 0>; + interrupt-parent = <&ace_intc>; + dmas = <&hda_link_out 6 + &hda_link_in 6>; + dma-names = "tx", "rx"; + power-domain = <&io0_domain>; + status = "okay"; + }; + + hub_ulp_domain: hub_ulp_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <15>; + }; + hub_hp_domain: hub_hpp_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <6>; + }; + io0_domain: io0_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <8>; + }; + io1_domain: io1_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <9>; + }; + io2_domain: io2_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <10>; + }; + io3_domain: io3_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <11>; + }; + hst_domain: hst_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <4>; + }; + ml0_domain: ml0_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <12>; + }; + ml1_domain: ml1_domain { + compatible = "intel,adsp-power-domain"; + lps = <&lps>; + bit-position = <13>; + }; + }; +};