patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 7 Packages Projects Releases Wiki Activity

tests: drivers: pinctrl: gd32: add DT AF parse test

Browse source 
Add a test to check that DT information for AF model is extracted
correctly.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2021-11-01 22:52:54 +01:00 committed by Anas Nashif
parent d702e74854
commit f5ed5e6d0f
6 changed files with 228 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
tests/drivers/pinctrl/gd32/CMakeLists.txt Normal file
View file

@ -0,0 +1,12 @@
# Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(pinctrl_gd32)
target_sources(app PRIVATE ../common/test_device.c)
if(CONFIG_PINCTRL_GD32_AF)
target_sources(app PRIVATE src/main_af.c)
endif()

13
tests/drivers/pinctrl/gd32/Kconfig Normal file
View file

@ -0,0 +1,13 @@
# Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
mainmenu "pinctrl GD32 DT Test"
source "Kconfig.zephyr"
config PINCTRL_TEST_NON_STATIC
bool "Enable access to pin control configuration"
select PINCTRL_NON_STATIC
help
This option should be selected by unit tests that need to access the pin
control configuration defined in a device driver.

63
tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay Normal file
View file

@ -0,0 +1,63 @@
/*
* Copyright (c) 2021 Teslabs Engineering S.L.
* SPDX-License-Identifier: Apache-2.0
*/
/ {
test_device: test_device {
compatible = "vnd,pinctrl-device";
pinctrl-0 = <&test_device_default>;
pinctrl-names = "default";
};
};
&pinctrl {
test_device_default: test_device_default {
/* Note: the groups are just meant for testing if properties and
pins are parsed correctly, but do not necessarily represent a
feasible combination */
pins1 {
pinmux = <GD32_PINMUX_AF('A', 0, AF0)>,
<GD32_PINMUX_AF('B', 1, AF1)>;
};
pins2 {
pinmux = <GD32_PINMUX_AF('C', 2, AF2)>;
drive-push-pull;
};
pins3 {
pinmux = <GD32_PINMUX_AF('A', 3, AF3)>;
drive-open-drain;
};
pins4 {
pinmux = <GD32_PINMUX_AF('B', 4, AF4)>;
bias-disable;
};
pins5 {
pinmux = <GD32_PINMUX_AF('C', 5, AF5)>;
bias-pull-up;
};
pins6 {
pinmux = <GD32_PINMUX_AF('A', 6, AF6)>;
bias-pull-down;
};
pins7 {
pinmux = <GD32_PINMUX_AF('B', 7, AF7)>;
slew-rate = "max-speed-2mhz";
};
pins8 {
pinmux = <GD32_PINMUX_AF('C', 8, AF8)>;
slew-rate = "max-speed-25mhz";
};
pins9 {
pinmux = <GD32_PINMUX_AF('A', 9, AF9)>;
slew-rate = "max-speed-50mhz";
};
pins10 {
pinmux = <GD32_PINMUX_AF('B', 10, AF10)>;
slew-rate = "max-speed-200mhz";
};
pins11 {
pinmux = <GD32_PINMUX_AF('C', 11, ANALOG)>;
};
};
};

5
tests/drivers/pinctrl/gd32/prj.conf Normal file
View file

@ -0,0 +1,5 @@
# Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
CONFIG_ZTEST=y
CONFIG_PINCTRL_TEST_NON_STATIC=y

128
tests/drivers/pinctrl/gd32/src/main_af.c Normal file
View file

@ -0,0 +1,128 @@
/*
* Copyright (c) 2021 Teslabs Engineering S.L.
* SPDX-License-Identifier: Apache-2.0
*/
#include <drivers/pinctrl.h>
#include <ztest.h>
/* pin configuration for test device */
#define TEST_DEVICE DT_NODELABEL(test_device)
PINCTRL_DT_DEV_CONFIG_DECLARE(TEST_DEVICE);
static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE);
static void test_dt_extract(void)
{
const struct pinctrl_state *scfg;
pinctrl_soc_pin_t pin;
zassert_equal(pcfg->state_cnt, 1U, NULL);
scfg = &pcfg->states[0];
zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT, NULL);
zassert_equal(scfg->pin_cnt, 12U, NULL);
pin = scfg->pins[0];
zassert_equal(GD32_PORT_GET(pin), 0, NULL);
zassert_equal(GD32_PIN_GET(pin), 0, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF0, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[1];
zassert_equal(GD32_PORT_GET(pin), 1, NULL);
zassert_equal(GD32_PIN_GET(pin), 1, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF1, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[2];
zassert_equal(GD32_PORT_GET(pin), 2, NULL);
zassert_equal(GD32_PIN_GET(pin), 2, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF2, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[3];
zassert_equal(GD32_PORT_GET(pin), 0, NULL);
zassert_equal(GD32_PIN_GET(pin), 3, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF3, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_OD, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[4];
zassert_equal(GD32_PORT_GET(pin), 1, NULL);
zassert_equal(GD32_PIN_GET(pin), 4, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF4, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[5];
zassert_equal(GD32_PORT_GET(pin), 2, NULL);
zassert_equal(GD32_PIN_GET(pin), 5, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF5, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLUP, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[6];
zassert_equal(GD32_PORT_GET(pin), 0, NULL);
zassert_equal(GD32_PIN_GET(pin), 6, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF6, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLDOWN, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[7];
zassert_equal(GD32_PORT_GET(pin), 1, NULL);
zassert_equal(GD32_PIN_GET(pin), 7, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF7, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
pin = scfg->pins[8];
zassert_equal(GD32_PORT_GET(pin), 2, NULL);
zassert_equal(GD32_PIN_GET(pin), 8, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF8, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_25MHZ, NULL);
pin = scfg->pins[9];
zassert_equal(GD32_PORT_GET(pin), 0, NULL);
zassert_equal(GD32_PIN_GET(pin), 9, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF9, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_50MHZ, NULL);
pin = scfg->pins[10];
zassert_equal(GD32_PORT_GET(pin), 1, NULL);
zassert_equal(GD32_PIN_GET(pin), 10, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_AF10, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_200MHZ, NULL);
pin = scfg->pins[11];
zassert_equal(GD32_PORT_GET(pin), 2, NULL);
zassert_equal(GD32_PIN_GET(pin), 11, NULL);
zassert_equal(GD32_AF_GET(pin), GD32_ANALOG, NULL);
zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
}
void test_main(void)
{
ztest_test_suite(pinctrl_gd32,
ztest_unit_test(test_dt_extract));
ztest_run_test_suite(pinctrl_gd32);
}

7
tests/drivers/pinctrl/gd32/testcase.yaml Normal file
View file

@ -0,0 +1,7 @@
# Copyright (c) 2021 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
tests:
drivers.pinctrl.gd32_af:
tags: drivers pinctrl
platform_allow: gd32f450i_eval