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soc: arm64: qemu-cortex-a53: Add MMU support

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Add qemu-cortex-a53 memory regions with proper attributes
to translation tables. Minimal regions to execute "hello_world"
are added as of now, More granular memory regions should be
added later as per the requirement.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
This commit is contained in:
Abhishek Shah 2019-12-23 15:53:53 +05:30 committed by Johan Hedberg
parent f587c5f019
commit f64cd1a5db
3 changed files with 37 additions and 0 deletions
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2
soc/arm/qemu_cortex_a53/CMakeLists.txt
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@ -1,2 +1,4 @@
# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

1
soc/arm/qemu_cortex_a53/dts_fixup.h
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@ -5,6 +5,7 @@
*/
#define DT_PL011_PORT0_BASE_ADDRESS DT_ARM_PL011_9000000_BASE_ADDRESS
#define DT_PL011_PORT0_SIZE DT_ARM_PL011_9000000_SIZE
#define DT_PL011_PORT0_NAME DT_ARM_PL011_9000000_LABEL
#define DT_PL011_PORT0_CLOCK_FREQUENCY DT_ARM_PL011_9000000_CLOCK_FREQUENCY
#define DT_PL011_PORT0_BAUD_RATE DT_ARM_PL011_9000000_CURRENT_SPEED

34
soc/arm/qemu_cortex_a53/mmu_regions.c Normal file
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@ -0,0 +1,34 @@
/*
* Copyright 2019 Broadcom
* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <arch/arm/aarch64/arm_mmu.h>
#include <dts_fixup.h>
#define SZ_1K 1024
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_INST_0_ARM_GIC_BASE_ADDRESS_0,
DT_INST_0_ARM_GIC_SIZE_0 * 2,
MT_DEVICE_nGnRnE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("UART",
DT_PL011_PORT0_BASE_ADDRESS,
DT_PL011_PORT0_SIZE,
MT_DEVICE_nGnRnE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("SRAM",
CONFIG_SRAM_BASE_ADDRESS,
CONFIG_SRAM_SIZE * SZ_1K,
MT_NORMAL | MT_RW | MT_SECURE),
};
const struct arm_mmu_config mmu_config = {
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
};