xtensa: mpu: introduce CONFIG_XTENSA_MPU_ONLY_SOC_RANGES
This allows the SoC to have total control on what MPU ranges to be programmed at boot. This overrides the generic ranges in the architecture core code. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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@ -243,6 +243,14 @@ config XTENSA_MPU_DEFAULT_MEM_TYPE
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If userspace is enabled, it will be used to restore the memory type of
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If userspace is enabled, it will be used to restore the memory type of
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the region being removed from a memory domain.
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the region being removed from a memory domain.
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config XTENSA_MPU_ONLY_SOC_RANGES
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bool
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help
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Enable this by the SoC to indicate to the architecture code to use
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the MPU ranges specified by SoC only, and skip the common ranges
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defined in the core architecture code. This gives total control to
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the SoC on the MPU ranges.
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endif # XTENSA_MPU
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endif # XTENSA_MPU
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endif # CPU_HAS_MPU
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endif # CPU_HAS_MPU
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@ -72,6 +72,7 @@ static struct xtensa_mpu_map xtensa_mpu_map_fg_kernel;
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* definied in the processor configuration.
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* definied in the processor configuration.
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*/
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*/
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#ifndef CONFIG_XTENSA_MPU_ONLY_SOC_RANGES
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/**
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/**
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* Static definition of all code and data memory regions of the
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* Static definition of all code and data memory regions of the
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* current Zephyr image. This information must be available and
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* current Zephyr image. This information must be available and
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@ -129,6 +130,7 @@ static const struct xtensa_mpu_range mpu_zephyr_ranges[] = {
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.memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE,
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.memory_type = CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE,
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},
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},
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};
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};
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#endif /* !CONFIG_XTENSA_MPU_ONLY_SOC_RANGES */
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/**
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/**
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* Return the pointer to the entry encompassing @a addr out of an array of MPU entries.
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* Return the pointer to the entry encompassing @a addr out of an array of MPU entries.
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@ -679,6 +681,7 @@ void xtensa_mpu_init(void)
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xtensa_mpu_map_fg_kernel.entries[entry] = ent;
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xtensa_mpu_map_fg_kernel.entries[entry] = ent;
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}
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}
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#ifndef CONFIG_XTENSA_MPU_ONLY_SOC_RANGES
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/*
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/*
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* Add necessary MPU entries for the memory regions of base Zephyr image.
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* Add necessary MPU entries for the memory regions of base Zephyr image.
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*/
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*/
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@ -696,6 +699,7 @@ void xtensa_mpu_init(void)
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(unsigned int)range->end,
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(unsigned int)range->end,
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ret);
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ret);
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}
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}
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#endif /* !CONFIG_XTENSA_MPU_ONLY_SOC_RANGES */
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/*
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/*
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* Now for the entries for memory regions needed by SoC.
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* Now for the entries for memory regions needed by SoC.
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