drivers: adc: add NXP S32 ADC SAR driver
Add support ADC SAR for NXP S32. ADC SAR diver support 3 group channels (precision, standard and external), run normal trigger in oneshot conversion mode with 2 callbacks normal end of conversion and normal end chain callbacks. An instance only run on 1 group channel and 1 kind of callback at the same time. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
This commit is contained in:
Cong Nguyen Huu
Mahesh Mahadevan
parent
3191d08130
commit
f809614136
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@ -43,3 +43,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_INFINEON_CAT1 adc_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SMARTBOND_GPADC adc_smartbond_gpadc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SMARTBOND_SDADC adc_smartbond_sdadc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_TLA2021 adc_tla2021.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NXP_S32_ADC_SAR adc_nxp_s32_adc_sar.c)
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@ -110,4 +110,6 @@ source "drivers/adc/Kconfig.smartbond"
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source "drivers/adc/Kconfig.tla2021"
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source "drivers/adc/Kconfig.nxp_s32"
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endif # ADC
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9
drivers/adc/Kconfig.nxp_s32
Normal file
9
drivers/adc/Kconfig.nxp_s32
Normal file
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@ -0,0 +1,9 @@
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# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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config ADC_NXP_S32_ADC_SAR
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bool "NXP S32 ADC SAR driver"
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default y
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depends on DT_HAS_NXP_S32_ADC_SAR_ENABLED
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help
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This option enables the NXP S32 ADC SAR driver.
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446
drivers/adc/adc_nxp_s32_adc_sar.c
Normal file
446
drivers/adc/adc_nxp_s32_adc_sar.c
Normal file
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@ -0,0 +1,446 @@
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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <Adc_Sar_Ip_HwAccess.h>
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#include <Adc_Sar_Ip.h>
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#include <Adc_Sar_Ip_Irq.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define DT_DRV_COMPAT nxp_s32_adc_sar
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LOG_MODULE_REGISTER(adc_nxp_s32_adc_sar, CONFIG_ADC_LOG_LEVEL);
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/* Convert channel of group ADC to channel of physical ADC instance */
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#define ADC_NXP_S32_GROUPCHAN_2_PHYCHAN(group, channel) \
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(ADC_SAR_IP_HW_REG_SIZE * group + channel)
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struct adc_nxp_s32_config {
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ADC_Type *base;
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uint8_t instance;
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uint8_t group_channel;
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uint8_t callback_select;
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Adc_Sar_Ip_ConfigType *adc_cfg;
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void (*irq_config_func)(const struct device *dev);
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const struct pinctrl_dev_config *pin_cfg;
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};
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struct adc_nxp_s32_data {
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const struct device *dev;
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *buf_end;
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uint16_t *repeat_buffer;
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uint32_t mask_channels;
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uint8_t num_channels;
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};
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static int adc_nxp_s32_init(const struct device *dev)
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{
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const struct adc_nxp_s32_config *config = dev->config;
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struct adc_nxp_s32_data *data = dev->data;
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Adc_Sar_Ip_StatusType status;
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/* This array shows max number of channels of each group */
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uint8_t map_chan_group[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN]
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= FEATURE_ADC_MAX_CHN_COUNT;
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data->num_channels = map_chan_group[config->instance][config->group_channel];
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if (config->pin_cfg) {
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if (pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT)) {
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return -EIO;
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}
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}
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status = Adc_Sar_Ip_Init(config->instance, config->adc_cfg);
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if (status) {
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return -EIO;
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}
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#if FEATURE_ADC_HAS_CALIBRATION
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status = Adc_Sar_Ip_DoCalibration(config->instance);
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if (status) {
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return -EIO;
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}
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#endif
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Adc_Sar_Ip_EnableNotifications(config->instance,
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config->callback_select ?
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ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN
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: ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC);
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data->dev = dev;
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config->irq_config_func(dev);
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static int adc_nxp_s32_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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struct adc_nxp_s32_data *data = dev->data;
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if (channel_cfg->channel_id >= data->num_channels) {
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LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Unsupported channel acquisition time");
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return -ENOTSUP;
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}
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Unsupported channel reference");
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return -ENOTSUP;
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}
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return 0;
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}
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static int adc_nxp_s32_validate_buffer_size(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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uint8_t active_channels = 0;
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size_t needed_size;
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active_channels = POPCOUNT(sequence->channels);
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needed_size = active_channels * sizeof(uint16_t);
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if (sequence->options) {
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needed_size *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed_size) {
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return -ENOSPC;
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}
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return 0;
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}
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#if FEATURE_ADC_HAS_AVERAGING
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static int adc_nxp_s32_set_averaging(const struct device *dev, uint8_t oversampling)
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{
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const struct adc_nxp_s32_config *config = dev->config;
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Adc_Sar_Ip_AvgSelectType avg_sel = ADC_SAR_IP_AVG_4_CONV;
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bool avg_en = true;
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switch (oversampling) {
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case 0:
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avg_en = false;
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break;
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case 2:
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avg_sel = ADC_SAR_IP_AVG_4_CONV;
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break;
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case 3:
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avg_sel = ADC_SAR_IP_AVG_8_CONV;
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break;
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case 4:
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avg_sel = ADC_SAR_IP_AVG_16_CONV;
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break;
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case 5:
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avg_sel = ADC_SAR_IP_AVG_32_CONV;
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break;
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default:
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LOG_ERR("Unsupported oversampling value");
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return -ENOTSUP;
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}
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Adc_Sar_Ip_SetAveraging(config->instance, avg_en, avg_sel);
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return 0;
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}
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#endif
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#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
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static int adc_nxp_s32_set_resolution(const struct device *dev, uint8_t adc_resol)
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{
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const struct adc_nxp_s32_config *config = dev->config;
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Adc_Sar_Ip_Resolution resolution;
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switch (adc_resol) {
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case 8:
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resolution = ADC_SAR_IP_RESOLUTION_8;
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break;
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case 10:
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resolution = ADC_SAR_IP_RESOLUTION_10;
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break;
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case 12:
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resolution = ADC_SAR_IP_RESOLUTION_12;
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break;
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case 14:
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resolution = ADC_SAR_IP_RESOLUTION_14;
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break;
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default:
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LOG_ERR("Unsupported resolution");
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return -ENOTSUP;
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}
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Adc_Sar_Ip_SetResolution(config->instance, resolution);
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return 0;
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}
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#endif
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static int adc_nxp_s32_start_read_async(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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const struct adc_nxp_s32_config *config = dev->config;
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struct adc_nxp_s32_data *data = dev->data;
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int error;
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uint32_t mask;
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uint8_t channel;
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if (find_msb_set(sequence->channels) > data->num_channels) {
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LOG_ERR("Channels out of bit map");
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return -EINVAL;
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}
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error = adc_nxp_s32_validate_buffer_size(dev, sequence);
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if (error) {
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LOG_ERR("Buffer size isn't enough");
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return -EINVAL;
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}
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#if FEATURE_ADC_HAS_AVERAGING
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error = adc_nxp_s32_set_averaging(dev, sequence->oversampling);
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if (error) {
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return -ENOTSUP;
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}
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#else
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if (sequence->oversampling) {
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LOG_ERR("Oversampling can't be changed");
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return -ENOTSUP;
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}
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#endif
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#if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
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error = adc_nxp_s32_set_resolution(dev, sequence->resolution);
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if (error) {
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return -ENOTSUP;
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}
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#else
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if (sequence->resolution != ADC_SAR_IP_MAX_RESOLUTION) {
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LOG_ERR("Resolution can't be changed");
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return -ENOTSUP;
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}
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#endif
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if (sequence->calibrate) {
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#if FEATURE_ADC_HAS_CALIBRATION
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error = Adc_Sar_Ip_DoCalibration(config->instance);
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if (error) {
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LOG_ERR("Error during calibration");
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return -EIO;
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}
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#else
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LOG_ERR("Unsupported calibration");
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return -ENOTSUP;
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#endif
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}
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for (int i = 0; i < data->num_channels; i++) {
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mask = (sequence->channels >> i) & 0x1;
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channel = ADC_NXP_S32_GROUPCHAN_2_PHYCHAN(config->group_channel, i);
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if (mask) {
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Adc_Sar_Ip_EnableChannelNotifications(config->instance,
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channel, ADC_SAR_IP_CHAN_NOTIF_EOC);
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Adc_Sar_Ip_EnableChannel(config->instance,
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ADC_SAR_IP_CONV_CHAIN_NORMAL, channel);
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} else {
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Adc_Sar_Ip_DisableChannelNotifications(config->instance,
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channel, ADC_SAR_IP_CHAN_NOTIF_EOC);
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Adc_Sar_Ip_DisableChannel(config->instance,
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ADC_SAR_IP_CONV_CHAIN_NORMAL, channel);
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}
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}
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/* Save ADC sequence sampling buffer and its end pointer address */
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data->buffer = sequence->buffer;
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if (config->callback_select) {
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data->buf_end = data->buffer + sequence->buffer_size / sizeof(uint16_t);
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}
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_nxp_s32_data *data = CONTAINER_OF(ctx, struct adc_nxp_s32_data, ctx);
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const struct adc_nxp_s32_config *config = data->dev->config;
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data->mask_channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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Adc_Sar_Ip_StartConversion(config->instance, ADC_SAR_IP_CONV_CHAIN_NORMAL);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_nxp_s32_data *const data =
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CONTAINER_OF(ctx, struct adc_nxp_s32_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int adc_nxp_s32_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_nxp_s32_data *data = dev->data;
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int error = 0;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = adc_nxp_s32_start_read_async(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int adc_nxp_s32_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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return adc_nxp_s32_read_async(dev, sequence, NULL);
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}
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static void adc_nxp_s32_isr(const struct device *dev)
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{
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const struct adc_nxp_s32_config *config = dev->config;
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Adc_Sar_Ip_IRQHandler(config->instance);
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}
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#define ADC_NXP_S32_DRIVER_API(n) \
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static const struct adc_driver_api adc_nxp_s32_driver_api_##n = { \
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.channel_setup = adc_nxp_s32_channel_setup, \
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.read = adc_nxp_s32_read, \
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IF_ENABLED(CONFIG_ADC_ASYNC, (.read_async = adc_nxp_s32_read_async,))\
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.ref_internal = DT_INST_PROP(n, vref_mv), \
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};
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#define ADC_NXP_S32_IRQ_CONFIG(n) \
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static void adc_nxp_s32_adc_sar_config_func_##n(const struct device *dev)\
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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adc_nxp_s32_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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};
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#define ADC_NXP_S32_CALLBACK_DEFINE(n) \
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void adc_nxp_s32_normal_end_conversion_callback##n(const uint16 PhysicalChanId)\
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{ \
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const struct device *dev = DEVICE_DT_INST_GET(n); \
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const struct adc_nxp_s32_config *config = dev->config; \
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struct adc_nxp_s32_data *data = dev->data; \
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uint16_t result = 0; \
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\
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result = Adc_Sar_Ip_GetConvData(n, PhysicalChanId); \
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LOG_DBG("End conversion, channel %d, group %d, result = %d", \
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ADC_SAR_IP_CHAN_2_BIT(PhysicalChanId), \
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config->group_channel, result); \
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\
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*data->buffer++ = result; \
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data->mask_channels &= \
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~BIT(ADC_SAR_IP_CHAN_2_BIT(PhysicalChanId)); \
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\
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if (!data->mask_channels) { \
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adc_context_on_sampling_done(&data->ctx, \
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(struct device *)dev); \
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} \
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}; \
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void adc_nxp_s32_normal_endchain_callback##n(void) \
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{ \
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const struct device *dev = DEVICE_DT_INST_GET(n); \
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const struct adc_nxp_s32_config *config = dev->config; \
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struct adc_nxp_s32_data *data = dev->data; \
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uint16_t result = 0; \
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uint8_t channel; \
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\
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while (data->mask_channels) { \
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channel = ADC_NXP_S32_GROUPCHAN_2_PHYCHAN( \
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config->group_channel, \
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(find_lsb_set(data->mask_channels)-1)); \
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result = Adc_Sar_Ip_GetConvData(n, channel); \
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LOG_DBG("End chain, channel %d, group %d, result = %d", \
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ADC_SAR_IP_CHAN_2_BIT(channel), \
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config->group_channel, result); \
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if (data->buffer < data->buf_end) { \
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*data->buffer++ = result; \
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} \
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data->mask_channels &= \
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~BIT(ADC_SAR_IP_CHAN_2_BIT(channel)); \
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} \
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\
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adc_context_on_sampling_done(&data->ctx, (struct device *)dev); \
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};
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#define ADC_NXP_S32_INSTANCE_CHECK(indx, n) \
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((DT_INST_REG_ADDR(n) == IP_ADC_##indx##_BASE) ? indx : 0)
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#define ADC_NXP_S32_GET_INSTANCE(n) \
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LISTIFY(__DEBRACKET ADC_INSTANCE_COUNT, ADC_NXP_S32_INSTANCE_CHECK, (|), n)
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#define ADC_NXP_S32_INIT_DEVICE(n) \
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ADC_NXP_S32_DRIVER_API(n) \
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ADC_NXP_S32_CALLBACK_DEFINE(n) \
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ADC_NXP_S32_IRQ_CONFIG(n) \
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COND_CODE_1(DT_INST_NUM_PINCTRL_STATES(n), \
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(PINCTRL_DT_INST_DEFINE(n);), (EMPTY)) \
|
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static const Adc_Sar_Ip_ConfigType adc_nxp_s32_default_config##n = \
|
||||
{ \
|
||||
.ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT, \
|
||||
.AdcResolution = ADC_SAR_IP_RESOLUTION_14, \
|
||||
.HighSpeedConvEn = DT_INST_PROP(n, high_speed), \
|
||||
.EndOfNormalChainNotification = \
|
||||
adc_nxp_s32_normal_endchain_callback##n, \
|
||||
.EndOfConvNotification = \
|
||||
adc_nxp_s32_normal_end_conversion_callback##n, \
|
||||
}; \
|
||||
static struct adc_nxp_s32_data adc_nxp_s32_data_##n = { \
|
||||
ADC_CONTEXT_INIT_TIMER(adc_nxp_s32_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_LOCK(adc_nxp_s32_data_##n, ctx), \
|
||||
ADC_CONTEXT_INIT_SYNC(adc_nxp_s32_data_##n, ctx), \
|
||||
}; \
|
||||
static const struct adc_nxp_s32_config adc_nxp_s32_config_##n = { \
|
||||
.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
|
||||
.instance = ADC_NXP_S32_GET_INSTANCE(n), \
|
||||
.group_channel = DT_INST_ENUM_IDX(n, group_channel), \
|
||||
.callback_select = DT_INST_ENUM_IDX(n, callback_select), \
|
||||
.adc_cfg = (Adc_Sar_Ip_ConfigType *)&adc_nxp_s32_default_config##n,\
|
||||
.irq_config_func = adc_nxp_s32_adc_sar_config_func_##n, \
|
||||
.pin_cfg = COND_CODE_1(DT_INST_NUM_PINCTRL_STATES(n), \
|
||||
(PINCTRL_DT_INST_DEV_CONFIG_GET(n)), (NULL)), \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(n, \
|
||||
&adc_nxp_s32_init, \
|
||||
NULL, \
|
||||
&adc_nxp_s32_data_##n, \
|
||||
&adc_nxp_s32_config_##n, \
|
||||
POST_KERNEL, \
|
||||
CONFIG_ADC_INIT_PRIORITY, \
|
||||
&adc_nxp_s32_driver_api_##n);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(ADC_NXP_S32_INIT_DEVICE)
|
||||
49
dts/bindings/adc/nxp,s32-adc-sar.yaml
Normal file
49
dts/bindings/adc/nxp,s32-adc-sar.yaml
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
# Copyright 2023 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP S32 ADC SAR controller
|
||||
|
||||
compatible: "nxp,s32-adc-sar"
|
||||
|
||||
include: [adc-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
vref-mv:
|
||||
type: int
|
||||
default: 3300
|
||||
description: Indicates the reference voltage of the ADC in mV.
|
||||
|
||||
group-channel:
|
||||
type: string
|
||||
required: true
|
||||
enum:
|
||||
- "precision"
|
||||
- "standard"
|
||||
- "external"
|
||||
description: The ADC group channel.
|
||||
|
||||
high-speed:
|
||||
type: boolean
|
||||
description: Use high speed during conversion, calibration.
|
||||
|
||||
callback-select:
|
||||
type: string
|
||||
default: "normal-end-conversion"
|
||||
enum:
|
||||
- "normal-end-conversion"
|
||||
- "normal-end-chain"
|
||||
description: |
|
||||
Select normal end conversion callback to reduce interrupt handling time.
|
||||
Select normal end chain callback to reduce the number of interrupt occurrences.
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
Loading…
Reference in a new issue