diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 80249670d0..60d33b1807 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -174,11 +174,6 @@ config RISCV_GENERIC_TOOLCHAIN Allow SOCs that have custom extended riscv ISA to still compile with generic riscv32 toolchain. -config RISCV_HAS_CPU_IDLE - bool "Does SOC has CPU IDLE instruction" - help - Does SOC has CPU IDLE instruction - config GEN_ISR_TABLES default y diff --git a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series index 7bd679e5f4..699e54e66b 100644 --- a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series +++ b/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series @@ -24,9 +24,6 @@ config RISCV_GENERIC_TOOLCHAIN config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/efinix_sapphire/Kconfig.defconfig b/soc/riscv/efinix_sapphire/Kconfig.defconfig index 7018c0f11f..08e2c851a2 100644 --- a/soc/riscv/efinix_sapphire/Kconfig.defconfig +++ b/soc/riscv/efinix_sapphire/Kconfig.defconfig @@ -9,10 +9,6 @@ config SOC config SYS_CLOCK_HW_CYCLES_PER_SEC default 100000000 -config RISCV_HAS_CPU_IDLE - bool - default y - config RISCV_SOC_INTERRUPT_INIT bool default y diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 index 1e93f2703b..4d65e4c43c 100644 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 +++ b/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 @@ -20,9 +20,6 @@ config RISCV_SOC_MCAUSE_EXCEPTION_MASK config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_GP default y diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series b/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series index 8e8ea25520..15e98314c8 100644 --- a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series +++ b/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config NUM_IRQS # Platform interrupts IRQs index start from index 16 default 32 -config RISCV_HAS_CPU_IDLE - default y - config RISCV_GP default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series index 7c5bc0ee89..0ed7358b63 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series +++ b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series @@ -22,9 +22,6 @@ config UART_NS16550_WA_ISR_REENABLE_INTERRUPT default y depends on UART_NS16550 -config RISCV_HAS_CPU_IDLE - default y - config FLASH_INIT_PRIORITY default 0 diff --git a/soc/riscv/litex_vexriscv/Kconfig.defconfig b/soc/riscv/litex_vexriscv/Kconfig.defconfig index 3efdf200ee..f3e4c7cc79 100644 --- a/soc/riscv/litex_vexriscv/Kconfig.defconfig +++ b/soc/riscv/litex_vexriscv/Kconfig.defconfig @@ -9,9 +9,6 @@ config SOC config SYS_CLOCK_HW_CYCLES_PER_SEC default 100000000 -config RISCV_HAS_CPU_IDLE - bool - config RISCV_HAS_PLIC bool diff --git a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series b/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series index ef161321a5..fc5aaa7c18 100644 --- a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series +++ b/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series @@ -11,9 +11,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series b/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series index e5c3a2ebce..4399972dd9 100644 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series +++ b/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series @@ -14,9 +14,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/neorv32/Kconfig.defconfig b/soc/riscv/neorv32/Kconfig.defconfig index 86aed551f5..bc37ea7472 100644 --- a/soc/riscv/neorv32/Kconfig.defconfig +++ b/soc/riscv/neorv32/Kconfig.defconfig @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config NUM_IRQS default 32 -config RISCV_HAS_CPU_IDLE - default y - config RISCV_GP default y diff --git a/soc/riscv/opentitan/Kconfig.defconfig b/soc/riscv/opentitan/Kconfig.defconfig index cc27b7ffd6..4ec6bffc4e 100644 --- a/soc/riscv/opentitan/Kconfig.defconfig +++ b/soc/riscv/opentitan/Kconfig.defconfig @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/renode_virt/Kconfig.defconfig b/soc/riscv/renode_virt/Kconfig.defconfig index 89e226edbb..5d2cd649b0 100644 --- a/soc/riscv/renode_virt/Kconfig.defconfig +++ b/soc/riscv/renode_virt/Kconfig.defconfig @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series index b2f16e5261..661fe4ba1e 100644 --- a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series +++ b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series index d6b9467868..3db750cb1a 100644 --- a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series +++ b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series index 347ac14b55..83165d5887 100644 --- a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series +++ b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series index 77436b593e..2dc45e1f34 100644 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series +++ b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series index 23a78c9f0d..5b62959858 100644 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series +++ b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series @@ -15,10 +15,6 @@ config RISCV_SOC_INTERRUPT_INIT bool default y -config RISCV_HAS_CPU_IDLE - bool - default y - config RISCV_HAS_PLIC bool default y diff --git a/soc/riscv/virt/Kconfig.defconfig b/soc/riscv/virt/Kconfig.defconfig index 9773586e92..e0982bc185 100644 --- a/soc/riscv/virt/Kconfig.defconfig +++ b/soc/riscv/virt/Kconfig.defconfig @@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config RISCV_SOC_INTERRUPT_INIT default y -config RISCV_HAS_CPU_IDLE - default y - config RISCV_HAS_PLIC default y diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c index 2e3ad1a36c..a138e01228 100644 --- a/tests/kernel/context/src/main.c +++ b/tests/kernel/context/src/main.c @@ -72,11 +72,10 @@ extern const int32_t z_sys_timer_irq_for_test; #endif -/* Cortex-M1, Nios II, and RISCV without CONFIG_RISCV_HAS_CPU_IDLE - * do have a power saving instruction, so k_cpu_idle() returns immediately +/* Cortex-M1 and Nios II do have a power saving instruction, so k_cpu_idle() + * returns immediately */ -#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2) && \ - (!defined(CONFIG_RISCV) || defined(CONFIG_RISCV_HAS_CPU_IDLE)) +#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2) #define HAS_POWERSAVE_INSTRUCTION #endif