drivers: pinctrl: Microchip XEC PINCTRL glitch fix
Glitches were observed if a GPIO pin was configured by ROM to a non-default state and then Zephyr PINCTRL reconfigured the pin. The fix involves using the correct PINCTRL YAML output enable and state flags. Reading the current spin state and reflecting into new pin configuration if the pin is output and the drive low/high properties are not present. We also take advantage of GPIO hardware reflecing the alternate output value in the parallel output bit before enabling parallel output mode. Interpret boolean flags with both enable and disable as do not touch if neither flag is present. We give precedence to enable over disable if both flags mistakenly appear. Note, PINCTRL always clears the GPIO control input pad disable bit. Signed-off-by: Manimaran A <manimaran.a@microchip.com>
This commit is contained in:
Manimaran A
Christopher Friedt
parent
79ee5a876f
commit
f8c8ee65be
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@ -148,11 +148,13 @@
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&i2c00_scl_gpio004 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c00_sda_gpio003 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -181,11 +183,13 @@
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&i2c01_scl_gpio131 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c01_sda_gpio130 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -198,11 +202,13 @@
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&i2c07_scl_gpio013 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c07_sda_gpio012 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -158,11 +158,13 @@
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&i2c00_scl_gpio004 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c00_sda_gpio003 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -175,11 +177,13 @@
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&i2c01_scl_gpio131 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c01_sda_gpio130 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -192,11 +196,13 @@
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&i2c07_scl_gpio013 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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&i2c07_sda_gpio012 {
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drive-open-drain;
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output-enable;
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output-high;
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};
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@ -12,56 +12,88 @@
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* Microchip XEC: each GPIO pin has two 32-bit control register.
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/*
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* Microchip XEC: each GPIO pin has two 32-bit control register.
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* The first 32-bit register contains all pin features except
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* slew rate and driver strength in the second control register.
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* We compute the register index from the beginning of the GPIO
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* control address space which is the same range of the PINCTRL
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* parent node.
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* parent node. A zero value in the PINCTRL pinmux field means
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* do not touch.
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*/
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static void config_drive_slew(struct gpio_regs * const regs, uint32_t idx, uint32_t conf)
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{
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uint32_t slew = conf & (MCHP_XEC_OSPEEDR_MASK << MCHP_XEC_OSPEEDR_POS);
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uint32_t drvstr = conf & (MCHP_XEC_ODRVSTR_MASK << MCHP_XEC_ODRVSTR_POS);
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uint32_t val = 0;
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uint32_t mask = 0;
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uint32_t slew = (conf >> MCHP_XEC_SLEW_RATE_POS) & MCHP_XEC_SLEW_RATE_MSK0;
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uint32_t drvstr = (conf >> MCHP_XEC_DRV_STR_POS) & MCHP_XEC_DRV_STR_MSK0;
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uint32_t msk = 0, val = 0;
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if (slew != MCHP_XEC_OSPEEDR_NO_CHG) {
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mask |= MCHP_GPIO_CTRL2_SLEW_MASK;
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if (slew == MCHP_XEC_OSPEEDR_FAST) {
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if (slew) {
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msk |= MCHP_GPIO_CTRL2_SLEW_MASK;
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/* slow slew value is 0 */
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if (slew == MCHP_XEC_SLEW_RATE_FAST0) {
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val |= MCHP_GPIO_CTRL2_SLEW_FAST;
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}
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}
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if (drvstr != MCHP_XEC_ODRVSTR_NO_CHG) {
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mask |= MCHP_GPIO_CTRL2_DRV_STR_MASK;
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val |= (drvstr << MCHP_GPIO_CTRL2_DRV_STR_POS);
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if (drvstr) {
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msk |= MCHP_GPIO_CTRL2_DRV_STR_MASK;
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/* drive strength values are 0 based */
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val |= ((drvstr - 1u) << MCHP_GPIO_CTRL2_DRV_STR_POS);
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}
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if (!mask) {
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if (!msk) {
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return;
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}
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regs->CTRL2[idx] = (regs->CTRL2[idx] & ~mask) | (val & mask);
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regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk);
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}
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/* Configure pin by writing GPIO Control and Control2 registers.
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* NOTE: Disable alternate output feature since the GPIO driver does.
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* While alternate output is enabled (default state of pin) HW does not
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* ignores writes to the parallel output bit for the pin. To set parallel
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* output value we must keep pin direction as input, set alternate output
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* disable, program pin value to parallel output bit, and then disable
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* alternate output mode.
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/*
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* Internal pulls feature:
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* None, weak pull-up, weak pull-down, or repeater mode (both pulls enabled).
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* We do not touch this field unless one or more of the DT booleans are set.
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* If the no-bias boolean is set then disable internal pulls.
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* If pull up and/or down is set enable the respective pull or both for what
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* MCHP calls repeater(keeper) mode.
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*/
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static uint32_t prog_pud(uint32_t pcr1, uint32_t conf)
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{
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if (conf & BIT(MCHP_XEC_NO_PUD_POS)) {
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pcr1 &= ~(MCHP_GPIO_CTRL_PUD_MASK);
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pcr1 |= MCHP_GPIO_CTRL_PUD_NONE;
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return pcr1;
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}
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if (conf & (BIT(MCHP_XEC_PU_POS) | BIT(MCHP_XEC_PD_POS))) {
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pcr1 &= ~(MCHP_GPIO_CTRL_PUD_MASK);
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if (conf & BIT(MCHP_XEC_PU_POS)) {
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pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
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}
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if (conf & BIT(MCHP_XEC_PD_POS)) {
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pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
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}
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}
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return pcr1;
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}
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/*
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* DT enable booleans take precedence over disable booleans.
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* We initially clear alternate output disable allowing us to set output state
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* in the control register. Hardware sets output state bit in both control and
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* parallel output register bits. Alternate output disable only controls which
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* register bit is writable by the EC. We also clear the input pad disable
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* bit because we need the input pin state and we don't know if the requested
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* alternate function is input or bi-directional.
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* Note 1: hardware allows input and output to be simultaneously enabled.
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* Note 2: hardware interrupt detection is only on the input path.
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*/
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static int xec_config_pin(uint32_t portpin, uint32_t conf, uint32_t altf)
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{
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struct gpio_regs * const regs = (struct gpio_regs * const)DT_INST_REG_ADDR(0);
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uint32_t port = MCHP_XEC_PINMUX_PORT(portpin);
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uint32_t pin = (uint32_t)MCHP_XEC_PINMUX_PIN(portpin);
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uint32_t msk = MCHP_GPIO_CTRL_AOD_MASK;
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uint32_t val = MCHP_GPIO_CTRL_AOD_DIS;
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uint32_t idx = 0u;
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uint32_t temp = 0u;
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uint32_t idx = 0u, pcr1 = 0u;
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if (port >= NUM_MCHP_GPIO_PORTS) {
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return -EINVAL;
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@ -72,57 +104,61 @@ static int xec_config_pin(uint32_t portpin, uint32_t conf, uint32_t altf)
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config_drive_slew(regs, idx, conf);
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/* default input pad enabled, buffer type push-pull, no internal pulls,
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* and invert polarity normal.
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*/
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msk |= (BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) | MCHP_GPIO_CTRL_BUFT_MASK |
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MCHP_GPIO_CTRL_PUD_MASK | MCHP_GPIO_CTRL_MUX_MASK
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| BIT(MCHP_GPIO_CTRL_POL_POS));
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/* Clear alternate output disable and input pad disable */
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regs->CTRL[idx] &= ~(BIT(MCHP_GPIO_CTRL_AOD_POS) | BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS));
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pcr1 = regs->CTRL[idx]; /* current configuration including pin input state */
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pcr1 = regs->CTRL[idx]; /* read multiple times to allow propagation from pad */
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pcr1 = regs->CTRL[idx]; /* Is this necessary? */
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pcr1 = prog_pud(pcr1, conf);
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/* Touch output enable. We always enable input */
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if (conf & BIT(MCHP_XEC_OUT_DIS_POS)) {
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pcr1 &= ~(MCHP_GPIO_CTRL_DIR_OUTPUT);
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}
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if (conf & BIT(MCHP_XEC_OUT_EN_POS)) {
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pcr1 |= MCHP_GPIO_CTRL_DIR_OUTPUT;
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}
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/* Touch output state? Bit can be set even if the direction is input only */
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if (conf & BIT(MCHP_XEC_OUT_LO_POS)) {
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pcr1 &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
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}
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if (conf & BIT(MCHP_XEC_OUT_HI_POS)) {
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pcr1 |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
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}
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/* Touch output buffer type? */
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if (conf & BIT(MCHP_XEC_PUSH_PULL_POS)) {
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pcr1 &= ~(MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
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}
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if (conf & BIT(MCHP_XEC_OPEN_DRAIN_POS)) {
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pcr1 |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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}
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/* Always touch power gate */
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pcr1 &= ~MCHP_GPIO_CTRL_PWRG_MASK;
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if (conf & BIT(MCHP_XEC_PIN_LOW_POWER_POS)) {
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msk |= MCHP_GPIO_CTRL_PWRG_MASK;
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val |= MCHP_GPIO_CTRL_PWRG_OFF;
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pcr1 |= MCHP_GPIO_CTRL_PWRG_OFF;
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} else {
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pcr1 |= MCHP_GPIO_CTRL_PWRG_VTR_IO;
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}
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temp = (conf & MCHP_XEC_PUPDR_MASK) >> MCHP_XEC_PUPDR_POS;
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switch (temp) {
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case MCHP_XEC_PULL_UP:
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val |= MCHP_GPIO_CTRL_PUD_PU;
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break;
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case MCHP_XEC_PULL_DOWN:
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val |= MCHP_GPIO_CTRL_PUD_PD;
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break;
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case MCHP_XEC_REPEATER:
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val |= MCHP_GPIO_CTRL_PUD_RPT;
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break;
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default:
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val |= MCHP_GPIO_CTRL_PUD_NONE;
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break;
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/* Always touch MUX (alternate function) */
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pcr1 &= ~MCHP_GPIO_CTRL_MUX_MASK;
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pcr1 |= (uint32_t)((altf & MCHP_GPIO_CTRL_MUX_MASK0) << MCHP_GPIO_CTRL_MUX_POS);
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/* Always touch invert of alternate function. Need another bit to avoid touching */
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if (conf & BIT(MCHP_XEC_FUNC_INV_POS)) {
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pcr1 |= BIT(MCHP_GPIO_CTRL_POL_POS);
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} else {
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pcr1 &= ~BIT(MCHP_GPIO_CTRL_POL_POS);
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}
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if ((conf >> MCHP_XEC_OTYPER_POS) & MCHP_XEC_OTYPER_MASK) {
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val |= MCHP_GPIO_CTRL_BUFT_OPENDRAIN;
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}
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if (conf & MCHP_XEC_FUNC_INV_MSK) {
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val |= BIT(MCHP_GPIO_CTRL_POL_POS);
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}
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regs->CTRL[idx] = (regs->CTRL[idx] & ~msk) | val;
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temp = (conf >> MCHP_XEC_OVAL_POS) & MCHP_XEC_OVAL_MASK;
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if (temp) {
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if (temp == MCHP_XEC_OVAL_DRV_HIGH) {
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regs->PAROUT[port] |= BIT(pin);
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} else {
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regs->PAROUT[port] &= ~BIT(pin);
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}
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regs->CTRL[idx] |= MCHP_GPIO_CTRL_DIR_OUTPUT;
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}
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val = (uint32_t)((altf & MCHP_GPIO_CTRL_MUX_MASK0) << MCHP_GPIO_CTRL_MUX_POS);
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regs->CTRL[idx] |= val;
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/* output state set in control & parallel regs */
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regs->CTRL[idx] = pcr1;
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/* make output state in control read-only in control and read-write in parallel reg */
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regs->CTRL[idx] = pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS);
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return 0;
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}
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@ -130,23 +166,22 @@ static int xec_config_pin(uint32_t portpin, uint32_t conf, uint32_t altf)
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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uint32_t portpin, mux, cfg, func;
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uint32_t portpin, pinmux, func;
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int ret;
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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mux = pins[i].pinmux;
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pinmux = pins[i];
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func = MCHP_XEC_PINMUX_FUNC(mux);
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func = MCHP_XEC_PINMUX_FUNC(pinmux);
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if (func >= MCHP_AFMAX) {
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return -EINVAL;
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}
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cfg = pins[i].pincfg;
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portpin = MEC_XEC_PINMUX_PORT_PIN(mux);
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portpin = MEC_XEC_PINMUX_PORT_PIN(pinmux);
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ret = xec_config_pin(portpin, cfg, func);
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ret = xec_config_pin(portpin, pinmux, func);
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if (ret < 0) {
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return ret;
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}
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@ -83,6 +83,8 @@ child-binding:
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- drive-push-pull
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- drive-open-drain
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- low-power-enable
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- output-disable
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- output-enable
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- output-high
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- output-low
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@ -94,8 +96,9 @@ child-binding:
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slew-rate:
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type: string
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default: "low-speed"
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default: "no-change"
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enum:
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- "no-change"
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- "low-speed"
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- "high-speed"
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description: |
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@ -106,8 +109,9 @@ child-binding:
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drive-strength:
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type: string
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default: "1x"
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default: "no-change"
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enum:
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- "no-change"
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- "1x"
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- "2x"
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- "4x"
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@ -20,32 +20,28 @@
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#define MCHP_AF7 0x7
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#define MCHP_AFMAX 0x8
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#define MCHP_XEC_PUPDR_POS 0
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#define MCHP_XEC_PUPDR_MASK 0x3
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#define MCHP_XEC_FUNC_INV_POS 2
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#define MCHP_XEC_FUNC_INV_MSK 0x4
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#define MCHP_XEC_OTYPER_POS 4
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#define MCHP_XEC_OTYPER_MASK 0x1
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#define MCHP_XEC_OTYPER_PUSHPULL 0
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#define MCHP_XEC_OTYPER_OPENDRAIN 0x1
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#define MCHP_XEC_OVAL_POS 6
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#define MCHP_XEC_OVAL_MASK 0x3
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#define MCHP_XEC_OVAL_DRV_LOW 0x1
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#define MCHP_XEC_OVAL_DRV_HIGH 0x2
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#define MCHP_XEC_OSPEEDR_POS 8
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#define MCHP_XEC_OSPEEDR_MASK 0x3
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#define MCHP_XEC_OSPEEDR_SLOW 0x0
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#define MCHP_XEC_OSPEEDR_FAST 0x1
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#define MCHP_XEC_OSPEEDR_NO_CHG 0x3 /* Do not modify slew rate */
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#define MCHP_XEC_ODRVSTR_POS 12
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#define MCHP_XEC_ODRVSTR_MASK 0x7
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#define MCHP_XEC_ODRVSTR_1X 0x0 /* 2 or 4(PIO-24) mA */
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#define MCHP_XEC_ODRVSTR_2X 0x1 /* 4 or 8(PIO-24) mA */
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#define MCHP_XEC_ODRVSTR_4X 0x2 /* 8 or 16(PIO-24) mA */
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#define MCHP_XEC_ODRVSTR_6X 0x3 /* 12 or 24(PIO-24) mA */
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#define MCHP_XEC_ODRVSTR_NO_CHG 0x7 /* Do not modify drive strength */
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#define MCHP_XEC_PIN_LOW_POWER_POS 15
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#define MCHP_XEC_PIN_LOW_POWER 1
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#define MCHP_XEC_NO_PUD_POS 12
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#define MCHP_XEC_PD_POS 13
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#define MCHP_XEC_PU_POS 14
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#define MCHP_XEC_PUSH_PULL_POS 15
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#define MCHP_XEC_OPEN_DRAIN_POS 16
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#define MCHP_XEC_OUT_DIS_POS 17
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#define MCHP_XEC_OUT_EN_POS 18
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#define MCHP_XEC_OUT_HI_POS 19
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#define MCHP_XEC_OUT_LO_POS 20
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/* bit[21] unused */
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#define MCHP_XEC_SLEW_RATE_POS 22
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#define MCHP_XEC_SLEW_RATE_MSK0 0x3
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#define MCHP_XEC_SLEW_RATE_SLOW0 0x1
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#define MCHP_XEC_SLEW_RATE_FAST0 0x2
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#define MCHP_XEC_DRV_STR_POS 24
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#define MCHP_XEC_DRV_STR_MSK0 0x7
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#define MCHP_XEC_DRV_STR0_1X 0x1 /* 2 or 4(PIO-24) mA */
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#define MCHP_XEC_DRV_STR0_2X 0x2 /* 4 or 8(PIO-24) mA */
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#define MCHP_XEC_DRV_STR0_4X 0x3 /* 8 or 16(PIO-24) mA */
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#define MCHP_XEC_DRV_STR0_6X 0x4 /* 12 or 24(PIO-24) mA */
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#define MCHP_XEC_PIN_LOW_POWER_POS 27
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#define MCHP_XEC_FUNC_INV_POS 29
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#define MCHP_XEC_PINMUX_PORT_POS 0
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#define MCHP_XEC_PINMUX_PORT_MSK 0xf
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|
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|
|
@ -26,71 +26,30 @@ extern "C" {
|
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/** @cond INTERNAL_HIDDEN */
|
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|
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/* Type for MCHP XEC pin. */
|
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typedef struct {
|
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/** Pinmux settings (port, pin and function). */
|
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uint16_t pinmux;
|
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/** Pin configuration (bias, drive and slew rate). */
|
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uint16_t pincfg;
|
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} pinctrl_soc_pin_t;
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typedef uint32_t pinctrl_soc_pin_t;
|
||||
|
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/* initialize pinmux member fields of pinctrl_pin_t */
|
||||
#define Z_PINCTRL_MCHP_XEC_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
|
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#define Z_PINCTRL_MCHP_XEC_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux))
|
||||
|
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#define MCHP_XEC_BIAS_DIS_VAL(nid) \
|
||||
(MCHP_XEC_NO_PULL * DT_PROP(nid, bias_disable))
|
||||
|
||||
#define MCHP_XEC_BIAS_PU_VAL(nid) \
|
||||
(MCHP_XEC_PULL_UP * DT_PROP(nid, bias_pull_up))
|
||||
|
||||
#define MCHP_XEC_BIAS_PD_VAL(nid) \
|
||||
(MCHP_XEC_PULL_DOWN * DT_PROP(nid, bias_pull_down))
|
||||
|
||||
#define MCHP_XEC_DRV_PP_VAL(nid) \
|
||||
(MCHP_XEC_PUSH_PULL * DT_PROP(nid, drive_push_pull))
|
||||
|
||||
#define MCHP_XEC_DRV_OD_VAL(nid) \
|
||||
(MCHP_XEC_OPEN_DRAIN * DT_PROP(nid, drive_open_drain))
|
||||
|
||||
#define MCHP_XEC_OVAL_DRV_LO(nid) \
|
||||
(MCHP_XEC_OVAL_LOW * DT_PROP(nid, output_low))
|
||||
|
||||
#define MCHP_XEC_OVAL_DRV_HI(nid) \
|
||||
(MCHP_XEC_OVAL_HIGH * DT_PROP(nid, output_high))
|
||||
|
||||
#define MCHP_XEC_LOW_POWER_EN(nid) \
|
||||
(MCHP_XEC_PIN_LOW_POWER * DT_PROP(nid, low_power_enable))
|
||||
|
||||
#define MCHP_XEC_SLEW_VAL(nid) \
|
||||
(DT_ENUM_IDX_OR(nid, slew_rate, MCHP_XEC_OSPEEDR_NO_CHG) << \
|
||||
MCHP_XEC_OSPEEDR_POS)
|
||||
|
||||
#define MCHP_XEC_DRVSTR_VAL(nid) \
|
||||
(DT_ENUM_IDX_OR(nid, drive_strength, MCHP_XEC_ODRVSTR_NO_CHG) << \
|
||||
MCHP_XEC_ODRVSTR_POS)
|
||||
|
||||
#define MCHP_XEC_FUNC_INVERT_VAL(nid) \
|
||||
(MCHP_XEC_FUNC_INVERT * DT_PROP(nid, microchip_output_func_invert))
|
||||
|
||||
/* initialize pincfg field in structure pinctrl_pin_t */
|
||||
#define Z_PINCTRL_MCHP_XEC_PINCFG_INIT(node_id) \
|
||||
((MCHP_XEC_BIAS_DIS_VAL(node_id) << MCHP_XEC_PUPDR_POS) | \
|
||||
(MCHP_XEC_BIAS_PU_VAL(node_id) << MCHP_XEC_PUPDR_POS) | \
|
||||
(MCHP_XEC_BIAS_PD_VAL(node_id) << MCHP_XEC_PUPDR_POS) | \
|
||||
(MCHP_XEC_DRV_PP_VAL(node_id) << MCHP_XEC_OTYPER_POS) | \
|
||||
(MCHP_XEC_DRV_OD_VAL(node_id) << MCHP_XEC_OTYPER_POS) | \
|
||||
(MCHP_XEC_OVAL_DRV_LO(node_id) << MCHP_XEC_OVAL_POS) | \
|
||||
(MCHP_XEC_OVAL_DRV_HI(node_id) << MCHP_XEC_OVAL_POS) | \
|
||||
(MCHP_XEC_LOW_POWER_EN(node_id) << MCHP_XEC_PIN_LOW_POWER_POS) | \
|
||||
(MCHP_XEC_FUNC_INVERT_VAL(node_id) << MCHP_XEC_FUNC_INV_POS) | \
|
||||
MCHP_XEC_SLEW_VAL(node_id) | \
|
||||
MCHP_XEC_DRVSTR_VAL(node_id))
|
||||
#define Z_PINCTRL_STATE_PINCFG_INIT(node_id) \
|
||||
((DT_PROP(node_id, bias_disable) << MCHP_XEC_NO_PUD_POS) \
|
||||
| (DT_PROP(node_id, bias_pull_down) << MCHP_XEC_PD_POS) \
|
||||
| (DT_PROP(node_id, bias_pull_up) << MCHP_XEC_PU_POS) \
|
||||
| (DT_PROP(node_id, drive_push_pull) << MCHP_XEC_PUSH_PULL_POS) \
|
||||
| (DT_PROP(node_id, drive_open_drain) << MCHP_XEC_OPEN_DRAIN_POS) \
|
||||
| (DT_PROP(node_id, output_disable) << MCHP_XEC_OUT_DIS_POS) \
|
||||
| (DT_PROP(node_id, output_enable) << MCHP_XEC_OUT_EN_POS) \
|
||||
| (DT_PROP(node_id, output_high) << MCHP_XEC_OUT_HI_POS) \
|
||||
| (DT_PROP(node_id, output_low) << MCHP_XEC_OUT_LO_POS) \
|
||||
| (DT_PROP(node_id, low_power_enable) << MCHP_XEC_PIN_LOW_POWER_POS) \
|
||||
| (DT_PROP(node_id, microchip_output_func_invert) << MCHP_XEC_FUNC_INV_POS) \
|
||||
| (DT_ENUM_IDX(node_id, slew_rate) << MCHP_XEC_SLEW_RATE_POS) \
|
||||
| (DT_ENUM_IDX(node_id, drive_strength) << MCHP_XEC_DRV_STR_POS))
|
||||
|
||||
/* initialize pin structure members */
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
|
||||
{ .pinmux = Z_PINCTRL_MCHP_XEC_PINMUX_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, state_prop, idx)), \
|
||||
.pincfg = Z_PINCTRL_MCHP_XEC_PINCFG_INIT( \
|
||||
DT_PROP_BY_IDX(node_id, state_prop, idx)), },
|
||||
(Z_PINCTRL_MCHP_XEC_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)) \
|
||||
| Z_PINCTRL_STATE_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))),
|
||||
|
||||
/* Use DT FOREACH macro to initialize each used pin */
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
|
|
|
|||
|
|
@ -9,21 +9,23 @@
|
|||
|
||||
#include <zephyr/devicetree.h>
|
||||
|
||||
#define MCHP_XEC_NO_PULL 0x0
|
||||
#define MCHP_XEC_PIN_FEAT_EN 0x1
|
||||
#define MCHP_XEC_NO_PULL 0x1
|
||||
#define MCHP_XEC_PULL_UP 0x1
|
||||
#define MCHP_XEC_PULL_DOWN 0x2
|
||||
#define MCHP_XEC_REPEATER 0x3
|
||||
#define MCHP_XEC_PUSH_PULL 0x0
|
||||
#define MCHP_XEC_PULL_DOWN 0x1
|
||||
#define MCHP_XEC_PUSH_PULL 0x1
|
||||
#define MCHP_XEC_OPEN_DRAIN 0x1
|
||||
#define MCHP_XEC_NO_OVAL 0x0
|
||||
#define MCHP_XEC_OVAL_LOW 0x1
|
||||
#define MCHP_XEC_OVAL_HIGH 0x2
|
||||
#define MCHP_XEC_OUT_DIS 0x1
|
||||
#define MCHP_XEC_OUT_EN 0x1
|
||||
#define MCHP_XEC_OUT_DRV_LOW 0x1
|
||||
#define MCHP_XEC_OUT_DRV_HIGH 0x1
|
||||
#define MCHP_XEC_DRVSTR_NONE 0x0
|
||||
#define MCHP_XEC_DRVSTR_2MA 0x1
|
||||
#define MCHP_XEC_DRVSTR_4MA 0x2
|
||||
#define MCHP_XEC_DRVSTR_8MA 0x3
|
||||
#define MCHP_XEC_DRVSTR_12MA 0x4
|
||||
#define MCHP_XEC_FUNC_INVERT 0x1
|
||||
#define MCHP_XEC_PIN_INPUT_DIS 0x1
|
||||
|
||||
#define MCHP_DT_ESPI_VW_FLAG_STATUS_POS 0
|
||||
#define MCHP_DT_ESPI_VW_FLAG_DIR_POS 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue