drivers: gpio_dw: update to use new GPIO API
Update driver code and board files to use new GPIO configuration flags such as GPIO_ACTIVE_LOW. Also add implementation of new port_* driver API as well as gpio_pin_interrupt_configure function. The interrupt triggering on both edges is a remnant from the old Quark SE which has a customized DesignWare GPIO block. So remove the support for both edges as the board is no longer supported. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Carles Cufí
parent
5f04861b83
commit
f8f1a91cf7
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@ -30,6 +30,9 @@
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#include <power/power.h>
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#endif
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static int gpio_dw_port_set_bits_raw(struct device *port, u32_t mask);
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static int gpio_dw_port_clear_bits_raw(struct device *port, u32_t mask);
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/*
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* ARC architecture configure IP through IO auxiliary registers.
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* Other architectures as ARM and x86 configure IP through MMIO registers
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@ -113,61 +116,157 @@ static inline void gpio_dw_clock_off(struct device *port)
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#define gpio_dw_clock_off(...)
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#endif
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static inline void dw_set_both_edges(u32_t base_addr, u32_t pin)
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{
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dw_set_bit(base_addr, INT_BOTHEDGE, pin, 1);
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}
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static inline int dw_base_to_block_base(u32_t base_addr)
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{
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return (base_addr & 0xFFFFFFC0);
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}
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static inline int dw_derive_port_from_base(u32_t base_addr)
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{
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u32_t port = (base_addr & 0x3f) / 12U;
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return port;
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}
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static inline int dw_interrupt_support(const struct gpio_dw_config *config)
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{
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return ((int)(config->irq_num) > 0);
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return ((int)(config->irq_num) > 0U);
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}
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static inline void dw_interrupt_config(struct device *port, int access_op,
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u32_t pin, int flags)
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static inline u32_t dw_get_ext_port(u32_t base_addr)
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{
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u32_t ext_port;
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/* 4-port GPIO implementation translates from base address to port */
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switch (dw_derive_port_from_base(base_addr)) {
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case 1:
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ext_port = EXT_PORTB;
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break;
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case 2:
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ext_port = EXT_PORTC;
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break;
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case 3:
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ext_port = EXT_PORTD;
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break;
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case 0:
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default:
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ext_port = EXT_PORTA;
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break;
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}
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return ext_port;
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}
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static inline u32_t dw_get_data_port(u32_t base_addr)
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{
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u32_t dr_port;
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/* 4-port GPIO implementation translates from base address to port */
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switch (dw_derive_port_from_base(base_addr)) {
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case 1:
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dr_port = SWPORTB_DR;
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break;
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case 2:
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dr_port = SWPORTC_DR;
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break;
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case 3:
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dr_port = SWPORTD_DR;
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break;
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case 0:
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default:
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dr_port = SWPORTA_DR;
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break;
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}
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return dr_port;
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}
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static inline u32_t dw_get_dir_port(u32_t base_addr)
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{
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u32_t ddr_port;
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/* 4-port GPIO implementation translates from base address to port */
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switch (dw_derive_port_from_base(base_addr)) {
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case 1:
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ddr_port = SWPORTB_DDR;
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break;
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case 2:
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ddr_port = SWPORTC_DDR;
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break;
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case 3:
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ddr_port = SWPORTD_DDR;
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break;
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case 0:
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default:
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ddr_port = SWPORTA_DDR;
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break;
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}
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return ddr_port;
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}
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static int gpio_dw_pin_interrupt_configure(struct device *port,
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unsigned int pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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const struct gpio_dw_config *config = port->config->config_info;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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bool flag_is_set;
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u32_t port_base_addr = context->base_addr;
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u32_t dir_port = dw_get_dir_port(port_base_addr);
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u32_t data_port = dw_get_data_port(port_base_addr);
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u32_t dir_reg;
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ARG_UNUSED(access_op);
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/* Check for invalid pin number */
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if (pin >= config->bits) {
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return -EINVAL;
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}
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/* set as an input pin */
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dw_set_bit(context->base_addr, SWPORTA_DDR, pin, 0);
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/* Only PORT-A supports interrupts */
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if (data_port != SWPORTA_DR) {
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return -ENOTSUP;
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}
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if (dw_interrupt_support(config)) {
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/* level or edge */
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flag_is_set = (flags & GPIO_INT_EDGE);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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/* Active low/high */
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flag_is_set = (flags & GPIO_INT_ACTIVE_HIGH);
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dw_set_bit(base_addr, INT_POLARITY, pin, flag_is_set);
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/* both edges */
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flag_is_set = (flags & GPIO_INT_DOUBLE_EDGE);
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if (flag_is_set) {
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dw_set_both_edges(base_addr, pin);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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if (mode != GPIO_INT_MODE_DISABLED) {
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/* Check if GPIO port supports interrupts */
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if (!dw_interrupt_support(config)) {
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return -ENOTSUP;
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}
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/* use built-in debounce */
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flag_is_set = (flags & GPIO_INT_DEBOUNCE);
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dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, flag_is_set);
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/* Interrupt to be enabled but pin is not set to input */
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dir_reg = dw_read(port_base_addr, dir_port) & BIT(pin);
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if (dir_reg != 0U) {
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return -EINVAL;
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}
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}
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/* Does not support both edges */
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if ((mode == GPIO_INT_MODE_EDGE) &&
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(trig == GPIO_INT_TRIG_BOTH)) {
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return -ENOTSUP;
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}
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/* Clear interrupt enable */
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dw_set_bit(base_addr, INTEN, pin, false);
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/* Mask and clear interrupt */
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dw_set_bit(base_addr, INTMASK, pin, true);
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dw_write(base_addr, PORTA_EOI, BIT(pin));
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if (mode != GPIO_INT_MODE_DISABLED) {
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/* level (0) or edge (1) */
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin,
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(mode == GPIO_INT_MODE_EDGE));
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/* Active low/high */
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dw_set_bit(base_addr, INT_POLARITY, pin,
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(trig == GPIO_INT_TRIG_HIGH));
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/* Finally enabling interrupt */
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dw_set_bit(base_addr, INTEN, pin, 1);
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dw_set_bit(base_addr, INTEN, pin, true);
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dw_set_bit(base_addr, INTMASK, pin, false);
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}
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return 0;
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}
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static inline void dw_pin_config(struct device *port,
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@ -177,18 +276,28 @@ static inline void dw_pin_config(struct device *port,
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const struct gpio_dw_config *config = port->config->config_info;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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int interrupt_support = dw_interrupt_support(config);
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u32_t dir_port = dw_get_dir_port(port_base_addr);
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bool pin_is_output, need_debounce;
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if (interrupt_support) {
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/* clear interrupt enable */
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dw_set_bit(base_addr, INTEN, pin, 0);
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/* Set init value then direction */
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pin_is_output = (flags & GPIO_OUTPUT) != 0U;
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if (pin_is_output) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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gpio_dw_port_set_bits_raw(port, BIT(pin));
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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gpio_dw_port_clear_bits_raw(port, BIT(pin));
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}
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}
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/* set direction */
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dw_set_bit(port_base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
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dw_set_bit(port_base_addr, dir_port, pin, pin_is_output);
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if (interrupt_support && (flags & GPIO_INT)) {
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dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
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/* Use built-in debounce.
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* Note debounce circuit is only available if also supporting
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* interrupts according to datasheet.
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*/
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if (dw_interrupt_support(config) && (dir_port == SWPORTA_DDR)) {
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need_debounce = (flags & GPIO_INT_DEBOUNCE);
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dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, need_debounce);
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}
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}
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@ -205,15 +314,39 @@ static inline void dw_port_config(struct device *port, int flags)
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static inline int gpio_dw_config(struct device *port, int access_op,
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u32_t pin, int flags)
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{
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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const struct gpio_dw_config *config = port->config->config_info;
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u32_t io_flags;
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/* Check for invalid pin number */
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if (pin >= config->bits) {
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return -EINVAL;
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}
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/* Does not support disconnected pin, and
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* not supporting both input/output at same time.
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*/
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io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
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if ((io_flags == GPIO_DISCONNECTED)
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|| (io_flags == (GPIO_INPUT | GPIO_OUTPUT))) {
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return -ENOTSUP;
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}
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/* No open-drain support */
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if ((flags & GPIO_SINGLE_ENDED) != 0U) {
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return -ENOTSUP;
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}
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/* Does not support pull-up/pull-down */
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0U) {
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return -ENOTSUP;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_pin_config(port, pin, flags);
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} else {
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dw_port_config(port, flags);
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}
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return 0;
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}
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@ -221,12 +354,14 @@ static inline int gpio_dw_write(struct device *port, int access_op,
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u32_t pin, u32_t value)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = context->base_addr;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t data_port = dw_get_data_port(port_base_addr);
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, SWPORTA_DR, pin, value);
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dw_set_bit(base_addr, data_port, pin, value);
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} else {
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dw_write(base_addr, SWPORTA_DR, value);
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dw_write(base_addr, data_port, value);
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}
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return 0;
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@ -236,25 +371,11 @@ static inline int gpio_dw_read(struct device *port, int access_op,
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u32_t pin, u32_t *value)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = context->base_addr;
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u32_t ext_port = EXT_PORTA;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t ext_port = dw_get_ext_port(port_base_addr);
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/* 4-port GPIO implementation translates from base address to port */
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switch (dw_derive_port_from_base(base_addr)) {
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case 1:
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ext_port = EXT_PORTB;
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break;
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case 2:
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ext_port = EXT_PORTC;
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break;
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case 3:
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ext_port = EXT_PORTD;
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break;
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case 0:
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default:
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break;
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}
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*value = dw_read(dw_base_to_block_base(base_addr), ext_port);
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*value = dw_read(base_addr, ext_port);
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if (GPIO_ACCESS_BY_PIN == access_op) {
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*value = !!(*value & BIT(pin));
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@ -262,6 +383,79 @@ static inline int gpio_dw_read(struct device *port, int access_op,
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return 0;
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}
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static int gpio_dw_port_get_raw(struct device *port, u32_t *value)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t ext_port = dw_get_ext_port(port_base_addr);
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*value = dw_read(base_addr, ext_port);
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return 0;
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}
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static int gpio_dw_port_set_masked_raw(struct device *port,
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u32_t mask, u32_t value)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t data_port = dw_get_data_port(port_base_addr);
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u32_t pins;
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pins = dw_read(base_addr, data_port);
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pins = (pins & ~mask) | (mask & value);
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dw_write(base_addr, data_port, pins);
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return 0;
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}
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static int gpio_dw_port_set_bits_raw(struct device *port, u32_t mask)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t data_port = dw_get_data_port(port_base_addr);
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u32_t pins;
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pins = dw_read(base_addr, data_port);
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pins |= mask;
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dw_write(base_addr, data_port, pins);
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return 0;
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}
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static int gpio_dw_port_clear_bits_raw(struct device *port, u32_t mask)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t data_port = dw_get_data_port(port_base_addr);
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u32_t pins;
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pins = dw_read(base_addr, data_port);
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pins &= ~mask;
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dw_write(base_addr, data_port, pins);
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return 0;
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}
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static int gpio_dw_port_toggle_bits(struct device *port, u32_t mask)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t port_base_addr = context->base_addr;
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u32_t data_port = dw_get_data_port(port_base_addr);
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u32_t pins;
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pins = dw_read(base_addr, data_port);
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pins ^= mask;
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dw_write(base_addr, data_port, pins);
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return 0;
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}
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static inline int gpio_dw_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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@ -277,6 +471,11 @@ static inline int gpio_dw_enable_callback(struct device *port, int access_op,
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const struct gpio_dw_config *config = port->config->config_info;
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t data_port = dw_get_data_port(context->base_addr);
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if (data_port != SWPORTA_DR) {
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return -ENOTSUP;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_write(base_addr, PORTA_EOI, BIT(pin));
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@ -295,6 +494,11 @@ static inline int gpio_dw_disable_callback(struct device *port, int access_op,
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const struct gpio_dw_config *config = port->config->config_info;
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struct gpio_dw_runtime *context = port->driver_data;
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u32_t base_addr = dw_base_to_block_base(context->base_addr);
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u32_t data_port = dw_get_data_port(context->base_addr);
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if (data_port != SWPORTA_DR) {
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return -ENOTSUP;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, INTMASK, pin, 1);
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@ -394,6 +598,12 @@ static const struct gpio_driver_api api_funcs = {
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.config = gpio_dw_config,
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.write = gpio_dw_write,
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.read = gpio_dw_read,
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.port_get_raw = gpio_dw_port_get_raw,
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.port_set_masked_raw = gpio_dw_port_set_masked_raw,
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.port_set_bits_raw = gpio_dw_port_set_bits_raw,
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.port_clear_bits_raw = gpio_dw_port_clear_bits_raw,
|
||||
.port_toggle_bits = gpio_dw_port_toggle_bits,
|
||||
.pin_interrupt_configure = gpio_dw_pin_interrupt_configure,
|
||||
.manage_callback = gpio_dw_manage_callback,
|
||||
.enable_callback = gpio_dw_enable_callback,
|
||||
.disable_callback = gpio_dw_disable_callback,
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
#define EXT_PORTC 0x58
|
||||
#define EXT_PORTD 0x5c
|
||||
#define INT_CLOCK_SYNC 0x60 /* alias LS_SYNC */
|
||||
#define INT_BOTHEDGE 0x68
|
||||
#define VER_ID_CODE 0x6c
|
||||
#define CONFIG_REG2 0x70
|
||||
#define CONFIG_REG1 0x74
|
||||
|
|
|
|||
Loading…
Reference in a new issue