pcie: add initial controller support
This adds : - Generic PCIe Controller layer implementing the current PCIe API - Generic PCIe Controller in ECAM mode driver The Generic PCIe Controller layer provides: - Configuration space read/write - single bus endpoint enumerations - Endpoint I/O, MEM & MEM64 BARs allocation - Endpoint I/O, MEM & MEM64 BARs get & translation for drivers The Generic PCIe Controller in ECAM mode driver provides: - Raw DT RANGES properties into usable PCIe regions - Configuration space read/write into ECAM config space - PCIe regions allocation & translation The limitations are: - No support for PCIe prefetchable regions - No support for PCIe bus configuration (only bus0 is supported) - No support for multiple controllers (no domain-id in BDF) Support has been designed to initially support Root Complexes with Root Complex Integrated Endpoint, which was designed for Embedded Systems with internal-only PCIe Endpoints on bus 0. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Carles Cufí
parent
c714368691
commit
f8f2936dba
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@ -1,6 +1,8 @@
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zephyr_library()
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zephyr_library_sources(pcie.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_CONTROLLER controller.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_ECAM pcie_ecam.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_MSI msi.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_SHELL shell.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_PTM ptm.c)
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@ -14,6 +14,23 @@ module = PCIE
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module-str = pcie
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source "subsys/logging/Kconfig.template.log_config"
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config PCIE_CONTROLLER
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bool "Enable PCIe Controller management"
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help
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Add support for PCIe Controller management when not handled by a
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system firmware like on x86 platforms.
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if PCIE_CONTROLLER
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config PCIE_ECAM
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bool "Enable support for PCIe ECAM Controllers"
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help
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Add support for Enhanced Configuration Address Mapping configured
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PCIe Controllers allowing all outgoing I/O and MEM TLPs to be mapped
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from memory space into any 256 MB region of the PCIe configuration space.
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endif # PCIE_CONTROLLER
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config PCIE_MSI
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bool "Enable support for PCI(e) MSI"
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help
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217
drivers/pcie/host/controller.c
Normal file
217
drivers/pcie/host/controller.c
Normal file
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@ -0,0 +1,217 @@
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/*
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* Copyright (c) 2021 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pcie_core, LOG_LEVEL_INF);
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#include <kernel.h>
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#include <drivers/pcie/pcie.h>
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#include <drivers/pcie/controller.h>
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#if CONFIG_PCIE_MSI
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#include <drivers/pcie/msi.h>
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#endif
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/* arch agnostic PCIe API implementation */
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uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg)
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{
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const struct device *dev;
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dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_pcie_controller));
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if (!dev) {
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LOG_ERR("Failed to get PCIe root complex");
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return 0xffffffff;
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}
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return pcie_ctrl_conf_read(dev, bdf, reg);
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}
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void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, uint32_t data)
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{
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const struct device *dev;
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dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_pcie_controller));
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if (!dev) {
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LOG_ERR("Failed to get PCIe root complex");
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return;
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}
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pcie_ctrl_conf_write(dev, bdf, reg, data);
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}
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uint32_t generic_pcie_ctrl_conf_read(mm_reg_t cfg_addr, pcie_bdf_t bdf, unsigned int reg)
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{
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volatile uint32_t *bdf_cfg_mem = (volatile uint32_t *)((uintptr_t)cfg_addr + (bdf << 4));
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if (!cfg_addr) {
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return 0xffffffff;
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}
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return bdf_cfg_mem[reg];
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}
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void generic_pcie_ctrl_conf_write(mm_reg_t cfg_addr, pcie_bdf_t bdf,
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unsigned int reg, uint32_t data)
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{
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volatile uint32_t *bdf_cfg_mem = (volatile uint32_t *)((uintptr_t)cfg_addr + (bdf << 4));
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if (!cfg_addr) {
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return;
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}
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bdf_cfg_mem[reg] = data;
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}
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static void generic_pcie_ctrl_enumerate_type1(const struct device *ctrl_dev, pcie_bdf_t bdf)
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{
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/* Not yet supported */
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}
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static void generic_pcie_ctrl_type0_enumerate_bars(const struct device *ctrl_dev, pcie_bdf_t bdf)
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{
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unsigned int bar, reg, data;
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uintptr_t scratch, bar_bus_addr;
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size_t size, bar_size;
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for (bar = 0, reg = PCIE_CONF_BAR0; reg <= PCIE_CONF_BAR5; reg ++, bar++) {
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bool found_mem64 = false;
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bool found_mem = false;
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data = scratch = pcie_conf_read(bdf, reg);
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if (PCIE_CONF_BAR_INVAL_FLAGS(data)) {
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continue;
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}
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if (PCIE_CONF_BAR_MEM(data)) {
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found_mem = true;
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if (PCIE_CONF_BAR_64(data)) {
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found_mem64 = true;
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scratch |= ((uint64_t)pcie_conf_read(bdf, reg + 1)) << 32;
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if (PCIE_CONF_BAR_ADDR(scratch) == PCIE_CONF_BAR_INVAL64) {
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continue;
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}
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} else {
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if (PCIE_CONF_BAR_ADDR(scratch) == PCIE_CONF_BAR_INVAL) {
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continue;
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}
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}
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}
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pcie_conf_write(bdf, reg, 0xFFFFFFFF);
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size = pcie_conf_read(bdf, reg);
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pcie_conf_write(bdf, reg, scratch & 0xFFFFFFFF);
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if (found_mem64) {
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pcie_conf_write(bdf, reg + 1, 0xFFFFFFFF);
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size |= ((uint64_t)pcie_conf_read(bdf, reg + 1)) << 32;
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pcie_conf_write(bdf, reg + 1, scratch >> 32);
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}
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if (!PCIE_CONF_BAR_ADDR(size)) {
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if (found_mem64) {
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reg++;
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}
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continue;
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}
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if (found_mem) {
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if (found_mem64) {
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bar_size = (uint64_t)~PCIE_CONF_BAR_ADDR(size) + 1;
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} else {
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bar_size = (uint32_t)~PCIE_CONF_BAR_ADDR(size) + 1;
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}
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} else {
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bar_size = (uint32_t)~PCIE_CONF_BAR_IO_ADDR(size) + 1;
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}
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if (pcie_ctrl_region_allocate(ctrl_dev, bdf, found_mem,
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found_mem64, bar_size, &bar_bus_addr)) {
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uintptr_t bar_phys_addr;
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pcie_ctrl_region_xlate(ctrl_dev, bdf, found_mem,
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found_mem64, bar_bus_addr, &bar_phys_addr);
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LOG_INF("[%02x:%02x.%x] BAR%d size 0x%lx "
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"assigned [%s 0x%lx-0x%lx -> 0x%lx-0x%lx]",
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PCIE_BDF_TO_BUS(bdf), PCIE_BDF_TO_DEV(bdf), PCIE_BDF_TO_FUNC(bdf),
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bar, bar_size,
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found_mem ? (found_mem64 ? "mem64" : "mem") : "io",
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bar_bus_addr, bar_bus_addr + bar_size - 1,
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bar_phys_addr, bar_phys_addr + bar_size - 1);
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pcie_conf_write(bdf, reg, bar_bus_addr & 0xFFFFFFFF);
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if (found_mem64) {
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pcie_conf_write(bdf, reg + 1, bar_bus_addr >> 32);
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}
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} else {
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LOG_INF("[%02x:%02x.%x] BAR%d size 0x%lx Failed memory allocation.",
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PCIE_BDF_TO_BUS(bdf), PCIE_BDF_TO_DEV(bdf), PCIE_BDF_TO_FUNC(bdf),
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bar, bar_size);
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}
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if (found_mem64) {
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reg++;
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}
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}
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}
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static void generic_pcie_ctrl_enumerate_type0(const struct device *ctrl_dev, pcie_bdf_t bdf)
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{
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/* Setup Type0 BARs */
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generic_pcie_ctrl_type0_enumerate_bars(ctrl_dev, bdf);
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}
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void generic_pcie_ctrl_enumerate(const struct device *ctrl_dev, pcie_bdf_t bdf_start)
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{
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uint32_t data, class, id;
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unsigned int dev = PCIE_BDF_TO_DEV(bdf_start),
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func = 0,
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bus = PCIE_BDF_TO_BUS(bdf_start);
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for (; dev <= PCIE_MAX_DEV; dev++) {
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func = 0;
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for (; func <= PCIE_MAX_FUNC; func++) {
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pcie_bdf_t bdf = PCIE_BDF(bus, dev, func);
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bool multifunction_device = false;
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bool layout_type_1 = false;
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id = pcie_conf_read(bdf, PCIE_CONF_ID);
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if (id == PCIE_ID_NONE) {
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continue;
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}
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class = pcie_conf_read(bdf, PCIE_CONF_CLASSREV);
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data = pcie_conf_read(bdf, PCIE_CONF_TYPE);
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multifunction_device = PCIE_CONF_MULTIFUNCTION(data);
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layout_type_1 = PCIE_CONF_TYPE_BRIDGE(data);
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LOG_INF("[%02x:%02x.%x] %04x:%04x class %x subclass %x progif %x "
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"rev %x Type%x multifunction %s",
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PCIE_BDF_TO_BUS(bdf), PCIE_BDF_TO_DEV(bdf), PCIE_BDF_TO_FUNC(bdf),
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id & 0xffff, id >> 16,
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PCIE_CONF_CLASSREV_CLASS(class),
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PCIE_CONF_CLASSREV_SUBCLASS(class),
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PCIE_CONF_CLASSREV_PROGIF(class),
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PCIE_CONF_CLASSREV_REV(class),
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layout_type_1 ? 1 : 0,
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multifunction_device ? "true" : "false");
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if (layout_type_1) {
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generic_pcie_ctrl_enumerate_type1(ctrl_dev, bdf);
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} else {
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generic_pcie_ctrl_enumerate_type0(ctrl_dev, bdf);
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}
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/* Do not enumerate sub-functions if not a multifunction device */
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if (PCIE_BDF_TO_FUNC(bdf) == 0 && !multifunction_device) {
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break;
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}
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}
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}
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}
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@ -5,6 +5,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pcie, LOG_LEVEL_ERR);
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#include <kernel.h>
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#include <stdbool.h>
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#include <drivers/pcie/pcie.h>
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@ -13,6 +16,10 @@
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#include <drivers/pcie/msi.h>
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#endif
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#ifdef CONFIG_PCIE_CONTROLLER
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#include <drivers/pcie/controller.h>
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#endif
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/* functions documented in drivers/pcie/pcie.h */
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bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id)
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@ -101,18 +108,31 @@ bool pcie_get_mbar(pcie_bdf_t bdf,
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struct pcie_mbar *mbar)
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{
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uint32_t reg = bar_index + PCIE_CONF_BAR0;
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#ifdef CONFIG_PCIE_CONTROLLER
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const struct device *dev;
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#endif
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uintptr_t phys_addr;
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size_t size;
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#ifdef CONFIG_PCIE_CONTROLLER
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dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_pcie_controller));
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if (!dev) {
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LOG_ERR("Failed to get PCIe root complex");
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return false;
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}
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#endif
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if (reg > PCIE_CONF_BAR5) {
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return false;
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}
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phys_addr = pcie_conf_read(bdf, reg);
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#ifndef CONFIG_PCIE_CONTROLLER
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if (PCIE_CONF_BAR_IO(phys_addr)) {
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/* Discard I/O bars */
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return false;
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}
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#endif
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if (PCIE_CONF_BAR_INVAL_FLAGS(phys_addr)) {
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/* Discard on invalid flags */
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@ -142,13 +162,33 @@ bool pcie_get_mbar(pcie_bdf_t bdf,
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return false;
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}
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if (PCIE_CONF_BAR_IO(phys_addr)) {
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size = PCIE_CONF_BAR_IO_ADDR(size);
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if (size == 0) {
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/* Discard on invalid size */
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return false;
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}
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} else {
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size = PCIE_CONF_BAR_ADDR(size);
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if (size == 0) {
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/* Discard on invalid size */
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return false;
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}
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}
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#ifdef CONFIG_PCIE_CONTROLLER
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/* Translate to physical memory address from bus address */
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if (!pcie_ctrl_region_xlate(dev, bdf, PCIE_CONF_BAR_MEM(phys_addr),
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PCIE_CONF_BAR_64(phys_addr),
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PCIE_CONF_BAR_MEM(phys_addr) ?
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PCIE_CONF_BAR_IO_ADDR(phys_addr)
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: PCIE_CONF_BAR_ADDR(phys_addr),
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&mbar->phys_addr)) {
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return false;
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}
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#else
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mbar->phys_addr = PCIE_CONF_BAR_ADDR(phys_addr);
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#endif /* CONFIG_PCIE_CONTROLLER */
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mbar->size = size & ~(size-1);
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return true;
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@ -182,6 +222,11 @@ bool pcie_probe_mbar(pcie_bdf_t bdf,
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*/
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#define IRQ_LIST_INITIALIZED 0
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#ifndef CONFIG_MAX_IRQ_LINES
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#warning TOFIX for non-x86
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#define CONFIG_MAX_IRQ_LINES 0
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#endif
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static ATOMIC_DEFINE(irq_reserved, CONFIG_MAX_IRQ_LINES);
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static unsigned int irq_alloc(void)
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293
drivers/pcie/host/pcie_ecam.c
Normal file
293
drivers/pcie/host/pcie_ecam.c
Normal file
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@ -0,0 +1,293 @@
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/*
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* Copyright (c) 2021 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pcie_ecam, LOG_LEVEL_ERR);
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#include <kernel.h>
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#include <device.h>
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#include <drivers/pcie/pcie.h>
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#include <drivers/pcie/controller.h>
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#define DT_DRV_COMPAT pci_host_ecam_generic
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/*
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* PCIe Controllers Regions
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*
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* TOFIX:
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* - handle prefetchable regions
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*/
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enum pcie_region_type {
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PCIE_REGION_IO = 0,
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PCIE_REGION_MEM,
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PCIE_REGION_MEM64,
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PCIE_REGION_MAX,
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};
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struct pcie_ecam_data {
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uintptr_t cfg_phys_addr;
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mm_reg_t cfg_addr;
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size_t cfg_size;
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struct {
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uintptr_t phys_start;
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uintptr_t bus_start;
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size_t size;
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size_t allocation_offset;
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} regions[PCIE_REGION_MAX];
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};
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static int pcie_ecam_init(const struct device *dev)
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{
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const struct pcie_ctrl_config *cfg = (const struct pcie_ctrl_config *)dev->config;
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struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
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int i;
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/*
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* Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 :
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* Bit# 33222222 22221111 11111100 00000000
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* 10987654 32109876 54321098 76543210
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*
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* where:
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*
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* n is 0 if the address is relocatable, 1 otherwise
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* p is 1 if the addressable region is "prefetchable", 0 otherwise
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* t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory),
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* or below 64 KB (for relocatable I/O).
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* ss is the space code, denoting the address space
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* 00 denotes Configuration Space
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* 01 denotes I/O Space
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* 10 denotes 32-bit-address Memory Space
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* 11 denotes 64-bit-address Memory Space
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* bbbbbbbb is the 8-bit Bus Number
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* ddddd is the 5-bit Device Number
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* fff is the 3-bit Function Number
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* rrrrrrrr is the 8-bit Register Number
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* hh...hh is a 32-bit unsigned number
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* ll...ll is a 32-bit unsigned number
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* for I/O Space is the 32-bit offset from the start of the region
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* for 32-bit-address Memory Space is the 32-bit offset from the start of the region
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* for 64-bit-address Memory Space is the 64-bit offset from the start of the region
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*
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* Here we only handle the p, ss, hh and ll fields.
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*
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* TOFIX:
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* - handle prefetchable bit
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*/
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for (i = 0 ; i < cfg->ranges_count ; ++i) {
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switch ((cfg->ranges[i].flags >> 24) & 0x03) {
|
||||
case 0x01:
|
||||
data->regions[PCIE_REGION_IO].bus_start = cfg->ranges[i].pcie_bus_addr;
|
||||
data->regions[PCIE_REGION_IO].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_IO].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_IO].bus_start < 0x1000)
|
||||
data->regions[PCIE_REGION_IO].allocation_offset = 0x1000;
|
||||
break;
|
||||
case 0x02:
|
||||
data->regions[PCIE_REGION_MEM].bus_start = cfg->ranges[i].pcie_bus_addr;
|
||||
data->regions[PCIE_REGION_MEM].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_MEM].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_MEM].bus_start < 0x1000)
|
||||
data->regions[PCIE_REGION_MEM].allocation_offset = 0x1000;
|
||||
break;
|
||||
case 0x03:
|
||||
data->regions[PCIE_REGION_MEM64].bus_start = cfg->ranges[i].pcie_bus_addr;
|
||||
data->regions[PCIE_REGION_MEM64].phys_start = cfg->ranges[i].host_map_addr;
|
||||
data->regions[PCIE_REGION_MEM64].size = cfg->ranges[i].map_length;
|
||||
/* Linux & U-Boot avoids allocating PCI resources from address 0 */
|
||||
if (data->regions[PCIE_REGION_MEM64].bus_start < 0x1000)
|
||||
data->regions[PCIE_REGION_MEM64].allocation_offset = 0x1000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!data->regions[PCIE_REGION_IO].size &&
|
||||
!data->regions[PCIE_REGION_MEM].size &&
|
||||
!data->regions[PCIE_REGION_MEM64].size) {
|
||||
LOG_ERR("No regions defined");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get Config address space physical address & size */
|
||||
data->cfg_phys_addr = cfg->cfg_addr;
|
||||
data->cfg_size = cfg->cfg_size;
|
||||
|
||||
if (data->regions[PCIE_REGION_IO].size) {
|
||||
LOG_DBG("IO bus [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_IO].bus_start,
|
||||
(data->regions[PCIE_REGION_IO].bus_start +
|
||||
data->regions[PCIE_REGION_IO].size - 1),
|
||||
data->regions[PCIE_REGION_IO].size);
|
||||
LOG_DBG("IO space [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_IO].phys_start,
|
||||
(data->regions[PCIE_REGION_IO].phys_start +
|
||||
data->regions[PCIE_REGION_IO].size - 1),
|
||||
data->regions[PCIE_REGION_IO].size);
|
||||
}
|
||||
if (data->regions[PCIE_REGION_MEM].size) {
|
||||
LOG_DBG("MEM bus [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_MEM].bus_start,
|
||||
(data->regions[PCIE_REGION_MEM].bus_start +
|
||||
data->regions[PCIE_REGION_MEM].size - 1),
|
||||
data->regions[PCIE_REGION_MEM].size);
|
||||
LOG_DBG("MEM space [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_MEM].phys_start,
|
||||
(data->regions[PCIE_REGION_MEM].phys_start +
|
||||
data->regions[PCIE_REGION_MEM].size - 1),
|
||||
data->regions[PCIE_REGION_MEM].size);
|
||||
}
|
||||
if (data->regions[PCIE_REGION_MEM64].size) {
|
||||
LOG_DBG("MEM64 bus [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_MEM64].bus_start,
|
||||
(data->regions[PCIE_REGION_MEM64].bus_start +
|
||||
data->regions[PCIE_REGION_MEM64].size - 1),
|
||||
data->regions[PCIE_REGION_MEM64].size);
|
||||
LOG_DBG("MEM64 space [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->regions[PCIE_REGION_MEM64].phys_start,
|
||||
(data->regions[PCIE_REGION_MEM64].phys_start +
|
||||
data->regions[PCIE_REGION_MEM64].size - 1),
|
||||
data->regions[PCIE_REGION_MEM64].size);
|
||||
}
|
||||
|
||||
/* Map config space to be used by the generic_pcie_ctrl_conf_read/write callbacks */
|
||||
device_map(&data->cfg_addr, data->cfg_phys_addr, data->cfg_size, K_MEM_CACHE_NONE);
|
||||
|
||||
LOG_DBG("Config space [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->cfg_phys_addr, (data->cfg_phys_addr + data->cfg_size - 1), data->cfg_size);
|
||||
LOG_DBG("Config mapped [0x%lx - 0x%lx, size 0x%lx]",
|
||||
data->cfg_addr, (data->cfg_addr + data->cfg_size - 1), data->cfg_size);
|
||||
|
||||
generic_pcie_ctrl_enumerate(dev, PCIE_BDF(0, 0, 0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t pcie_ecam_ctrl_conf_read(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
|
||||
{
|
||||
struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
|
||||
|
||||
return generic_pcie_ctrl_conf_read(data->cfg_addr, bdf, reg);
|
||||
}
|
||||
|
||||
static void pcie_ecam_ctrl_conf_write(const struct device *dev, pcie_bdf_t bdf, unsigned int reg,
|
||||
uint32_t reg_data)
|
||||
{
|
||||
struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
|
||||
|
||||
generic_pcie_ctrl_conf_write(data->cfg_addr, bdf, reg, reg_data);
|
||||
}
|
||||
|
||||
static bool pcie_ecam_region_allocate_type(struct pcie_ecam_data *data, pcie_bdf_t bdf,
|
||||
size_t bar_size, uintptr_t *bar_bus_addr,
|
||||
enum pcie_region_type type)
|
||||
{
|
||||
uintptr_t addr;
|
||||
|
||||
addr = (((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) |
|
||||
((bar_size) - 1)) + 1;
|
||||
|
||||
if (addr - data->regions[type].bus_start + bar_size > data->regions[type].size)
|
||||
return false;
|
||||
|
||||
*bar_bus_addr = addr;
|
||||
data->regions[type].allocation_offset = addr - data->regions[type].bus_start + bar_size;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool pcie_ecam_region_allocate(const struct device *dev, pcie_bdf_t bdf,
|
||||
bool mem, bool mem64, size_t bar_size,
|
||||
uintptr_t *bar_bus_addr)
|
||||
{
|
||||
struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
|
||||
enum pcie_region_type type;
|
||||
|
||||
if (mem && !data->regions[PCIE_REGION_MEM64].size &&
|
||||
!data->regions[PCIE_REGION_MEM].size) {
|
||||
LOG_DBG("bdf %x no mem region defined for allocation", bdf);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!mem && !data->regions[PCIE_REGION_IO].size) {
|
||||
LOG_DBG("bdf %x no io region defined for allocation", bdf);
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate into mem64 region if available or is the only available
|
||||
*
|
||||
* TOFIX:
|
||||
* - handle allocation from/to mem/mem64 when a region is full
|
||||
*/
|
||||
if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||
|
||||
(data->regions[PCIE_REGION_MEM64].size &&
|
||||
!data->regions[PCIE_REGION_MEM].size))) {
|
||||
type = PCIE_REGION_MEM64;
|
||||
} else if (mem) {
|
||||
type = PCIE_REGION_MEM;
|
||||
} else {
|
||||
type = PCIE_REGION_IO;
|
||||
}
|
||||
|
||||
return pcie_ecam_region_allocate_type(data, bdf, bar_size, bar_bus_addr, type);
|
||||
}
|
||||
|
||||
static bool pcie_ecam_region_xlate(const struct device *dev, pcie_bdf_t bdf,
|
||||
bool mem, bool mem64, uintptr_t bar_bus_addr,
|
||||
uintptr_t *bar_addr)
|
||||
{
|
||||
struct pcie_ecam_data *data = (struct pcie_ecam_data *)dev->data;
|
||||
enum pcie_region_type type;
|
||||
|
||||
/* Means it hasn't been allocated */
|
||||
if (!bar_bus_addr)
|
||||
return false;
|
||||
|
||||
if (mem && ((mem64 && data->regions[PCIE_REGION_MEM64].size) ||
|
||||
(data->regions[PCIE_REGION_MEM64].size &&
|
||||
!data->regions[PCIE_REGION_MEM].size))) {
|
||||
type = PCIE_REGION_MEM64;
|
||||
} else if (mem) {
|
||||
type = PCIE_REGION_MEM;
|
||||
} else {
|
||||
type = PCIE_REGION_IO;
|
||||
}
|
||||
|
||||
*bar_addr = data->regions[type].phys_start + (bar_bus_addr - data->regions[type].bus_start);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static const struct pcie_ctrl_driver_api pcie_ecam_api = {
|
||||
.conf_read = pcie_ecam_ctrl_conf_read,
|
||||
.conf_write = pcie_ecam_ctrl_conf_write,
|
||||
.region_allocate = pcie_ecam_region_allocate,
|
||||
.region_xlate = pcie_ecam_region_xlate,
|
||||
};
|
||||
|
||||
#define PCIE_ECAM_INIT(n) \
|
||||
static struct pcie_ecam_data pcie_ecam_data##n; \
|
||||
static const struct pcie_ctrl_config pcie_ecam_config##n = { \
|
||||
.cfg_addr = DT_INST_REG_ADDR(n), \
|
||||
.cfg_size = DT_INST_REG_SIZE(n), \
|
||||
.ranges_count = DT_NUM_RANGES(DT_DRV_INST(n)), \
|
||||
.ranges = { \
|
||||
DT_FOREACH_RANGE(DT_DRV_INST(n), PCIE_RANGE_FORMAT) \
|
||||
}, \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(n, &pcie_ecam_init, NULL, \
|
||||
&pcie_ecam_data##n, \
|
||||
&pcie_ecam_config##n, \
|
||||
PRE_KERNEL_1, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
|
||||
&pcie_ecam_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(PCIE_ECAM_INIT)
|
||||
|
|
@ -243,6 +243,7 @@ extern uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id);
|
|||
|
||||
#define PCIE_CONF_TYPE 3U
|
||||
|
||||
#define PCIE_CONF_MULTIFUNCTION(w) (((w) & 0x00800000U) != 0U)
|
||||
#define PCIE_CONF_TYPE_BRIDGE(w) (((w) & 0x007F0000U) != 0U)
|
||||
|
||||
/*
|
||||
|
|
@ -262,6 +263,7 @@ extern uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id);
|
|||
#define PCIE_CONF_BAR_MEM(w) (((w) & 0x00000001U) != 0x00000001U)
|
||||
#define PCIE_CONF_BAR_64(w) (((w) & 0x00000006U) == 0x00000004U)
|
||||
#define PCIE_CONF_BAR_ADDR(w) ((w) & ~0xfUL)
|
||||
#define PCIE_CONF_BAR_IO_ADDR(w) ((w) & ~0x3UL)
|
||||
#define PCIE_CONF_BAR_FLAGS(w) ((w) & 0xfUL)
|
||||
#define PCIE_CONF_BAR_NONE 0U
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue