drivers: serial: Add Infineon CAT1 UART driver
Added initial version of Infineon CAT1 UART driver. Added initial version of binding file for Infineon CAT1 UART driver. Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar
Carles Cufí
parent
81822e0501
commit
f956e81bb6
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@ -50,6 +50,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_NEORV32 uart_neorv32.c)
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zephyr_library_sources_ifdef(CONFIG_USART_GD32 usart_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC uart_hvc_xen.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC_CONSOLEIO uart_hvc_xen_consoleio.c)
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zephyr_library_sources_ifdef(CONFIG_UART_INFINEON_CAT1 uart_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_UART_PIPE uart_pipe.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SMARTBOND uart_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_UART_NXP_S32_LINFLEXD uart_nxp_s32_linflexd.c)
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@ -202,6 +202,8 @@ source "drivers/serial/Kconfig.neorv32"
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source "drivers/serial/Kconfig.xen"
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source "drivers/serial/Kconfig.ifx_cat1"
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source "drivers/serial/Kconfig.smartbond"
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source "drivers/serial/Kconfig.nxp_s32"
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15
drivers/serial/Kconfig.ifx_cat1
Normal file
15
drivers/serial/Kconfig.ifx_cat1
Normal file
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@ -0,0 +1,15 @@
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# Infineon CAT1 UART configuration options
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# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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# SPDX-License-Identifier: Apache-2.0
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config UART_INFINEON_CAT1
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bool "Infineon CAT1 UART driver"
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default y
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depends on DT_HAS_INFINEON_CAT1_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select USE_INFINEON_UART
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help
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This option enables the UART driver for Infineon CAT1 family.
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526
drivers/serial/uart_ifx_cat1.c
Normal file
526
drivers/serial/uart_ifx_cat1.c
Normal file
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@ -0,0 +1,526 @@
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/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief UART driver for Infineon CAT1 MCU family.
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*
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* Note:
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* - Uart ASYNC functionality is not implemented in current
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* version of Uart CAT1 driver.
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*/
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#define DT_DRV_COMPAT infineon_cat1_uart
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <cyhal_uart.h>
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#include <cyhal_utils_psoc.h>
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#include <cyhal_scb_common.h>
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/* Data structure */
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struct ifx_cat1_uart_data {
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cyhal_uart_t obj; /* UART CYHAL object */
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struct uart_config cfg;
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cyhal_resource_inst_t hw_resource;
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cyhal_clock_t clock;
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#if CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb; /* Interrupt Callback */
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void *irq_cb_data; /* Interrupt Callback Arg */
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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/* Device config structure */
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struct ifx_cat1_uart_config {
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const struct pinctrl_dev_config *pcfg;
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CySCB_Type *reg_addr;
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struct uart_config dt_cfg;
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uint8_t irq_priority;
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};
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/* Default Counter configuration structure */
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static const cy_stc_scb_uart_config_t _cyhal_uart_default_config = {
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 12,
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.enableMsbFirst = false,
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.dataWidth = 8UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = false,
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.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
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#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
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.rtsRxFifoLevel = 20UL,
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#elif defined(COMPONENT_CAT2)
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.rtsRxFifoLevel = 3UL,
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#endif
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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/* Level triggers when at least one element is in FIFO */
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.rxFifoTriggerLevel = 0UL,
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.rxFifoIntEnableMask = 0x0UL,
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/* Level triggers when half-fifo is half empty */
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.txFifoTriggerLevel = (CY_SCB_FIFO_SIZE / 2 - 1),
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.txFifoIntEnableMask = 0x0UL
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};
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/* Helper API */
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static cyhal_uart_parity_t _convert_uart_parity_z_to_cyhal(enum uart_config_parity parity)
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{
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cyhal_uart_parity_t cyhal_parity;
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switch (parity) {
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case UART_CFG_PARITY_NONE:
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cyhal_parity = CYHAL_UART_PARITY_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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cyhal_parity = CYHAL_UART_PARITY_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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cyhal_parity = CYHAL_UART_PARITY_EVEN;
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break;
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default:
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cyhal_parity = CYHAL_UART_PARITY_NONE;
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}
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return cyhal_parity;
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}
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static uint32_t _convert_uart_stop_bits_z_to_cyhal(enum uart_config_stop_bits stop_bits)
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{
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uint32_t cyhal_stop_bits;
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switch (stop_bits) {
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case UART_CFG_STOP_BITS_1:
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cyhal_stop_bits = 1u;
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break;
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case UART_CFG_STOP_BITS_2:
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cyhal_stop_bits = 2u;
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break;
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default:
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cyhal_stop_bits = 1u;
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}
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return cyhal_stop_bits;
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}
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static uint32_t _convert_uart_data_bits_z_to_cyhal(enum uart_config_data_bits data_bits)
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{
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uint32_t cyhal_data_bits;
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switch (data_bits) {
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case UART_CFG_DATA_BITS_5:
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cyhal_data_bits = 1u;
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break;
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case UART_CFG_DATA_BITS_6:
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cyhal_data_bits = 6u;
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break;
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case UART_CFG_DATA_BITS_7:
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cyhal_data_bits = 7u;
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break;
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case UART_CFG_DATA_BITS_8:
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cyhal_data_bits = 8u;
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break;
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case UART_CFG_DATA_BITS_9:
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cyhal_data_bits = 9u;
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break;
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default:
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cyhal_data_bits = 1u;
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}
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return cyhal_data_bits;
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}
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static int32_t _get_hw_block_num(CySCB_Type *reg_addr)
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{
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uint32_t i;
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for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
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if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
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return i;
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}
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}
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return -1;
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}
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static int ifx_cat1_uart_poll_in(const struct device *dev, unsigned char *c)
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{
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cy_rslt_t rec;
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struct ifx_cat1_uart_data *data = dev->data;
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rec = cyhal_uart_getc(&data->obj, c, 0u);
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return ((rec == CY_SCB_UART_RX_NO_DATA) ? -1 : 0);
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}
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static void ifx_cat1_uart_poll_out(const struct device *dev, unsigned char c)
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{
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struct ifx_cat1_uart_data *data = dev->data;
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(void) cyhal_uart_putc(&data->obj, (uint32_t)c);
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}
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static int ifx_cat1_uart_err_check(const struct device *dev)
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{
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struct ifx_cat1_uart_data *data = dev->data;
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uint32_t status = Cy_SCB_UART_GetRxFifoStatus(data->obj.base);
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int errors = 0;
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if (status & CY_SCB_UART_RX_OVERFLOW) {
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errors |= UART_ERROR_OVERRUN;
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}
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if (status & CY_SCB_UART_RX_ERR_PARITY) {
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errors |= UART_ERROR_PARITY;
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}
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if (status & CY_SCB_UART_RX_ERR_FRAME) {
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errors |= UART_ERROR_FRAMING;
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}
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return errors;
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}
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static int ifx_cat1_uart_configure(const struct device *dev,
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const struct uart_config *cfg)
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{
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__ASSERT_NO_MSG(cfg != NULL);
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cy_rslt_t result;
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struct ifx_cat1_uart_data *data = dev->data;
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cyhal_uart_cfg_t uart_cfg = {
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.data_bits = _convert_uart_data_bits_z_to_cyhal(cfg->data_bits),
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.stop_bits = _convert_uart_stop_bits_z_to_cyhal(cfg->stop_bits),
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.parity = _convert_uart_parity_z_to_cyhal(cfg->parity)
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};
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/* Store Uart Zephyr configuration (uart config) into data structure */
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data->cfg = *cfg;
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/* Configure parity, data and stop bits */
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result = cyhal_uart_configure(&data->obj, &uart_cfg);
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/* Configure the baud rate */
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if (result == CY_RSLT_SUCCESS) {
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result = cyhal_uart_set_baud(&data->obj, cfg->baudrate, NULL);
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}
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/* Enable RTS/CTS flow control */
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if ((result == CY_RSLT_SUCCESS) && cfg->flow_ctrl) {
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result = cyhal_uart_enable_flow_control(&data->obj, true, true);
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}
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return (result == CY_RSLT_SUCCESS) ? 0 : -ENOTSUP;
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};
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static int ifx_cat1_uart_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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ARG_UNUSED(dev);
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struct ifx_cat1_uart_data *const data = dev->data;
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if (cfg == NULL) {
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return -EINVAL;
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}
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*cfg = data->cfg;
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/* Uart event callback for Interrupt driven mode */
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static void _uart_event_callback_irq_mode(void *arg, cyhal_uart_event_t event)
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{
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ARG_UNUSED(event);
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const struct device *dev = (const struct device *) arg;
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struct ifx_cat1_uart_data *const data = dev->data;
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if (data->irq_cb != NULL) {
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data->irq_cb(dev, data->irq_cb_data);
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}
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}
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/* Fill FIFO with data */
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static int ifx_cat1_uart_fifo_fill(const struct device *dev,
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const uint8_t *tx_data, int size)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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size_t _size = (size_t) size;
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(void)cyhal_uart_write(&data->obj, (uint8_t *) tx_data, &_size);
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return (int) _size;
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}
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/* Read data from FIFO */
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static int ifx_cat1_uart_fifo_read(const struct device *dev,
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uint8_t *rx_data, const int size)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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size_t _size = (size_t) size;
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(void)cyhal_uart_read(&data->obj, rx_data, &_size);
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return (int) _size;
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}
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/* Enable TX interrupt */
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static void ifx_cat1_uart_irq_tx_enable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj,
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(cyhal_uart_event_t) CYHAL_UART_IRQ_TX_EMPTY,
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config->irq_priority, 1);
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}
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/* Disable TX interrupt */
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static void ifx_cat1_uart_irq_tx_disable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj,
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(cyhal_uart_event_t) CYHAL_UART_IRQ_TX_EMPTY,
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config->irq_priority, 0);
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}
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/* Check if UART TX buffer can accept a new char */
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static int ifx_cat1_uart_irq_tx_ready(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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uint32_t mask = Cy_SCB_GetTxInterruptStatusMasked(data->obj.base);
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return (((mask & (CY_SCB_UART_TX_NOT_FULL | SCB_INTR_TX_EMPTY_Msk)) != 0u) ? 1 : 0);
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}
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/* Check if UART TX block finished transmission */
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static int ifx_cat1_uart_irq_tx_complete(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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return (int) !(cyhal_uart_is_tx_active(&data->obj));
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}
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/* Enable RX interrupt */
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static void ifx_cat1_uart_irq_rx_enable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj,
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(cyhal_uart_event_t) CYHAL_UART_IRQ_RX_NOT_EMPTY,
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config->irq_priority, 1);
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}
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/* Disable TX interrupt */
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static void ifx_cat1_uart_irq_rx_disable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj,
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(cyhal_uart_event_t) CYHAL_UART_IRQ_RX_NOT_EMPTY,
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config->irq_priority, 0);
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}
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/* Check if UART RX buffer has a received char */
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static int ifx_cat1_uart_irq_rx_ready(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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return cyhal_uart_readable(&data->obj) ? 1 : 0;
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}
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/* Enable Error interrupts */
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static void ifx_cat1_uart_irq_err_enable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)
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(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
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config->irq_priority, 1);
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}
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/* Disable Error interrupts */
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static void ifx_cat1_uart_irq_err_disable(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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const struct ifx_cat1_uart_config *const config = dev->config;
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cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)
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(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
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config->irq_priority, 0);
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}
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/* Check if any IRQs is pending */
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static int ifx_cat1_uart_irq_is_pending(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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uint32_t intcause = Cy_SCB_GetInterruptCause(data->obj.base);
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return (int) (intcause & (CY_SCB_TX_INTR | CY_SCB_RX_INTR));
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}
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/* Start processing interrupts in ISR.
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* This function should be called the first thing in the ISR. Calling
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* uart_irq_rx_ready(), uart_irq_tx_ready(), uart_irq_tx_complete()
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* allowed only after this.
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*/
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static int ifx_cat1_uart_irq_update(const struct device *dev)
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{
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struct ifx_cat1_uart_data *const data = dev->data;
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int status = 1;
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if (((ifx_cat1_uart_irq_is_pending(dev) & CY_SCB_RX_INTR) != 0u) &&
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(Cy_SCB_UART_GetNumInRxFifo(data->obj.base) == 0u)) {
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status = 0;
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}
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return status;
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}
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static void ifx_cat1_uart_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
|
||||
void *cb_data)
|
||||
{
|
||||
struct ifx_cat1_uart_data *data = dev->data;
|
||||
cyhal_uart_t *uart_obj = &data->obj;
|
||||
|
||||
/* Store user callback info */
|
||||
data->irq_cb = cb;
|
||||
data->irq_cb_data = cb_data;
|
||||
|
||||
/* Register a uart general callback handler */
|
||||
cyhal_uart_register_callback(uart_obj, _uart_event_callback_irq_mode, (void *) dev);
|
||||
}
|
||||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
|
||||
|
||||
static int ifx_cat1_uart_init(const struct device *dev)
|
||||
{
|
||||
struct ifx_cat1_uart_data *const data = dev->data;
|
||||
const struct ifx_cat1_uart_config *const config = dev->config;
|
||||
cy_rslt_t result;
|
||||
int ret;
|
||||
|
||||
cyhal_uart_configurator_t uart_init_cfg = {
|
||||
.resource = &data->hw_resource,
|
||||
.config = &_cyhal_uart_default_config,
|
||||
.clock = &data->clock,
|
||||
};
|
||||
|
||||
/* Dedicate SCB HW resource */
|
||||
data->hw_resource.type = CYHAL_RSC_SCB;
|
||||
data->hw_resource.block_num = _get_hw_block_num(config->reg_addr);
|
||||
|
||||
/* Configure dt provided device signals when available */
|
||||
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Allocates clock for selected IP block */
|
||||
result = _cyhal_utils_allocate_clock(&data->clock, &data->hw_resource,
|
||||
CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT, true);
|
||||
if (result != CY_RSLT_SUCCESS) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Assigns a programmable divider to a selected IP block */
|
||||
en_clk_dst_t clk_idx = _cyhal_scb_get_clock_index(uart_init_cfg.resource->block_num);
|
||||
|
||||
result = _cyhal_utils_peri_pclk_assign_divider(clk_idx, uart_init_cfg.clock);
|
||||
if (result != CY_RSLT_SUCCESS) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Initialize the UART peripheral */
|
||||
result = cyhal_uart_init_cfg(&data->obj, &uart_init_cfg);
|
||||
if (result != CY_RSLT_SUCCESS) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Perform initial Uart configuration */
|
||||
data->obj.is_clock_owned = true;
|
||||
ret = ifx_cat1_uart_configure(dev, &config->dt_cfg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct uart_driver_api ifx_cat1_uart_driver_api = {
|
||||
.poll_in = ifx_cat1_uart_poll_in,
|
||||
.poll_out = ifx_cat1_uart_poll_out,
|
||||
.err_check = ifx_cat1_uart_err_check,
|
||||
|
||||
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
|
||||
.configure = ifx_cat1_uart_configure,
|
||||
.config_get = ifx_cat1_uart_config_get,
|
||||
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
|
||||
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
.fifo_fill = ifx_cat1_uart_fifo_fill,
|
||||
.fifo_read = ifx_cat1_uart_fifo_read,
|
||||
.irq_tx_enable = ifx_cat1_uart_irq_tx_enable,
|
||||
.irq_tx_disable = ifx_cat1_uart_irq_tx_disable,
|
||||
.irq_tx_ready = ifx_cat1_uart_irq_tx_ready,
|
||||
.irq_rx_enable = ifx_cat1_uart_irq_rx_enable,
|
||||
.irq_rx_disable = ifx_cat1_uart_irq_rx_disable,
|
||||
.irq_tx_complete = ifx_cat1_uart_irq_tx_complete,
|
||||
.irq_rx_ready = ifx_cat1_uart_irq_rx_ready,
|
||||
.irq_err_enable = ifx_cat1_uart_irq_err_enable,
|
||||
.irq_err_disable = ifx_cat1_uart_irq_err_disable,
|
||||
.irq_is_pending = ifx_cat1_uart_irq_is_pending,
|
||||
.irq_update = ifx_cat1_uart_irq_update,
|
||||
.irq_callback_set = ifx_cat1_uart_irq_callback_set,
|
||||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
};
|
||||
|
||||
#define INFINEON_CAT1_UART_INIT(n) \
|
||||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
static struct ifx_cat1_uart_data ifx_cat1_uart##n##_data; \
|
||||
\
|
||||
static struct ifx_cat1_uart_config ifx_cat1_uart##n##_cfg = { \
|
||||
.dt_cfg.baudrate = DT_INST_PROP(n, current_speed), \
|
||||
.dt_cfg.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \
|
||||
.dt_cfg.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1), \
|
||||
.dt_cfg.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8), \
|
||||
.dt_cfg.flow_ctrl = DT_INST_PROP(n, hw_flow_control), \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
.reg_addr = (CySCB_Type *)DT_INST_REG_ADDR(n), \
|
||||
.irq_priority = DT_INST_IRQ(n, priority) \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(n, \
|
||||
&ifx_cat1_uart_init, NULL, \
|
||||
&ifx_cat1_uart##n##_data, \
|
||||
&ifx_cat1_uart##n##_cfg, PRE_KERNEL_1, \
|
||||
CONFIG_SERIAL_INIT_PRIORITY, \
|
||||
&ifx_cat1_uart_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_UART_INIT)
|
||||
62
dts/bindings/serial/infineon,cat1-uart.yaml
Normal file
62
dts/bindings/serial/infineon,cat1-uart.yaml
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
# Copyright (c) 2018, Cypress
|
||||
# Copyright (c) 2020, ATL Electronics
|
||||
# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
# an affiliate of Cypress Semiconductor Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Infineon CAT1 UART
|
||||
|
||||
compatible: "infineon,cat1-uart"
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
description: |
|
||||
PORT pin configuration for TX, RX, RTS, CTS signals.
|
||||
We expect that the phandles will reference pinctrl nodes. These
|
||||
nodes will have a nodelabel that matches the Infineon SoC Pinctrl
|
||||
defines and be of the form p<port>_<pin><peripheral inst>_<signal>.
|
||||
|
||||
Examples
|
||||
use TX, RX
|
||||
pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
|
||||
|
||||
use RX only
|
||||
pinctrl-0 = <&p5_0_scb5_uart_rx>;
|
||||
|
||||
use TX, RX, RTS, CTS
|
||||
pinctrl-0 = <&p3_1_scb2_uart_tx &p3_0_scb2_uart_rx
|
||||
&p3_2_scb2_uart_rts &p3_3_scb2_uart_cts>;
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
|
||||
stop-bits:
|
||||
type: string
|
||||
description: |
|
||||
The number of stop bits, refer to uart_config_stop_bits
|
||||
enum:
|
||||
- "0.5"
|
||||
- "1"
|
||||
- "1.5"
|
||||
- "2"
|
||||
|
||||
data-bits:
|
||||
type: int
|
||||
description: |
|
||||
The number of data bits. Refer to enumeration uart_config_data_bits.
|
||||
enum:
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
Loading…
Reference in a new issue