drivers: video: ov2640: add clock rate control property
Add Clock Rate Control property to OV2640 CMOS video sensor Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
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@ -435,6 +435,7 @@ struct ov2640_config {
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#if DT_INST_NODE_HAS_PROP(0, reset_gpios)
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struct gpio_dt_spec reset_gpio;
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#endif
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uint8_t clock_rate_control;
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};
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struct ov2640_data {
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@ -821,7 +822,7 @@ static int ov2640_set_resolution(const struct device *dev,
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/* Set CLKRC */
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ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
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ret |= ov2640_write_reg(&cfg->i2c, CLKRC, 0x87);
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ret |= ov2640_write_reg(&cfg->i2c, CLKRC, cfg->clock_rate_control);
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/* Write DSP input registers */
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ov2640_write_all(dev, uxga_regs, ARRAY_SIZE(uxga_regs));
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@ -1030,6 +1031,7 @@ static const struct ov2640_config ov2640_cfg_0 = {
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#if DT_INST_NODE_HAS_PROP(0, reset_gpios)
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.reset_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
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#endif
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.clock_rate_control = DT_INST_PROP(0, clock_rate_control),
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};
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static struct ov2640_data ov2640_data_0;
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@ -12,4 +12,18 @@ properties:
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The RESETn pin is asserted to disable the sensor causing a hard
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reset. The sensor receives this as an active-low signal.
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clock-rate-control:
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type: int
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default: 0x87
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description: |
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Define the value to the Clock Rate Control register. By changing
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the system clock divide ratio and PLL, the frame rate and pixel
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rate will change together.
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Bit[7] Internal frequency doublers ON/OFF selection.
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0: ON 1: OFF
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Bit[6] Reserved
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Bit[5:0] Clock divider.
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CLK = XVCLK /(decimal value of CLKRC[5:0] + 1)
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include: i2c-device.yaml
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