patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

ext: stm32cube: update stm32f4xx cube version

Browse source 
Update Cube version for STM32F4XX family
from version: V1.15.0
to version: V1.16.0

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-09-15 13:22:52 +02:00 committed by Kumar Gala
parent 653d0242ca
commit faa0aee21a
185 changed files with 862 additions and 627 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
ext/hal/st/stm32cube/stm32f4xx/README
View file

@ -1,4 +1,4 @@
The current version supported in Zephyr for STM32F4 Cube is V1.15.0
The current version supported in Zephyr for STM32F4 Cube is V1.16.0
Patch List:

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/Legacy/stm32_hal_legacy.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32_assert_template.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention

41
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_can.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@ -73,9 +73,13 @@ typedef enum
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
@ -231,7 +235,9 @@ typedef struct
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
@ -253,16 +259,19 @@ typedef struct
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
/**
* @}
*/

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cec.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cec.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_conf.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cortex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_crc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_crc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DCMI Extension HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_def.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dfsdm.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dfsdm.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma2d.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dsi.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dsi.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DSI HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_eth.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ramfunc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FMPI2C HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FMPI2C HAL Extended module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hcd.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention

6
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@ -143,7 +143,7 @@ typedef struct __I2S_HandleTypeDef
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
This parameter can be a value of @ref I2S_ErrorCode */
}I2S_HandleTypeDef;
/**

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_irda.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_irda.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention

8
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_iwdg.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@ -110,10 +110,6 @@ typedef struct
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_lptim.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_lptim.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of LTDC HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_mmc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_mmc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of MMC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nand.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nor.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nor.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pccard.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_qspi.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_qspi.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rng.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SAI Extension HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sd.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sdram.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smartcard.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spdifrx.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spdifrx.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SPDIFRX HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spi.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spi.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sram.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim_ex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_uart.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_usart.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_wwdg.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention

46
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_adc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_adc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of ADC LL module.
******************************************************************************
* @attention
@ -98,8 +98,6 @@ extern "C" {
#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
/* Internal mask for ADC group injected sequencer: */
/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
/* - data register offset */
@ -124,15 +122,6 @@ extern "C" {
#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
/* Definition of ADC group injected sequencer bits information to be inserted */
/* into ADC group injected sequencer ranks literals definition. */
#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
/* Internal mask for ADC group regular trigger: */
/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
/* - regular trigger source */
@ -187,11 +176,6 @@ extern "C" {
#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
/* Internal mask for ADC channel: */
/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
/* - channel identifier defined by number */
@ -264,7 +248,6 @@ extern "C" {
#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
/* Internal mask for ADC analog watchdog: */
/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
/* (concatenation of multiple bits used in different analog watchdogs, */
@ -285,14 +268,9 @@ extern "C" {
#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
/* ADC registers bits positions */
#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
/**
* @}
*/
@ -869,10 +847,10 @@ typedef struct
/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
@ -2944,9 +2922,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
MODIFY_REG(ADCx->JSQR,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
}
/**
@ -3007,9 +2987,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
return (uint32_t)(READ_BIT(ADCx->JSQR,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
>> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
);
}

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_bus.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_bus.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of BUS LL module.
@verbatim

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_cortex.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_cortex.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_crc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_crc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of CRC LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dac.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_dac.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DAC LL module.
******************************************************************************
* @attention

6
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_dma.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
@ -233,7 +233,7 @@ typedef struct
* @}
*/
/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE MODE
/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
* @{
*/
#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma2d.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_dma2d.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of DMA2D LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_exti.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_exti.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fmc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fsmc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_gpio.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_gpio.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_i2c.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_i2c.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of I2C LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_iwdg.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_iwdg.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_lptim.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_lptim.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of LPTIM LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_pwr.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_pwr.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of PWR LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rcc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_rcc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RCC LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rng.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_rng.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RNG LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rtc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_rtc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of RTC LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_sdmmc.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_spi.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_spi.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SPI LL module.
******************************************************************************
* @attention

12
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_system.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_system.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of SYSTEM LL module.
@verbatim
==============================================================================
@ -346,14 +346,6 @@ extern "C" {
* @}
*/
#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
/**
* @}
*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_tim.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_tim.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of TIM LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usart.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usart.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of USART LL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usb.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_utils.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_utils.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================

4
ext/hal/st/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_wwdg.h
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_wwdg.h
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention

12
ext/hal/st/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal.c
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -68,11 +68,11 @@
* @{
*/
/**
* @brief STM32F4xx HAL Driver version number V1.5.0
* @brief STM32F4xx HAL Driver version number V1.7.1
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@ -272,7 +272,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
HAL_SYSTICK_Config(SystemCoreClock/1000U);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
/* Return function status */
return HAL_OK;

4
ext/hal/st/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc.c
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions

4
ext/hal/st/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc_ex.c
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions

613
ext/hal/st/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_can.c
View file

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
* @version V1.7.0
* @date 17-February-2017
* @version V1.7.1
* @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@ -578,15 +578,21 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
}
/* Select one empty transmit mailbox */
@ -636,7 +642,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
/* Get tick */
/* Get tick */
tickstart = HAL_GetTick();
/* Check End of transmission flag */
@ -648,24 +654,33 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
__HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
/* Process unlocked */
__HAL_UNLOCK(hcan);
__HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
return HAL_TIMEOUT;
}
}
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_TX */
hcan->State = HAL_CAN_STATE_READY;
break;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
@ -701,6 +716,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
@ -738,39 +755,49 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
((uint32_t)hcan->pTxMsg->Data[0U]));
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
((uint32_t)hcan->pTxMsg->Data[4U]));
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
else
{
@ -795,24 +822,70 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
uint32_t tickstart = 0U;
CanRxMsgTypeDef* pRxMsg = NULL;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
/* Check if CAN state is not busy for RX FIFO0 */
if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Check if CAN state is not busy for RX FIFO1 */
if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
}
}
/* Get tick */
tickstart = HAL_GetTick();
@ -831,35 +904,45 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
}
}
}
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
/* Set RxMsg pointer */
if(FIFONumber == CAN_FIFO0)
{
hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
pRxMsg = hcan->pRxMsg;
}
else /* FIFONumber == CAN_FIFO1 */
{
pRxMsg = hcan->pRx1Msg;
}
/* Get the Id */
pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (pRxMsg->IDE == CAN_ID_STD)
{
pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the FIFONumber */
hcan->pRxMsg->FIFONumber = FIFONumber;
pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
{
@ -871,18 +954,45 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
/* Release FIFO1 */
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_RX0 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
default: /* HAL_CAN_STATE_BUSY_RX1 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
@ -899,53 +1009,98 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
tmp = hcan->State;
if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
{
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR);
if(FIFONumber == CAN_FIFO0)
{
/* Enable FIFO 0 message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
}
else
{
/* Enable FIFO 1 message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
}
}
else
/* Check if CAN state is not busy for RX FIFO0 */
if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Check if CAN state is not busy for RX FIFO1 */
if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
(hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
return HAL_BUSY;
}
/* Process locked */
__HAL_LOCK(hcan);
/* Change CAN state */
if(FIFONumber == CAN_FIFO0)
{
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
case(HAL_CAN_STATE_BUSY_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
}
}
else /* FIFONumber == CAN_FIFO1 */
{
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
case(HAL_CAN_STATE_BUSY_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
break;
default: /* HAL_CAN_STATE_READY */
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
}
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Enable interrupts: */
/* - Enable Error warning Interrupt */
/* - Enable Error passive Interrupt */
/* - Enable Bus-off Interrupt */
/* - Enable Last error code Interrupt */
/* - Enable Error Interrupt */
/* - Enable Transmit mailbox empty Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME);
/* Process unlocked */
__HAL_UNLOCK(hcan);
if(FIFONumber == CAN_FIFO0)
{
/* Enable FIFO 0 overrun and message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
else
{
/* Enable FIFO 1 overrun and message pending Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
/* Return function status */
return HAL_OK;
}
@ -968,7 +1123,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
/* Request Sleep mode */
hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
/* Sleep mode status */
if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
{
@ -978,8 +1133,8 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
/* Return function status */
return HAL_ERROR;
}
/* Get tick */
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
@ -993,13 +1148,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
return HAL_TIMEOUT;
}
}
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcan);
/* Return function status */
return HAL_OK;
}
@ -1066,7 +1221,32 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
uint32_t errorcode = HAL_CAN_ERROR_NONE;
/* Check Overrun flag for FIFO0 */
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
if(tmp1 && tmp2)
{
/* Set CAN error code to FOV0 error */
errorcode |= HAL_CAN_ERROR_FOV0;
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
}
/* Check Overrun flag for FIFO1 */
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
if(tmp1 && tmp2)
{
/* Set CAN error code to FOV1 error */
errorcode |= HAL_CAN_ERROR_FOV1;
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
}
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
{
@ -1075,11 +1255,27 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
if(tmp1 || tmp2 || tmp3)
{
/* Call transmit function */
CAN_Transmit_IT(hcan);
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
/* Check Transmit success */
if(tmp1 || tmp2 || tmp3)
{
/* Call transmit function */
CAN_Transmit_IT(hcan);
}
else /* Transmit failure */
{
/* Set CAN error code to TXFAIL error */
errorcode |= HAL_CAN_ERROR_TXFAIL;
}
/* Clear transmission status flags (RQCPx and TXOKx) */
SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
}
}
tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
/* Check End of reception flag for FIFO0 */
@ -1088,7 +1284,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO0);
}
tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
/* Check End of reception flag for FIFO1 */
@ -1097,7 +1293,10 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO1);
}
/* Set error code in handle */
hcan->ErrorCode |= errorcode;
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
@ -1176,6 +1375,29 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
/* Disable interrupts: */
/* - Disable Error warning Interrupt */
/* - Disable Error passive Interrupt */
/* - Disable Bus-off Interrupt */
/* - Disable Last error code Interrupt */
/* - Disable Error Interrupt */
/* - Disable FIFO 0 message pending Interrupt */
/* - Disable FIFO 0 Overrun Interrupt */
/* - Disable FIFO 1 message pending Interrupt */
/* - Disable FIFO 1 Overrun Interrupt */
/* - Disable Transmit mailbox empty Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_FMP0|
CAN_IT_FOV0|
CAN_IT_FMP1|
CAN_IT_FOV1|
CAN_IT_TME);
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@ -1231,8 +1453,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
*/
/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
*
* @brief CAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@ -1286,25 +1508,31 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
and Error Interrupts */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR );
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
switch(hcan->State)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_TX */
hcan->State = HAL_CAN_STATE_READY;
break;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
}
/* Transmission complete callback */
HAL_CAN_TxCpltCallback(hcan);
@ -1321,52 +1549,66 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
*/
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Get the Id */
hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
uint32_t tmp1 = 0U;
CanRxMsgTypeDef* pRxMsg = NULL;
/* Set RxMsg pointer */
if(FIFONumber == CAN_FIFO0)
{
hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
pRxMsg = hcan->pRxMsg;
}
else /* FIFONumber == CAN_FIFO1 */
{
pRxMsg = hcan->pRx1Msg;
}
/* Get the Id */
pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (pRxMsg->IDE == CAN_ID_STD)
{
pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FIFONumber */
hcan->pRxMsg->FIFONumber = FIFONumber;
pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
hcan->pRxMsg->Data[0U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
hcan->pRxMsg->Data[1U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
hcan->pRxMsg->Data[2U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
hcan->pRxMsg->Data[3U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
hcan->pRxMsg->Data[4U] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
hcan->pRxMsg->Data[5U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
hcan->pRxMsg->Data[6U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
hcan->pRxMsg->Data[7U] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
/* Disable FIFO 0 message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
/* Disable FIFO 0 overrun and message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
/* Disable FIFO 1 message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
/* Disable FIFO 1 overrun and message pending Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
tmp1 = hcan->State;
if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
{
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
@ -1376,16 +1618,43 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
CAN_IT_LEC |
CAN_IT_ERR);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
/* Change CAN state */
if (FIFONumber == CAN_FIFO0)
{
/* Disable CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX0):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX1;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
break;
default: /* HAL_CAN_STATE_BUSY_RX0 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
else
else /* FIFONumber == CAN_FIFO1 */
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
switch(hcan->State)
{
case(HAL_CAN_STATE_BUSY_TX_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX;
break;
case(HAL_CAN_STATE_BUSY_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_RX0;
break;
case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
break;
default: /* HAL_CAN_STATE_BUSY_RX1 */
hcan->State = HAL_CAN_STATE_READY;
break;
}
}
/* Receive complete callback */

Some files were not shown because too many files have changed in this diff Show more