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log: swo: enable pin control support for swo log backend

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Enable pin control support for SWO log backend, by creating a new
ITM node for the ARM instrumentation trace macrocell. Add pin control
properties under this node, and refactor the swo-req-freq property to be
defined within this node.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-05-25 11:28:29 -05:00 committed by Mahesh Mahadevan
parent d497cca845
commit fcc25dcf0c
12 changed files with 101 additions and 15 deletions
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9
dts/arm/nordic/nrf52810.dtsi
View file

@ -17,7 +17,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

9
dts/arm/nordic/nrf52811.dtsi
View file

@ -21,7 +21,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

9
dts/arm/nordic/nrf52820.dtsi
View file

@ -22,7 +22,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

9
dts/arm/nordic/nrf52832.dtsi
View file

@ -17,7 +17,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

9
dts/arm/nordic/nrf52833.dtsi
View file

@ -21,7 +21,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

9
dts/arm/nordic/nrf52840.dtsi
View file

@ -17,7 +17,14 @@
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
swo-ref-frequency = <32000000>;
#address-cells = <1>;
#size-cells = <1>;
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <32000000>;
};
};
};

7
dts/arm/nordic/nrf5340_cpuapp.dtsi
View file

@ -18,7 +18,12 @@
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
swo-ref-frequency = <64000000>;
itm: itm@e0000000 {
compatible = "arm,armv8m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <64000000>;
};
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";

6
dts/bindings/cpu/arm,cortex-m.yaml
View file

@ -4,9 +4,3 @@
# Common fields for ARM Cortex-M CPU
include: cpu.yaml
properties:
swo-ref-frequency:
type: int
required: false
description: Reference clock frequency for SWO if different than CPU clock.

9
dts/bindings/debug/arm,armv7m-itm.yaml Normal file
View file

@ -0,0 +1,9 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: Apache-2.0
description: |
ARMv7 instrumentation trace macrocell. Used for single wire output (SWO)
compatible: "arm,armv7m-itm"
include: arm,itm.yaml

9
dts/bindings/debug/arm,armv8m-itm.yaml Normal file
View file

@ -0,0 +1,9 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: Apache-2.0
description: |
ARMv8 instrumentation trace macrocell. Used for single wire output (SWO)
compatible: "arm,armv8m-itm"
include: arm,itm.yaml

13
dts/bindings/debug/arm,itm.yaml Normal file
View file

@ -0,0 +1,13 @@
# Copyright 2022 NXP
# SPDX-License-Identifier: Apache-2.0
# Common fields for ARM instrumentation trace macrocell
# Pin control property may be used for SWO pins
include: [base.yaml, pinctrl-device.yaml]
properties:
swo-ref-frequency:
type: int
required: false
description: Reference clock frequency for SWO if different than CPU clock.

18
subsys/logging/log_backend_swo.c
View file

@ -26,19 +26,25 @@
#include <zephyr/logging/log_core.h>
#include <zephyr/logging/log_output.h>
#include <zephyr/logging/log_backend_std.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
/** The stimulus port from which SWO data is received and displayed */
#define ITM_PORT_LOGGER 0
/* If ITM has pin control properties, apply them for SWO pins */
#if DT_NODE_HAS_PROP(DT_NODELABEL(itm), pinctrl_0)
PINCTRL_DT_DEFINE(DT_NODELABEL(itm));
#endif
/* Set TPIU prescaler for the current debug trace clock frequency. */
#if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0
#define SWO_FREQ_DIV 1
#else
/* Set reference frequency which can be custom or cpu frequency. */
#if DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), swo_ref_frequency)
#define SWO_REF_FREQ DT_PROP(DT_PATH(cpus, cpu_0), swo_ref_frequency)
#if DT_NODE_HAS_PROP(DT_NODELABEL(itm), swo_ref_frequency)
#define SWO_REF_FREQ DT_PROP(DT_NODELABEL(itm), swo_ref_frequency)
#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#define SWO_REF_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
#else
@ -114,6 +120,14 @@ static void log_backend_swo_init(struct log_backend const *const backend)
ITM->TCR = 0x0001000D;
/* Enable stimulus port used by the logger */
ITM->TER = 1 << ITM_PORT_LOGGER;
/* Initialize pin control settings, if any are defined */
#if DT_NODE_HAS_PROP(DT_NODELABEL(itm), pinctrl_0)
const struct pinctrl_dev_config *pincfg =
PINCTRL_DT_DEV_CONFIG_GET(DT_NODELABEL(itm));
pinctrl_apply_state(pincfg, PINCTRL_STATE_DEFAULT);
#endif
}
static void log_backend_swo_panic(struct log_backend const *const backend)