drivers: spi: Initial version of the Infineon CAT1 SPI driver
Initial version of Infineon CAT1 SPI Driver supporting synchronous and asynchronous data transfer API Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi
Carles Cufí
parent
5b12b6ab55
commit
fd04f8cc81
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@ -18,3 +18,4 @@ supported:
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- uart
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- i2c
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- watchdog
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- spi
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@ -25,6 +25,9 @@ CONFIG_SERIAL=y
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# Enable pin controller
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CONFIG_PINCTRL=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Enable clock controller
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CONFIG_CLOCK_CONTROL=y
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@ -48,3 +48,4 @@ zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ mspi_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_RTIO spi_rtio.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_ASYNC spi_signal.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_INFINEON_CAT1 spi_ifx_cat1.c)
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@ -133,4 +133,6 @@ source "drivers/spi/Kconfig.ambiq"
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source "drivers/spi/Kconfig.rpi_pico"
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source "drivers/spi/Kconfig.ifx_cat1"
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endif # SPI
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12
drivers/spi/Kconfig.ifx_cat1
Normal file
12
drivers/spi/Kconfig.ifx_cat1
Normal file
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@ -0,0 +1,12 @@
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# Infineon CAT1 SPI configuration options
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# Copyright (c) 2022 Cypress Semiconductor Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config SPI_INFINEON_CAT1
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bool "Infineon CAT1 SPI driver"
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default y
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depends on DT_HAS_INFINEON_CAT1_SPI_ENABLED
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select USE_INFINEON_SPI
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help
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This option enables the SPI driver for Infineon CAT1 family.
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360
drivers/spi/spi_ifx_cat1.c
Normal file
360
drivers/spi/spi_ifx_cat1.c
Normal file
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@ -0,0 +1,360 @@
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/*
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* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT infineon_cat1_spi
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(cat1_spi);
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#include "spi_context.h"
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/kernel.h>
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#include <cyhal_scb_common.h>
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#include <cyhal_spi.h>
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#define IFX_CAT1_SPI_LOCK_TMOUT_MS (30 * 1000)
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#define IFX_CAT1_SPI_DEFAULT_OVERSAMPLE (4)
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#define IFX_CAT1_SPI_MIN_DATA_WIDTH (8)
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#define IFX_CAT1_SPI_MAX_DATA_WIDTH (32)
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/* Device config structure */
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struct ifx_cat1_spi_config {
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CySCB_Type *reg_addr;
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const struct pinctrl_dev_config *pcfg;
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cy_stc_scb_spi_config_t scb_spi_config;
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uint8_t irq_priority;
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};
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/* Data structure */
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struct ifx_cat1_spi_data {
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struct spi_context ctx;
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cyhal_spi_t obj; /* SPI CYHAL object */
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cyhal_resource_inst_t hw_resource;
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uint8_t dfs_value;
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size_t chunk_len;
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};
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static int32_t get_hw_block_num(CySCB_Type *reg_addr)
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{
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uint32_t i;
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for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
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if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
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return i;
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}
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}
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return -ENOMEM;
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}
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static uint8_t get_dfs_value(struct spi_context *ctx)
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{
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switch (SPI_WORD_SIZE_GET(ctx->config->operation)) {
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case 8:
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return 1;
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case 16:
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return 2;
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case 32:
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return 4;
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default:
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return 1;
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}
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}
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static void transfer_chunk(const struct device *dev)
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{
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struct ifx_cat1_spi_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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size_t chunk_len = spi_context_max_continuous_chunk(ctx);
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if (chunk_len == 0) {
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goto exit;
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}
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data->chunk_len = chunk_len;
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cy_rslt_t result = cyhal_spi_transfer_async(
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&data->obj, ctx->tx_buf, spi_context_tx_buf_on(ctx) ? chunk_len : 0, ctx->rx_buf,
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spi_context_rx_buf_on(ctx) ? chunk_len : 0);
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if (result == CY_RSLT_SUCCESS) {
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return;
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}
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ret = -EIO;
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exit:
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, dev, ret);
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}
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static void spi_interrupt_callback(void *arg, cyhal_spi_event_t event)
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{
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const struct device *dev = (const struct device *)arg;
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struct ifx_cat1_spi_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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if (event & CYHAL_SPI_IRQ_ERROR) {
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#if defined(CONFIG_SPI_ASYNC)
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cyhal_spi_abort_async(&data->obj);
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#endif
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spi_context_cs_control(ctx, false);
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spi_context_complete(ctx, dev, -EIO);
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}
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if (event & CYHAL_SPI_IRQ_DONE) {
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spi_context_update_tx(ctx, data->dfs_value, data->chunk_len);
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spi_context_update_rx(ctx, data->dfs_value, data->chunk_len);
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transfer_chunk(dev);
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}
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}
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int spi_config(const struct device *dev, const struct spi_config *spi_cfg)
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{
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cy_rslt_t result;
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struct ifx_cat1_spi_data *const data = dev->data;
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const struct ifx_cat1_spi_config *const config = dev->config;
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cy_stc_scb_spi_config_t scb_spi_config = config->scb_spi_config;
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struct spi_context *ctx = &data->ctx;
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bool spi_mode_cpol = false;
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bool spi_mode_cpha = false;
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/* check if configuration was changed from previous run, if so skip setup again */
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if (spi_context_configured(ctx, spi_cfg)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP) {
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation) > IFX_CAT1_SPI_MAX_DATA_WIDTH) {
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LOG_ERR("Word size %d is greater than %d", SPI_WORD_SIZE_GET(spi_cfg->operation),
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IFX_CAT1_SPI_MAX_DATA_WIDTH);
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return -EINVAL;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation) < IFX_CAT1_SPI_MIN_DATA_WIDTH) {
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LOG_ERR("Word size %d is less than %d", SPI_WORD_SIZE_GET(spi_cfg->operation),
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IFX_CAT1_SPI_MIN_DATA_WIDTH);
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return -EINVAL;
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}
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if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_SLAVE) {
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scb_spi_config.spiMode = CY_SCB_SPI_SLAVE;
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scb_spi_config.oversample = 0;
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scb_spi_config.enableMisoLateSample = false;
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} else {
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scb_spi_config.spiMode = CY_SCB_SPI_MASTER;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) {
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spi_mode_cpol = true;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) {
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spi_mode_cpha = true;
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}
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if (SPI_WORD_SIZE_GET(spi_cfg->operation)) {
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scb_spi_config.txDataWidth = SPI_WORD_SIZE_GET(spi_cfg->operation);
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scb_spi_config.rxDataWidth = SPI_WORD_SIZE_GET(spi_cfg->operation);
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}
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if (spi_mode_cpha) {
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scb_spi_config.sclkMode =
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spi_mode_cpol ? CY_SCB_SPI_CPHA1_CPOL1 : CY_SCB_SPI_CPHA1_CPOL0;
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} else {
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scb_spi_config.sclkMode =
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spi_mode_cpol ? CY_SCB_SPI_CPHA0_CPOL1 : CY_SCB_SPI_CPHA0_CPOL0;
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}
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scb_spi_config.enableMsbFirst = (spi_cfg->operation & SPI_TRANSFER_LSB) ? false : true;
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/* Force free resource */
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if (data->obj.base != NULL) {
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cyhal_spi_free(&data->obj);
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}
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/* Initialize the SPI peripheral */
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cyhal_spi_configurator_t spi_init_cfg = {.resource = &data->hw_resource,
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.config = &scb_spi_config,
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.gpios = {NC, {NC, NC, NC, NC}, NC, NC}};
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result = cyhal_spi_init_cfg(&data->obj, &spi_init_cfg);
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if (result != CY_RSLT_SUCCESS) {
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return -ENOTSUP;
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}
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/* Assigns a programmable divider to a selected IP block */
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en_clk_dst_t clk_idx = _cyhal_scb_get_clock_index(spi_init_cfg.resource->block_num);
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result = _cyhal_utils_peri_pclk_assign_divider(clk_idx, &data->obj.clock);
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if (result != CY_RSLT_SUCCESS) {
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return -ENOTSUP;
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}
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/* Configure Slave select polarity */
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if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_SLAVE) {
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Cy_SCB_SPI_SetActiveSlaveSelectPolarity(data->obj.base, CY_SCB_SPI_SLAVE_SELECT0,
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scb_spi_config.ssPolarity);
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}
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/* Set the data rate */
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result = cyhal_spi_set_frequency(&data->obj, spi_cfg->frequency);
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if (result != CY_RSLT_SUCCESS) {
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return -EIO;
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}
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/* Write 0 when NULL buffer is provided for Tx/Rx */
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data->obj.write_fill = 0;
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/* Register common SPI callback */
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cyhal_spi_register_callback(&data->obj, spi_interrupt_callback, (void *)dev);
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cyhal_spi_enable_event(&data->obj, CYHAL_SPI_IRQ_DONE, config->irq_priority, true);
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/* Store spi config in context */
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ctx->config = spi_cfg;
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data->dfs_value = get_dfs_value(ctx);
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return 0;
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}
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static int transceive(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
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bool asynchronous, spi_callback_t cb, void *userdata)
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{
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int result;
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struct ifx_cat1_spi_data *const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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spi_context_lock(ctx, asynchronous, cb, userdata, spi_cfg);
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result = spi_config(dev, spi_cfg);
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if (result) {
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LOG_ERR("Error in SPI Configuration (result: 0x%x)", result);
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return result;
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}
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, data->dfs_value);
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spi_context_cs_control(ctx, true);
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transfer_chunk(dev);
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result = spi_context_wait_for_completion(&data->ctx);
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spi_context_release(ctx, result);
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return result;
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}
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static int ifx_cat1_spi_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
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}
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#if defined(CONFIG_SPI_ASYNC)
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static int ifx_cat1_spi_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs, spi_callback_t cb,
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void *userdata)
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{
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return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
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}
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#endif
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static int ifx_cat1_spi_release(const struct device *dev, const struct spi_config *spi_cfg)
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{
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struct ifx_cat1_spi_data *const data = dev->data;
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cyhal_spi_free(&data->obj);
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return 0;
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}
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static const struct spi_driver_api ifx_cat1_spi_api = {
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.transceive = ifx_cat1_spi_transceive_sync,
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#if defined(CONFIG_SPI_ASYNC)
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.transceive_async = ifx_cat1_spi_transceive_async,
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#endif
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.release = ifx_cat1_spi_release,
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};
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static int ifx_cat1_spi_init(const struct device *dev)
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{
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struct ifx_cat1_spi_data *const data = dev->data;
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const struct ifx_cat1_spi_config *const config = dev->config;
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int ret;
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/* Dedicate SCB HW resource */
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data->hw_resource.type = CYHAL_RSC_SCB;
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data->hw_resource.block_num = get_hw_block_num(config->reg_addr);
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* Configure slave select (master) */
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spi_context_cs_configure_all(&data->ctx);
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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#define IFX_CAT1_SPI_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static struct ifx_cat1_spi_data spi_cat1_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_cat1_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_cat1_data_##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)}; \
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static struct ifx_cat1_spi_config spi_cat1_config_##n = { \
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.reg_addr = (CySCB_Type *)DT_INST_REG_ADDR(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.scb_spi_config = \
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{.spiMode = CY_SCB_SPI_MASTER, /* overwrite by cfg */ \
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.sclkMode = CY_SCB_SPI_CPHA0_CPOL0, /* overwrite by cfg */ \
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.rxDataWidth = 8, /* overwrite by cfg */ \
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.txDataWidth = 8, /* overwrite by cfg */ \
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.enableMsbFirst = true, /* overwrite by cfg */ \
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.subMode = DT_INST_PROP_OR(n, sub_mode, CY_SCB_SPI_MOTOROLA), \
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.oversample = \
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DT_INST_PROP_OR(n, oversample, IFX_CAT1_SPI_DEFAULT_OVERSAMPLE), \
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.enableFreeRunSclk = DT_INST_PROP_OR(n, enable_free_run_sclk, false), \
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.enableInputFilter = DT_INST_PROP_OR(n, enable_input_filter, false), \
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.enableMisoLateSample = \
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DT_INST_PROP_OR(n, enable_miso_late_sample, true), \
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.enableTransferSeperation = \
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DT_INST_PROP_OR(n, enable_transfer_seperation, false), \
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.enableWakeFromSleep = DT_INST_PROP_OR(n, enableWakeFromSleep, false), \
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.ssPolarity = DT_INST_PROP_OR(n, ss_polarity, CY_SCB_SPI_ACTIVE_LOW), \
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.rxFifoTriggerLevel = DT_INST_PROP_OR(n, rx_fifo_trigger_level, 0), \
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.rxFifoIntEnableMask = DT_INST_PROP_OR(n, rx_fifo_int_enable_mask, 0), \
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.txFifoTriggerLevel = DT_INST_PROP_OR(n, tx_fifo_trigger_level, 0), \
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.txFifoIntEnableMask = DT_INST_PROP_OR(n, tx_fifo_int_enable_mask, 0), \
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.masterSlaveIntEnableMask = \
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DT_INST_PROP_OR(n, master_slave_int_enable_mask, 0)}, \
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\
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.irq_priority = DT_INST_IRQ(n, priority), \
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}; \
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DEVICE_DT_INST_DEFINE(n, &ifx_cat1_spi_init, NULL, &spi_cat1_data_##n, \
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&spi_cat1_config_##n, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &ifx_cat1_spi_api);
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DT_INST_FOREACH_STATUS_OKAY(IFX_CAT1_SPI_INIT)
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20
dts/bindings/spi/infineon,cat1-spi.yaml
Normal file
20
dts/bindings/spi/infineon,cat1-spi.yaml
Normal file
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@ -0,0 +1,20 @@
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# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Infineon CAT1 SPI
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compatible: "infineon,cat1-spi"
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include: [spi-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
spi1: &scb3 {
|
||||
compatible = "infineon,cat1-spi";
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&p6_0_scb3_spi_m_mosi &p6_1_scb3_spi_m_miso &p6_2_scb3_spi_m_clk>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
slow@0 {
|
||||
compatible = "test-spi-loopback-slow";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <2000000>;
|
||||
};
|
||||
fast@0 {
|
||||
compatible = "test-spi-loopback-fast";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_prt6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
/* Configure pin control bias mode for SPI pins */
|
||||
p6_0_scb3_spi_m_mosi: p6_0_scb3_spi_m_mosi {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_8)>;
|
||||
drive-push-pull;
|
||||
};
|
||||
|
||||
p6_1_scb3_spi_m_miso: p6_1_scb3_spi_m_miso {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_8)>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
p6_2_scb3_spi_m_clk: p6_2_scb3_spi_m_clk {
|
||||
pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_8)>;
|
||||
drive-push-pull;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
&pinctrl {
|
||||
/* Configure pin control bias mode for SPI pins (MASTER) */
|
||||
p10_0_scb1_spi_m_mosi: p10_0_scb1_spi_m_mosi {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_8)>;
|
||||
drive-push-pull;
|
||||
};
|
||||
|
||||
p10_1_scb1_spi_m_miso: p10_1_scb1_spi_m_miso {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_8)>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
p10_2_scb1_spi_m_clk: p10_2_scb1_spi_m_clk {
|
||||
pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_8)>;
|
||||
drive-push-pull;
|
||||
};
|
||||
};
|
||||
|
||||
spi: &scb1 {
|
||||
compatible = "infineon,cat1-spi";
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&p10_0_scb1_spi_m_mosi &p10_1_scb1_spi_m_miso &p10_2_scb1_spi_m_clk>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio_prt10 3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
slow@0 {
|
||||
compatible = "test-spi-loopback-slow";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <200000>;
|
||||
};
|
||||
|
||||
fast@0 {
|
||||
compatible = "test-spi-loopback-fast";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_prt10 {
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in a new issue